JPS60171540A - Integrated circuit - Google Patents

Integrated circuit

Info

Publication number
JPS60171540A
JPS60171540A JP59026664A JP2666484A JPS60171540A JP S60171540 A JPS60171540 A JP S60171540A JP 59026664 A JP59026664 A JP 59026664A JP 2666484 A JP2666484 A JP 2666484A JP S60171540 A JPS60171540 A JP S60171540A
Authority
JP
Japan
Prior art keywords
circuit
register
integrated circuit
signal
control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59026664A
Other languages
Japanese (ja)
Inventor
Katsuji Hosoda
細田 勝司
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP59026664A priority Critical patent/JPS60171540A/en
Publication of JPS60171540A publication Critical patent/JPS60171540A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/006Identification

Abstract

PURPOSE:To identify an integrated circuit IC by providing a read-only discrimination lable register storing the coded information inside the IC and reading electronically this register from outside. CONSTITUTION:An instruction is put on a control signal 10 to read out an ID register 70 storing the identification label ID information (name of IC, number of plates, working speed, name of maker, etc.) of an IC. Then a control circuit 30 decodes said instruction and turns on an output instruction signal 52 to deliver the contents of the register 70 onto a data bus signal 20. A data buffer circuit 40 is set at a high impedance by a data buffer control signal 52 given from the circuit 30. Therefore the signal 20 is never affected by the circuit 40. While the register 70 is set at a high impedance under the control of the circuit 30 when the circuit 40 is kept active.

Description

【発明の詳細な説明】 本発明は、マイクロコンピュータから超大型コンピュー
タにいたるあらゆる14報処理装置に使用される集積回
路の回路構成に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a circuit configuration of an integrated circuit used in all 14-information processing devices ranging from microcomputers to very large computers.

本発明の目的は、今までは集47目り1路メーカによっ
て集積回路のケースに印刷された英数字からのみ集積1
o回路の品名を「沼識していたのを、集積回路の内部に
該集イイ回路の名称、版数、動作速度そしてメーカ名等
の符号化した情報を貯えた読み出し専用ルジスタ(ID
レジスタ)を設け、外部から電子的に該レジスタを読み
出すことによって、集積回路を識別できるようにした回
路構成をもつ集積回路を供給することにある。
It is an object of the present invention to solve the problem that hitherto only the alphanumeric characters printed on the case of an integrated circuit by the manufacturer of the integrated circuit can be used.
The product name of the o-circuit was previously known as a read-only register (ID
An object of the present invention is to provide an integrated circuit having a circuit configuration in which the integrated circuit can be identified by providing a register (register) and reading out the register electronically from the outside.

本発明によれば、制御信号とデータバス信号を入出力と
する専用及び汎用型集積回路であって、制御回路、デー
タバッファ回路、データ処理回路等の基本構成要素の上
に、前記データバス信号に接続した■l) (Iden
tification )レジスタを新しく備えること
により5制御信号を前記II)レジスタの内容をデータ
バス信号に出力する様にすると、本集積回路の名称、版
数、動作速度、メーカ名等の符号化したII)情報を得
ることができ、集積回路単体時には集積回路に適応する
テストプログラムの自動選別と実行等が、又、装置6組
込み時罠は誤実装のチェックや集積回路の版数やメーカ
識別による診断プログラムの自動分岐等が実施可能とな
る集積回路が提供される。
According to the present invention, there is provided a dedicated and general-purpose integrated circuit that inputs and outputs control signals and data bus signals, and the data bus signal ■l) (Iden
By providing a new register, the contents of the above-mentioned II) register can be output to the data bus signal. Information can be obtained, such as automatic selection and execution of test programs suitable for the integrated circuit when a single integrated circuit is used, and diagnostic programs that check for incorrect mounting and identify the version number and manufacturer of the integrated circuit when installing the device 6. Provided is an integrated circuit that can perform automatic branching and the like.

次に、本発明の実施例について図面を参照して説明する
Next, embodiments of the present invention will be described with reference to the drawings.

第1図はこの発明の集積回路の一実施例を示1−たブロ
ック図である。第1図の実施例における回路は、アドレ
ス、ライト及びリード信号等からなるfltll側+(
8号10、データバス信号20、制御信号10を人出力
とする制御部回路30、データバス信号20を入出力と
し制御回路30の出力のデータバッファ1ltjl r
Illl信号51によりデータのfAf、れを制御さi
する3ステート双方向のデータバラ“7ア回路40、f
lj制御回路30からのタイミング制御信号50および
データバッファ回路40からの内部データバス信号60
全入出力とするデータ処理回路100とを基本414成
とする専用及び汎用型集積回路であって、制御回路30
からの出力命令信号52によりデータバス信号20上に
集積回路の名称、版数、動作速度、メーカ名等のID情
報を出力する3ステートの読み出し専用のIDレジスタ
70が新1−<追加されている。
FIG. 1 is a block diagram showing one embodiment of an integrated circuit according to the present invention. The circuit in the embodiment of FIG. 1 consists of address, write, read signals, etc.
No. 8 10, data bus signal 20, control circuit 30 which uses control signal 10 as human output, data buffer 1ltjl r which uses data bus signal 20 as input and output and outputs from control circuit 30
The data fAf is controlled by the Illll signal 51.
3-state bidirectional data rose “7a circuit 40, f
Timing control signal 50 from lj control circuit 30 and internal data bus signal 60 from data buffer circuit 40
It is a dedicated and general-purpose integrated circuit basically consisting of 414 data processing circuits 100 as all inputs and outputs, and a control circuit 30.
A new 3-state read-only ID register 70 has been added that outputs ID information such as the name, version number, operating speed, and manufacturer name of the integrated circuit on the data bus signal 20 in response to an output command signal 52 from the There is.

第1図の実施例の構成から明確なように、本発明は一般
的な専用及び汎用型集積回路に読み出し専用のIDレジ
スタが追加されている点が構成上大き々特徴となってい
る。以F読み出し専用のIDレジスタを取付けた目的及
び使用法について説明する。第2図に本集積回路に関す
る種々の情報を貯えている読み出し専用の16ビツトの
10レジスタのフォーマット例を示す。第2図は、12
ビツト(ビット4〜ビツト15)f名称を示すビットに
、2ビツト(ビット2〜ピツド3)を動作速度を示すビ
ットに、残υの2ピツト(ビット0〜ピツト1)を集積
回路の機能の追加等の履歴即ち版数を示すビットに、そ
れぞれフォーマットしたIDレジスタの例である。第1
図及び第2図に示したIIJIDレジスタのようにして
使用する。
As is clear from the configuration of the embodiment shown in FIG. 1, the present invention is largely characterized in that a read-only ID register is added to a general purpose-built and general-purpose integrated circuit. The purpose and usage of the F read-only ID register will be explained below. FIG. 2 shows an example of the format of ten read-only 16-bit registers that store various information regarding the integrated circuit. Figure 2 shows 12
Bits (bits 4 to 15) f indicate the name, 2 bits (bits 2 to 3) indicate the operating speed, and the remaining 2 bits (bits 0 to 1) indicate the function of the integrated circuit. This is an example of an ID register formatted into bits indicating the history of additions, ie, the version number. 1st
It is used like the IIJID register shown in FIG.

第1図において、制御信号10に集積回路のID情報を
貯えているIDレジスタ70を読み出す為の命令をのせ
ると、制御回路30で本命令を解読して、出力命令信号
52をONにLIDレジスタ70の内容をデータバス信
号20上に出力する。
In FIG. 1, when a command to read the ID register 70 storing ID information of the integrated circuit is placed on the control signal 10, the control circuit 30 decodes this command and turns the output command signal 52 ON. The contents of register 70 are output on data bus signal 20.

なおこの時、データバッファ回路40は、制御回路30
からのデータバッファ制御信号52によシハイインピー
ダンス状態になるために、データバス信号20には影響
を与えない。逆にデータバッファ回路40が動作してい
る時、IDレジスタ70はハーイインピーダンス状態に
なるように制憫j回路30により制御される。
Note that at this time, the data buffer circuit 40 is connected to the control circuit 30.
The data bus signal 20 is not affected because it enters a high impedance state due to the data buffer control signal 52 from the data buffer control signal 52 . Conversely, when the data buffer circuit 40 is operating, the ID register 70 is controlled by the limit j circuit 30 to be in a high impedance state.

以上から明らかなように、本発明に示す如く集積回路に
関するID情報を貯えておく IDレジスタをイ」加す
ると、次のような種々の利点及び今後の発展が見込まれ
る。
As is clear from the above, the following various advantages and future developments can be expected by adding an ID register for storing ID information regarding integrated circuits as shown in the present invention.

まず集積回路メーカ側における利点として次のことがあ
けられる。
First, the advantages for integrated circuit manufacturers are as follows.

(イ)、同一端子数の集積回路でIDレジスタをアクセ
スするのに必要な制御信号とデータ信号の入出力端子の
割振シを規格化すれば、同一端子数の集積回路の範囲内
で多品種の自動テストが可能になる。
(b) If we standardize the allocation of input/output terminals for control signals and data signals necessary to access the ID register in integrated circuits with the same number of terminals, it is possible to automatic testing becomes possible.

(ロ)、従って上記(イ)に示した条件下ではFA (
Factory Automation )化が簡単に
実現できる。
(b) Therefore, under the conditions shown in (b) above, FA (
Factory Automation) can be easily realized.

次に集積回路のユーザ側における利点としては次の点が
あげられる。
Next, the advantages of integrated circuits for users include the following points.

(イ)、集積回路の受入れ検査時において版数の違いに
よるトラブルが避けられ検査の自動化が可能となる。
(b) Troubles due to differences in version numbers can be avoided during acceptance inspection of integrated circuits, and inspection can be automated.

(CI) 、装置又はプリント基板に実装された状態で
誤実装のチェックが電子的に可能となる。
(CI) makes it possible to electronically check for incorrect mounting when mounted on a device or printed circuit board.

(ハ)、集積回路の機能が追加されたときに、IDレジ
スタの内容を読みだすことによシ、その機能の有無をチ
ェックできるので、装置の機能の管理も電子的に可能と
なる。
(c) When a function of an integrated circuit is added, the presence or absence of the function can be checked by reading the contents of the ID register, so that the functions of the device can be managed electronically.

以上の如く本発明は集積回路の入出力端子の割付けが規
格化されない場合でも利点が多く、もし規格化されれば
格段の利点を発揮する。又、現在t’sとんどの電子回
路が集積回路化されつつあるが、本発明の概念が入出力
端子の機能割付けの規格化の働きかけにもなり得る。規
格化が実現すれば、集積回路の品種の急激な増加に悩む
メーカ及びユーザにとって大きな救いとなシ、更に大き
な発展を促すことになる。
As described above, the present invention has many advantages even when the assignment of input/output terminals of an integrated circuit is not standardized, and if it is standardized, it will exhibit significant advantages. Furthermore, although most electronic circuits are now being integrated into integrated circuits, the concept of the present invention can also be used to standardize the functional assignment of input/output terminals. If standardization is achieved, it will be a great relief to manufacturers and users who are suffering from the rapid increase in the variety of integrated circuits, and it will encourage even greater development.

本発明は以上説明したように、制御信号とデータバス信
号を人出力とする専用及び汎用型集積口ME IDレジ
スタを付加することにより、本集積回路の名称1版数、
動作速度、メーカ等の符号化しlこID情報を得ること
ができる為、診断プログラムの自動選別、集積回路の誤
実装のチェック等が人手を介さないで電子的に行うこと
ができる。
As explained above, the present invention adds dedicated and general-purpose integration port ME ID registers for human output of control signals and data bus signals, so that the name and version number of the integrated circuit can be changed.
Since encoded ID information such as operating speed and manufacturer can be obtained, automatic selection of diagnostic programs, checking for incorrect mounting of integrated circuits, etc. can be performed electronically without human intervention.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明に係る集積回路の一実/1m例のブロッ
ク図、第2図は本発明の集積回路の構1戊装素であるI
IJIDレジスタォーマットの一例を示(7た図である
。 lO・・・制φ11信号、20・・データバス信号、3
0・・・制御i’I11 回路、 40 ・データバツ
7ア回路。 50・・・タイミング制御信と、 51・・・データバッファjlj制御4m吋、52・・
・出力命令イci号、 60・・・内部データバス信号、 70・・・IDレジスタ。 代理人 弁理士 染川利°吉
FIG. 1 is a block diagram of one example of an integrated circuit according to the present invention/1 m, and FIG. 2 is a block diagram of an integrated circuit according to the present invention.
An example of the IJID register format is shown (Fig. 7). lO... control φ11 signal, 20... data bus signal,
0...Control i'I11 circuit, 40 ・Data bus 7a circuit. 50...Timing control signal, 51...Data buffer jlj control 4 m x, 52...
- Output instruction No. 1, 60... Internal data bus signal, 70... ID register. Agent Patent Attorney Rikichi Somekawa

Claims (1)

【特許請求の範囲】[Claims] 制御信号とデータバス信号を人出力とする専用及び汎用
型集積回路において、制御回路、データバッファ回路、
データ処理回路等の基本回路構成要素の上に、該集積回
路に関する符号化した1iv報を蓄積した複数ビットか
らなる読み出し専用のIDレジスタを具備し、前記制御
信号により該IDレジスタ内の情報を前記データバス信
号上に読み出すように(−たことをl特徴とする集積回
路。
In dedicated and general-purpose integrated circuits that output control signals and data bus signals, control circuits, data buffer circuits,
A read-only ID register consisting of a plurality of bits that stores encoded information regarding the integrated circuit is provided on basic circuit components such as a data processing circuit, and the information in the ID register is read by the control signal. An integrated circuit characterized in that it is read out on a data bus signal.
JP59026664A 1984-02-15 1984-02-15 Integrated circuit Pending JPS60171540A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59026664A JPS60171540A (en) 1984-02-15 1984-02-15 Integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59026664A JPS60171540A (en) 1984-02-15 1984-02-15 Integrated circuit

Publications (1)

Publication Number Publication Date
JPS60171540A true JPS60171540A (en) 1985-09-05

Family

ID=12199671

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59026664A Pending JPS60171540A (en) 1984-02-15 1984-02-15 Integrated circuit

Country Status (1)

Country Link
JP (1) JPS60171540A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000065598A1 (en) * 1999-04-27 2000-11-02 Seiko Epson Corporation Integrated circuit
JP2006053943A (en) * 1992-08-31 2006-02-23 Intel Corp Identification device for identifying microprocessor, and method of identifying microprocessor

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006053943A (en) * 1992-08-31 2006-02-23 Intel Corp Identification device for identifying microprocessor, and method of identifying microprocessor
JP4723965B2 (en) * 1992-08-31 2011-07-13 インテル・コーポレーション Identification device for identifying a microprocessor
WO2000065598A1 (en) * 1999-04-27 2000-11-02 Seiko Epson Corporation Integrated circuit
US6889299B1 (en) 1999-04-27 2005-05-03 Seiko Epson Corporation Semiconductor integrated circuit

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