JPS60138661A - Processor control system - Google Patents

Abstract

PURPOSE:To attain the use of a memory having an optional access time without reducing the procesing speed of a processor, by setting the send-back timing of an answer signal by the processor itself to an access request to a memory. CONSTITUTION:An answer signal RDY control circuit 1 sends an RDY signal corresponding to the access time of a memory to receive an access back to a processor 2 against a processor request PRQ signal given from the processor 2. In other words, the send-back timing (queuing cycle number) of the RDY signal is supplied to the circuit 1 in the form of the set data supplied from the processor 2. Thus the timing can be decided by a processor itself. As a result, the processor 2 can use a memory of a low speed and low cost with a system having no inconvenience with low performance then, a memory of a high speed and high cost with a system requiring high performance respectively. In such a way, memory having an optional access time without reducing the processing speed can be used by setting the send-back timing of the RDY signal by the processor itself.

Description

Detailed Description of the Invention fa+ Technical Field of the Invention The present invention relates to a system in which a processing unit (CPU) sequentially outputs a program stored in a memory to execute a predetermined process. The present invention relates to a control method for a processing device that makes it possible to adjust the capacity.

(b) Prior Art and Problems Conventionally, the access time for accessing a memory or the like based on a request from a CPU has been fixed, and high speed has generally been desired.

However, not all users necessarily require high-speed processing, and even if low-cost memory with a long access time is sufficient for the purpose, it may not be possible to easily connect it to a CPU and use it. There were times when it was difficult to do. For this reason, there has been a problem in that it is difficult to provide a computer system with high cost performance that meets the user's application.

FIG. 1 is a diagram illustrating a conventional memory access operation.

1 shows a CLK signal waveform, that is, a clock signal waveform for synchronously controlling a CPU, etc., and shows a series of signal waveforms in which a memory, etc. is accessed in cycles T1 to T4.

Figure 1 ■ shows the PRQ signal waveform, that is, the processor request signal (PRQ) that requests access from the CPU to memory, etc.
Signal) 71L type is shown, and the signal waveform at which an access operation of a memory or the like is started based on the PRQ signal is shown.

Figure 1 ■ shows the data waveform, for example, DO to D15.
The state wave in which data consisting of is read from memory and supplied to the CPU is shown. The illustrated memory access time and Ecc (error check) time are required for the data to be effectively read by the CPU. The memory access time is the time during which data is read from the memory, and the ECC time is the time required to check the read data for errors and to automatically correct any errors.

Figure 1 ■ is the RDY (re a dy) signal waveform,
Immediately, the signal waveform of the memory etc. is shown in response to an access request from the CPU. Based on the RDY signal, the CPU outputs the data at the falling edge of the next machine cycle T4 (Fig. 1 ■)
Read.

As described above, the conventional CPtJ is generally intended to access memory, etc. using a fixed predetermined machine cycle, in the example described above, four machine cycles, and to perform as high-speed operation as possible. For this reason, it has been difficult to use, for example, an inexpensive memory with a slow access time in accordance with the user's application with a simple configuration. Furthermore, if the speed of the CPU's machine cycle is reduced in order to connect to memory, etc. that has a slow access time, the high-speed processing ability of the CPU will be reduced, which will reduce the cost performance of the computer system. There was a problem in that it became impossible to maintain the maintenance side due to the high cost.

(C1 Purpose of the Invention The purpose of the present invention is to solve the above-mentioned conventional problems.
An object of the present invention is to provide a control method for a processing device that allows the use of memory having an arbitrary access time without reducing the processing speed of the processing device.

(dl) Configuration of the Invention In order to achieve the above object, the present invention is configured such that the processing device (program) itself can set the return timing of a response signal (ready signal) in response to a memory access request.

The present invention will be explained in detail below using Examples.

tel Embodiment of the Invention FIG. 2 is an embodiment of the present invention, FIG. 3 is an explanatory diagram explaining the operation of one embodiment of the present invention shown in FIG. 2, and FIG. 4 is an illustration of the RDY control circuit shown in FIG. 2. Specific Circuit Example: FIG. 5 is an explanatory diagram illustrating the operation of a specific circuit example of the RDY control circuit shown in FIG. 4.

In the figure, 1 is an RD and Y control circuit, 2 is a CPU, 3 is a memory jlil control circuit, 4 is a memory block consisting of a RAM that stores a program, 5 is an Ecc control circuit, 6 is a PRQ signal input terminal, 7 is the RDY signal output terminal, 8.1
3 is a flip-flop circuit at J-, 9 is a counter, 10
11 represents a comparator, 11 represents a setting register, and 12.14 represents an AND circuit.

The RDY control circuit 1 responds to the PRQ signal from the CPtJ2 by controlling the RD according to the access time of the memory to be accessed.
This is a circuit for returning the 'l' signal to the CPU2. In this embodiment, the return timing of this RDY signal (the number of standby cycles to be described later) is determined by the CPU 2 (i.e., the program).
The configuration is such that it is supplied to the RDY control circuit 1 as setting data from the RDY control circuit 1. Specifically, CPU2 is ■P
From L processing (i.e. ROM program processing) to continuous processing (
When transitioning to RAM program processing), this standby cycle number data is set. As a result, low-speed/low-cost memory can be used in a system where a low performance CPU 2 is sufficient, and high-speed/high-cost memory can be used in a system that requires high performance.

The memory control circuit 3 to which the PRQ signal is input supplies, for example, a read signal or an address signal for reading to the memory block 4. Then, after a predetermined access time has elapsed, predetermined data is read from the memory block 4 and input to the Ecc control circuit 5. The ECC control circuit 5 detects whether or not there is an error in the read data using an error detection bit included in the read data, and if there is an error, performs processing such as automatic correction. After the ash amount is processed by the Ecc control circuit 5, the CPU 2 reads the data, thereby completing the series of accesses.

Further, the CPU 2 can also write predetermined data into the memory block 4 via the Ecc control circuit 5.

Figure 3 ■ shows the CLK signal waveform, and the machine cycle TI
, ``r2. T3. T4.'' and Tw. Tw indicates a state in which the CPU 2 is in a standby machine cycle.

3 shows the waveform of the I) RQ signal that requests access from the CPU 2 to the memory, etc.

Figure 3 ■ shows data DO or D read out from memory.
15, and the data output signal waveform from the Ecc control circuit 5 is shown. The time for the CPU 2 to read data DO to D15 from the data output signal waveform is the memory access time for reading data from the memory block 4 and the Ecc time required for checking the read data for errors. It will be a time of peace with. E
By spending the cc time, the reliability of the read data is increased.

3 is the RDY signal waveform, and at the falling edge of the next machine cycle after which the RDY signal waveform was sent (falling edge of machine cycle T4), the CPU 2 receives the data D.
The signal waveform for reading O to D15 (Figure 3) is shown. In the case shown in FIG. 3, the timing of issuing the RDY signal is delayed by one cycle compared to the case shown in FIG. The RDY control circuit 1 uses tl to notify the CPU of the timing.

FIG. 4 shows a specific circuit example of the RDY control circuit 1 shown in FIG. 3. PRQ signal PRQ signal.

By inputting the RDY signal to the input terminal 6, the RDY signal is outputted from the RDY signal output terminal 7 after being delayed by the number of standby cycles Tw set in advance by the flow column. The operation will be explained in detail below using FIG.

First, when executing the program in the memory block 4, the CPU 2 writes standby cycle number data to the setting register 11 together with the write signal WRIT. This standby cycle number data is a value that corresponds to the access time of the memory block 4 installed in the system (i.e., the time from when the PRQ signal is sent to when it can actually be accessed). This is set by

When this setting is completed, the CPU 2 outputs a PRQ signal for program execution.

When the PRQ signal (■ in Figure 5) is input to the PRQ input signal terminal 6, the flip-flop circuit 8 is set at the falling edge of the T1 cycle of the CLK signal and outputs an H level FO multiplied signal (the Figure 5 ■Arrow).

As a result, the counter 9 receives the T of the CLK signal (■ in Figure 5).
Counting is performed at each falling edge of the 2nd cycle, T3 cycle, and Tw cycle. The count value is comparator 1
It is input to 0. On the other hand, the cycle T to be delayed mentioned above
The setting value from the setting register 11 in which the number of W is set is input to the comparator 10, and compared with the count value input from the counter 9. If they are equal, the comparator 1
0 outputs an H level signal to the AND circuit 12.

The AND circuit 12 inputs the H level FO multiplied signal from the flip-flop circuit 8 to the J- signal from the comparator 10.
The H level signal, which is the result of AND logic with the level signal, is input to the flip-flop circuit 13 at J-. When a signal is input to the J- circuit 13cL, it outputs an F1 signal at H level (arrow in Figure 5).
. The F1 signal is sent in the last cycle of the standby cycle T'w, and the AND logic of the F1 signal and the FO multiplied signal is taken by the AND circuit 14, and RDY
RDY signal of 1-level from signal output terminal 7 (Fig. 5 ■)
is output as .

Then, the flip-flop circuit 8 is reset to J- by the CLK signal at the falling edge of the last cycle Tw, and the FO multiplier signal (Fig. 5) and the RDY signal (Fig.
(2) in the figure is set to L level, and the counter 9 is reset to the initial state. Furthermore, the flip-flop circuit 13 is reset to J- by the falling CLK signal of the next cycle T4 (■ in Figure 5), and the F1 signal (■ in Figure 5) is reset.
) becomes L lebel.

(fl As described in detail, according to the present invention, R
Since the DY signal is sent back to the CPtJ, it is possible to easily mix a computer system with high cost performance using low-cost memory that matches the user's application, without significantly reducing the high-speed processing performance of the CPU. Possible

[Brief explanation of the drawing]

Figure 1 is an explanatory diagram explaining conventional memory access;
The figure shows one embodiment of the present invention, and FIG. 3 shows the second embodiment of the present invention.
FIG. 3 is an explanatory diagram illustrating the operation of the embodiment. FIG. 4 shows a specific circuit example of the RDY control circuit shown in FIG. 2, and FIG. 5 shows an explanation for explaining the operation of the specific circuit example of the RDY control circuit shown in FIG. In the figure, l indicates the RDY control circuit 52, the CPU, 3 the memory control circuit, 4 the memory block, 5 the EcC control circuit, and 6
The PRQ signal signal nesting terminal is the RDY signal output terminal, and 8.
13 is a flip-flop circuit at J-, 9 is a counter, 1
0 is a comparator. 11 represents a setting register, and 12.14 represents an AND circuit.

Claims (1)

[Claims] A system comprising a processing device, a memory, and a memory access by the processing device by being supplied with a response signal to a signal sent from the processing device,
A setting means for setting a return timing of a response signal to the access request signal, and a control circuit for outputting a response signal to the processing device that has sent the access request signal based on the timing set in the setting means, and the processing device but,
1. A control method for a processing device, wherein a return timing corresponding to an access time of a memory to be accessed is set in the setting means, and then an access request to the memory is issued.