JPH04372030A - Memory access system for processor - Google Patents

Abstract

PURPOSE:To perform the high-speed consecutive access of an address latch function of a CPU to a memory element (DRAM). CONSTITUTION:A memory bank composed of DRAMs 2 and 4 and DRAM controllers 3 and 5 is interleaved with banks 0 and 1. When a CPU 10 performs the read access to the memory bank 0, the other memory bank prepares for the access in the next bus cycle, and starts the read access of the other memory bank 1 before the end 4 the read access of the memory bank 0. At the time of the consecutive write access, the write access end time of the memory bank 0 is estimated by the other memory bank 1, performing the write access of the other memory bank 1 after the end time.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory access method for a processor when successively accessing a memory element having an address latch function using an advanced address mode.

0002

[Background Art] In order to perform high-speed data transfer, 32-bit CPUs, which are the mainstream of recent processors (hereinafter referred to as CPUs), operate in an advanced address mode (hereinafter referred to as advanced mode) in addition to the normal mode.
It is equipped with

The advanced mode is described in detail in Japanese Patent Application No. 1-273181 and Japanese Patent Application No. 1-280332 filed by the present inventor.
In short, the address output is output one clock earlier to overlap with the previous bus cycle, and the CP
This function enables the U to pipeline bus cycles externally, realizing a bus cycle with an access time of 3 clocks and a cycle time of 2 clocks, thereby speeding up memory access.

FIG. 5 is a circuit configuration diagram for executing the conventional memory access method using the advanced mode, in which 10 is a CPU, 11 is a decoder, and 12 is a memory element (DRAM) having an internal address latch function. , 13
is a memory element (ROM) that does not have an internal address latch function.
), 14 is a DRAM controller which is a control means for the DRAM 12.

[0005] The CPU 10 receives ADAE from the decoder 11.
N signal is input, and this ADAEN signal is High.
At h level (hereinafter abbreviated as "H"), normal mode, low level (hereinafter abbreviated as "L")
When , the mode becomes advanced mode.

FIG. 6 is a memory access timing diagram by the above circuit, in which (a) shows the normal mode and (b) shows the advanced mode. Referring to these figures, for example, when accessing DRAM and ROM continuously, in normal mode, 4 clocks + 4
While it takes a total of 8 clocks, in advanced mode it only takes 4 clocks + 2 clocks, a total of 6 clocks, which means that the access time is shortened by 2 clocks.

[0007]

[Problem to be solved by the invention] In this way, DRAM
The effect of advanced mode is demonstrated when access and ROM access are consecutive, but for example, D
There is a problem when RAM accesses are continuous. DRA
In M access, it is necessary to secure a prescribed time that is the sum of the pulse width of the RAS signal and the RAS precharge time, and it is necessary to configure the RAS and CAS generators to satisfy this. By the way, DR of 80[ns]
In AM, the pulse width of the RAS signal is 80 [ns], and the RA
The S precharge time is 70 [ns].

FIG. 7 is a timing diagram when DRAM accesses are made consecutively in the advanced mode. Referring to this figure, during the execution of DRAM cycle (1), the DRA
Address signal of M cycle (2) is output, and D
DRAM signal of RAM cycle (2) (select signal:
The shaded area) is output. In the DRAM cycle (2), the next access can be started from the moment this DRAM signal is output, but the next cycle cannot be started until the pulse width of the RAS signal and the RAS precharge time are secured. If the DRAM cycle (2) is started after securing the pulse width of the RAS signal and the RAS precharge time, it will actually take four clocks each, making it impossible to take advantage of the advantages of the advanced mode.

When an application program is actually executed, there are far more opportunities for consecutive DRAM accesses than for consecutive DRAM accesses and ROM accesses, so in the conventional memory access method, advanced mode is not used. There were very few benefits to using it. The present invention was devised in view of such problems, and its purpose is to eliminate wasted RAS precharge time, maximize the benefits of advanced mode, and improve CPU performance. The purpose is to provide a memory access method.

0010

[Means and Operations for Solving the Problems] The configuration of the present invention to achieve the above object uses an advanced address mode in which address output is output one clock earlier to overlap with the previous bus cycle. , a memory access method for a CPU that continuously accesses a memory element having an address latch function at every predetermined precharge time, the memory bank comprising the memory element and a control means for controlling the memory element. The two banks are interleaved, and when the CPU is making read access to one memory bank, the other memory bank secures the precharge time and prepares for access in the next bus cycle, and then transfers the data to one memory bank. The present invention is characterized in that a read access to the other memory bank is started before the read access to the other memory bank is completed.

[0011] Furthermore, the configuration of the present invention for achieving the above object is such that each of the memory banks monitors the access state of other banks, predicts the end time of the access, and automatically controls the memory bank until the end time of the access. A standby means for waiting the access timing of the bank is provided, and when one memory bank is in the process of write access and the write access by the CPU continues, the standby means causes the other memory bank to standby, and when one of the memory banks The present invention is characterized in that write access to the other memory bank is started after the end time of write access to the other memory bank.

0012

Embodiments Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. It should be noted that the present invention is an improvement on the conventional memory access method using the advanced mode, so parts having the same configuration and the same function as the conventional ones will be given the same names and symbols, and their explanation will be omitted.

FIG. 1 is a diagram showing an example of a circuit configuration for implementing the memory access method of the present invention. As shown in this figure, in this embodiment, the memory structure accessed by the CPU 10 is bank 0 at addresses 0, 8, 10, 18, . . ., bank 0 at addresses 4, C, 14, 1C, . It has an interleaved configuration of two banks, including bank 1 of address).

Specifically, as components corresponding to bank 0, a first DRAM 2 and a first DRAM controller 3 as control means for the first DRAM 2 are provided, and as components corresponding to bank 1, A second DRAM 4 and a second controller 5 serving as control means for the second DRAM 4 are provided. Bank 0 and bank 1 also include independent RAS and CAS generators (not shown),
Each has separate select signals DRAM0 and DRAM1.

FIG. 2 shows the memory access timing when a DRAM continuous read cycle is performed from the CPU 10 equipped with the advanced mode in such a circuit configuration. Referring to this figure, when the CPU 10 is operating in advanced mode, during bank 0 DRAM access, the address for bank 1 DRAM access in the next bus cycle is output, and the DRAM1 signal is output. Ru. Thereby, address decoding can be ended during access to the first DRAM 2, and access to the second DRAM 4 can be started. For this reason, Figure 5
In the conventional circuit example shown in 4 clocks + 4 clocks + 4
What used to take 4 clocks + 4 clocks now requires 4 clocks + 2 clocks + 3 clocks by changing the circuit configuration shown in Figure 4.
Only two clocks are required, and the performance of the CPU 10 can be greatly improved by making full use of the advanced mode's address first-out function.

Next, the case of continuous write cycles in advanced mode will be explained. During a write cycle, the CPU 10 outputs write data at the falling edge of the T1A clock, and each DRAM 2, 4 outputs write data at the falling edge of the T1A clock.
This write data is captured at the falling edge of the AS0 and CAS1 signals. Therefore, if the write process is performed at the timing shown in Figure 2, when writing to DRAM2 and DRAM4, CPU1
Write data of 0 is not finalized, and the process fails. Therefore, in the write cycle, the RAS and CAS generators must wait so that the write data of the CPU 10 is determined at the falling edge of the CAS0 signal and the CAS1 signal.

As this standby means, in this embodiment, FIG.
Wait circuits for RAS and CAS generators are provided in each bank 0 and 1. Extension given to each signal name in this figure. Each L has a meaning at the Low level, and in the following explanation, this extension. Omit L. Further, FIG. 4 is a diagram showing the operation timing of this wait circuit. To summarize, it monitors whether or not the state of another bank is being accessed, and if it is being accessed, predicts the end time of the cycle, The operation of each RAS and CAS generator is temporarily put on standby so that each CAS signal falls after the time when the write data of the next cycle is determined.

To specifically explain the configuration and operation of each wait circuit, the DL in each DRAM controller 3, 5
DLA0 signal generated by A generators 3a and 5a,
The timing at which the DLA1 signal (select signal) is issued is determined by the DRAM0 signal or the DRAM1 signal and the CL
Adjust with the K signal (clock signal) and adjust the DR of the other bank.
It is input to the OTHER terminals of AM controllers 3 and 5. As shown in FIG. 4, these DLA0 and DLA1 signals are negated one clock before the end of the bus cycle of the other DRAM, so it is possible to easily predict the end time of the operation of the other DRAM. Also, OTHER
The DLA0 signal or DLA1 signal input to the terminal is the RAS0 signal generated by the RAS generators 3b and 5b.
signal, RAS1 signal output timing to the other DRAM.
Since the controller waits until the operation end time and starts bus access at the same time as the end of the operation, the write data is correctly written to DRAM2 and 4 of each memory bank 0 and 1 even in the case of continuous write cycles, and the DR
It is possible to prevent problems caused by having the AMs 2 and 4 and the DRAM controllers 3 and 5 in an interleaved configuration.

It should be noted that if the interleaved configuration of DRAMs 2, 4 and DRAM controllers 3, 5 is applied to a two-port memory as in this embodiment, if system access and local access request access to separate DRAM controllers, two-port The wait time due to arbitration is eliminated or the number of times of waiting is reduced to 1/2, thereby improving system performance.

[0020]

[Effects of the Invention] As explained above, in the present invention, CP
The memory configuration accessed by U is an interleaved configuration of two banks, and when the CPU is making read access to one memory bank, the other memory bank secures RAS precharge time and prepares for access in the next bus cycle. Since the read access to one memory bank is started before the read access to the other memory bank is completed, there is no wasted RAS precharge time, and the advantages of advanced mode can be maximized. It became so. In particular, when executing an application program that requires continuous DRAM access, the conventional method uses only 1% of the total bus access time.
The method of the present invention reduces the waste of RAS precharge time, which used to be 40%, to zero, making it possible to increase the capacity by 1.25 times.

Furthermore, in the present invention, each memory bank is provided with a standby means that monitors the access state of other banks, predicts the end time of the access, and waits for the access timing of the own bank until that time has elapsed. and when one memory bank is in the process of write access and the write access continues, the standby means causes the other memory bank to stand by, and after the write access end time of the one memory bank, the other memory bank is stopped. Since write access of the bank is started, the write data sent in consecutive cycles is transferred to the D of each memory bank.
Write data is correctly written to the RAM, and problems caused by the interleaved configuration can be prevented.

Therefore, even if read access and write access are performed consecutively, the advanced
Since you can take full advantage of the advantages of C
A memory access method that can improve PU performance can be provided.

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram for executing a memory access method according to an embodiment of the present invention.

FIG. 2 is a timing diagram of DRAM continuous read access by the above circuit.

FIG. 3 is a configuration diagram of a wait circuit of the RAS and CAS generators used in this embodiment.

FIG. 4 is a timing diagram of DRAM continuous write access by the wait circuit.

FIG. 5 is a circuit configuration diagram for executing a conventional memory access method.

FIG. 6 is a timing diagram of memory access by a conventional circuit, in which (a) shows the case in the normal mode, and (b) shows the case in the advanced mode.

FIG. 7 is a timing diagram of continuous DRAM access in advanced mode in a conventional circuit.

[Explanation of symbols]

0, 1...Memory bank, 2, 4...Memory element with address latch function (DR
AM) 3, 5...Control means (DRAM controller), 10...Processor (CPU)

Claims (2)

[Claims] Claim 1: Using an advanced address mode in which address output is output one clock earlier to overlap with the previous bus cycle, access to a memory element having an address latch function is performed every precharge time. A continuous memory access method for a processor, wherein a memory bank consisting of the memory element and a control means for controlling the memory element has an interleaved configuration of two banks, and the processor read accesses one memory bank. If so, the other memory bank secures the precharge time to prepare for access in the next bus cycle, and starts read access to the other memory bank before the read access to one memory bank ends. A memory access method for a processor characterized by: 2. A memory access method for a processor according to claim 1, wherein each of said memory banks monitors the access state of other banks, predicts the end time of said access, and maintains access to the own bank until that time elapses. A standby means is provided for waiting for the access timing of the memory bank, and when one memory bank is in the process of write access and the write access by the processor continues, the standby means causes the other memory bank to wait, and when one memory bank A memory access method for a processor, characterized in that write access to another memory bank is started after a write access end time for one bank.