JPS60134956A - Information processing system - Google Patents

Abstract

PURPOSE:To process the continuous data access to a main storage device at a high speed by providing a by pass designating flag and an access right designating flag and by passing an access right designating circuit and a main storage contention check circuit. CONSTITUTION:If a storage device access right designating request is outputted from a processor 1 or 2, a processor access right command flag 901 or 902 is set through a switching circuit 312, etc. Then, switching circuits 312, 313, and 314 are selected fixedly by the output of the flag 901 or 902. If an access contention check by pass designating request is outputted, a contention check by pass flag 801 is set, and outputs of main storage module busy check circuits 322 and 323 are ignored. Flags 901, 902, and 802 are set in this manner to by pass an access right designating circuit 9 and circuits 322 and 323, thereby processing the continuous data access to the main storage device at a high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION TECHNICAL FIELD The present invention relates to an information processing system that performs storage device access conflict control.

BACKGROUND TECHNOLOGY Conventionally, in a multiprocessor system that shares a main memory, memory access requests from multiple processors are managed on a memory module-by-storage module basis, with respect to multiple independently accessible memory modules that make up the main memory. There is a need to. Therefore, when storing continuous address data from a certain processor to the main memory, or conversely when loading continuous address data from the main memory to a certain processor, each time the main memory is accessed, Push check and same storage module accessor check for the preceding memory access request of the own processor (normally, if the preceding memory access is a store operation, the subsequent store, 1fC is a load because the memory module is busy until the preceding store operation is completed) Waiting time) etc., the processing takes time. Additionally, the hardware required to process these checks at high speed is also becoming more complex.

OBJECTS OF THE INVENTION An object of the present invention is to provide an information processing system that eliminates the above-mentioned drawbacks and can process continuous data access to a main memory at high speed.

Configuration of the Invention The information processing system of the present invention includes a plurality of information processing devices,
A storage device configured of a plurality of independently accessible storage modules that perform data write/read operations in response to memory access requests issued from these processing devices; an access control circuit that controls an access conflict check and an access order for the storage device; and an access control circuit that allows one of the information processing devices to monopolize the access right to the storage device, and controls access rights to the storage device to another of the plurality of information processing devices until an instruction to reset the access right is received. a storage device access right designation circuit that specifies to suppress memory access requests from the processing device; and outputs instructions to set and reset the storage device access right designation circuit in response to a predetermined command from the information processing device. a contention check bypass mode circuit that instructs the access control circuit to bypass the access contention check; and a contention check bypass mode circuit in response to a predetermined command from the information processing device. , and a bypass instruction circuit that outputs a reset instruction.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described in detail with reference to the drawings. Fig. 1 shows the configuration of the refreshing side of the present invention. In Figure 1, to simplify the explanation, Ichiji Mli
tli has two processors and two storage modules that constitute the main storage device. First, from the first arithmetic processing processor 1, a request synchronization signal 101, a memory request code 10
2 and memory request address 103, memory write data 104 is transmitted to signal lines 111 to 11 as necessary.
4 and the main memory access control circuit, the first main memory module 6'l: is sent to the second main memory module 7. Similarly, from the second arithmetic processing processor 2, in addition to the request synchronization signal 201, memory request code 201, and memory request address 203, memory write data 204 is sent to the signal lines 211 to 214 and the main memory access control circuit 3 as necessary. The data is sent to the first main memory module 6 or the second main memory module 7 via the main memory module 7.

Here, the details of the access control circuit 3 will be explained.

The request synchronization signal sent on lines 111 and 211 is sent to gate 301.3 (12 Nantes gate 304.3).
05.307 and the AND gate 306 determine the priority (first arithmetic processing processor, second arithmetic processing processor), and the switching circuits 312, 313 and 3
Fourteen selection signals 336 and 337 are output. These selection signals 336 and 337 are further applied to the NAND gate 30 if the first processor access right designation flag 901 of the main memory device access right designation circuit 9 is not set and the selection signal 336 is not set.
Conditions are taken at 9, Nantesgate 310 and 3 ],
1 and a first processor access right designation flag 90] and a second processor access right designation flag 9, respectively.
It is logically summed with 02. Next, it is determined whether the request of the first processor 2 or the request of the second processor 2 is selected, and a request selection signal 33 is sent.
9 and 3·1O are output. Here, the bypass designation 7 flag 801 of the conflict check bypass finger and foot circuit 8, the second processor access right designation flag 901, and the second processor access right flag 902 or 4 are not set. -ba, nando game) 3
+'l 3 from the first processing processor j and the processing processor 2 of %92 quent synchronization signal 1] -1
The output signal 338 in which the logic 1j of 211 is taken is the first main memory module selection signal 347 after reading the memory request lower bit signal line 345 by the decoding circuit 315 at the output of the switching circuit 313; Alternatively, the second main memory module selection code 348 and the Nant gates 316 and 319 perform an AND operation.However, since the signal line 803 is in the OFF state, the Nant gate outputs 353 and 354 are both ((
The output of the first main memory module busy check circuit 322 and the second main memory module busy check circuit 323 and the request selection signal 3 are turned on and Fi does not function under the OR condition of the Nant gates 320 and 321.
39 and 340 as well as the Nantes gates 318 and 319. That is, the bypass designation flag 801, the first processor access right designation flag 901, and the second processor access right designation flag 9
If 02 is in the reset state, the requests output from the first processor 1 and the second processor 2 are not processed until after the first main memory module busy check circuit 322 or the main memory module l busy check circuit 323 has been checked. The first main memory module 6 and the second main memory module 7 cannot be accessed. On the other hand, the first processor 1 and the second processor! 7-2
When a storage device access right designation request is output from one of the processors using the request code shown in the table, the switching circuit 312 outputs the request code line 343 or the code of the main memory access right control circuit 5. times W65
(The request selection signal 339 is tW FjZ at l.
and: 340 and AND gates 504 and 505 take the condition, and the first processor access right designation flag 9
The 4-bit signal 509 of 01 or the set signal 508 of the second processor access right designation flag 902 can be output.

Table Memory Request Code Format When these flags 901 or 902 are set, an h1 removal request is output in subsequent new requests, and a reset request is issued.
506 is output]'1. switching circuits 312 and 31 until
3 and 314 are permanently selected by the output of flag 901 or 902.

Next, the access conflict check bypass specification - anti-end is output in the request code, and the request code line 34 is output as /b.
3 is j support check bypass ↑δ1J group 1f-! 1 road 4
It is decoded by the data code circuit 401 and a set signal 403 of the conflict check bypass flag 801 is output. After this flag 8O1 is set, the first unique module busy check circuit 3 is output until a release request is output in July and a reset signal 402 is output.
22 and 2nd King Memory Module Busy Check Episode 11
The output of line 3323 is output as signal 1, and the request synchronization signal is output as the content of line 356 on line 3551.

Request synchronization (G is the synchronization register 601 of the first main memory module 6 or the king of the second main memory module 7;
is sent to the synchronization register 701 of the command registers 602 and 702 to enable the outputs of the respective command registers 602 and 702, and the decode circuits 605. The address information 60 is stored in the first memory 606 and the second memory 706 by the code output of 705.
9,709 and store data information 610 work 710
accessed using.

As is clear from the above operation description, a series of data transfers are processed continuously and at high speed without being disturbed by other processors.
, 7, the above flag 80J.

This can be achieved by setting 901 or 902. In the explanation here, the main storage device is taken as an example, but it is also effective to replace this portion with a buffer memory (cache memory).

Effects of the Invention In the present invention, a series of access conflicts can be avoided by providing a mode circuit that bypasses the access specification circuit and the main memory access conflict check circuit, which allows one of a plurality of information processing devices to occupy the storage device. It is said that data that does not need to be checked can be transferred to main memory continuously and at high speed.

[Brief explanation of the drawing]

FIG. 1 is a view showing one flow side of the present invention. In FIG. 1, 1... music/first arithmetic processing processor, 2... candy 2 arithmetic processing processors 1, 3...
...Main memory access control circuit, 4...Conflict check bypass control circuit, 5...Main memory access right control circuit, 6...First main memory Module 7...Second main memory module,
...Conflict check bypass designation circuit, 9...
・Main memory unit access right designation circuit, 101.201・
...Request synchronization signal, 102, 202...
...Memory request code, 103.203...
...Memory request address, 104.204...
...Memory write data, 301°302...
...Gate, 303. 304. 305°307.
308, 309, 310, 3 i 1...-1-and gate, 306...and gate, 312°313.314...switching circuit, 315...
... lever)" times JI, 322... first main memory module busy check circuit, 323... second
main memory module busy check circuit, 316.31
7,318°319.32 (1,321...Nide gate, 401.501...Decode circuit, 801...Bypass finger/foot flag, 901...
...Glossary access right specification flag, 902
...Process 1 access right specification flag, 50
4,505...and gate.

Claims (1)

[Scope of Claims] 1. A plurality of information processing devices; a storage device that performs data pull-in and read operations in response to memory access requests issued independently from the plurality of information processing devices; and the memory access device. Receiving the request includes an access control circuit that checks access conflicts with respect to the storage device and controls the access order; and 4. An access control circuit that controls the access conflict check and access order for the storage device; a storage device access right designation circuit that suppresses memory access requests from other information processing devices among the plurality of information processing devices; and a storage device access right designation circuit that suppresses memory access requests from other information processing devices; An information processing system comprising: an access right control circuit that issues a circuit set and reset instruction. 2. A storage device comprising a plurality of storage modules that can be accessed independently of each other; a conflict check bypass designation circuit that instructs the access control circuit to bypass the access conflict check; 2. The information processing system according to claim 1, further comprising a conflict check bypass control circuit that outputs a set and reset instruction for the conflict check bypass mode circuit in response to a predetermined command.