JPH04333950A - Information processing system - Google Patents

Abstract

PURPOSE:To prevent a bus from being occupied for a long time and the ability of an input/output device and a processor from being affected by the occupation. CONSTITUTION:This information processing system is equipped with a processor 1 with a central processing circuit 11 to execute a processing according to instructions and data on a memory and a FIFO type write buffer 14 to successively hold data written from this central processing circuit and to successively supply the held written data to the outside. Further, a storage device 3 is provided with a first circuit 31 to primarily hold addresses and data written from the processor while being connected through a memory bus 2 to this processor, second circuit 33 to successively write the information from this first circuit to a storage area and a third circuit 32 to continuously fetch the data of the write buffer in the processor into the first circuit. Moreover, an input/output device 4 connected to the processor and the storage device by the bus is provided to control input/output with an external device, and the addresses and data written from the write buffer in the processor are transferred by one time of bus arbitration.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing system.

0002

2. Description of the Related Art Conventionally, in an information processing system having a write buffer in a processing device, there is no temporary storage means in the storage device, and write addresses and data are transferred word by word to the storage device through a bus. An example of this conventional system configuration is shown in FIG.

In the system shown in FIG. 3, the write address and data of the processor 11 are stored in the write buffer 14.
The data is sequentially stored in the memory array 34, read out word by word by the memory control circuit 36 in the storage device 3, and written into the memory array 34. Here, a processor 11 in the processing device 1,
It is assumed that the exchange with the cache 13 and the write buffer 14 via the processor bus 12 is sufficiently fast for the processing capacity of the processor 11, and does not interfere with the processing capacity of the processor 11. FIG. 4 shows the time relationship on the memory bus 2 of two consecutive word write operations in this conventional system.

0004

[Problem to be solved by the invention] In the conventional system,
As is clear from Figure 4, since bus arbitration, address and data transfer, writing, and result reporting are performed, the bus is occupied for a long time due to data writing, which affects the performance of input/output devices and processing devices. There is a problem of giving

[0005]

[Means for Solving the Problems] The information processing system of the present invention includes a central processing circuit that performs processing based on instructions and data on a memory, and a central processing circuit that sequentially retains write data from the central processing circuit and transfers the retained write data to an external device. a processing device having a FIFO type write buffer that sequentially supplies data to the processor; a first means connected to the processing device via a bus and temporarily holding write addresses and data from the processing device; a storage device having a second means for sequentially writing into a storage area from the means; and a third means for successively fetching data from the write buffer in the processing device into the first means; The device includes a processing device and an input/output device connected to the storage device and in charge of input/output with an external device; transfer of a write address and data from the write buffer in the processing device is performed by one bus arbitration.

[0006]

Embodiments Next, embodiments of the present invention will be described with reference to the drawings. Referring to FIG. 1 illustrating one embodiment of the present invention,
The information processing system is composed of a processing device 1, a storage device 3, and an input/output device 4 that are interconnected via a memory bus 2. The processor 11 in the processing device 1 reads instructions and data stored in the memory array 34 in the storage device 3 using the read control circuit 35, takes them into the cache 13 in the processing device 1 via the memory bus 2, and stores them in the cache. 13 via the processor bus 12, processing is executed in accordance with the above-mentioned read command and data. The cache 13 is a write-through type cache, and write data from the processor 11 is sent to the cache 1.
It is necessary to write to the memory array 34 in the storage device 3 at the same time that the data is written to the memory array 34 in the storage device 3. Generally, the memory array 34 constituting the storage device 3 is sufficiently slow compared to the processing speed of the processor 11, and hinders the processing performance. In order to absorb this speed difference, a FIFO type write buffer 14 is placed between the processing device 1 and the memory bus 2, and it sequentially stores write addresses and data of the processor 11, and sequentially outputs them to the memory bus 2. Furthermore, the write buffer 14 in the processing device 1 is added to the storage device 3 by one bus arbitration.
A continuous readout circuit 32 is provided that can read addresses and data stored in the memory continuously, and the readout addresses and data are temporarily stored in a write data holding circuit 31 that temporarily holds the addresses and data stored in the memory. Write to array 34. In this information processing system, FIG. 2 shows the time relationship on the memory bus 2 when write addresses and data for two words are stored in the write buffer 14. As is clear from this time relationship, the conventional technology required 10 bus cycles2.
Word writing is shortened to 4 cycles, making it possible to significantly reduce the occupancy of the memory bus 2. This makes it possible to reduce contention on the memory bus 2 between data transfers from devices such as the input/output device 4 connected to the memory bus 2 and writes from the processing device 1 .

[0007]

As explained above, according to the present invention, the bus occupancy rate can be reduced.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram showing an embodiment of the present invention.

FIG. 2 is a diagram illustrating the operation of the embodiment.

FIG. 3 is a configuration diagram showing a conventional example.

FIG. 4 is a diagram illustrating the operation of a conventional example.

[Explanation of symbols]

1 Processing equipment 2 Memory bus 3. Storage device 4 Input/output device 11 Processor 14 Write buffer 31 Write data holding circuit 32 Continuous readout circuit 33 Write circuit 34 Memory array 35 Readout control circuit

Claims (1)

[Claims] Claim 1: It has a central processing circuit that performs processing according to instructions and data on a memory, and a FIFO type write buffer that sequentially holds write data from the central processing circuit and sequentially supplies the held write data to the outside. a processing device; a first means connected to the processing device via a bus and temporarily holding write addresses and data from the processing device; and a second means for sequentially writing into the storage area from the first means. and a third means for successively fetching the data of the write buffer in the processing device into the first means; connected to the processing device and the storage device by the bus, and connected to the external device. 1. An information processing system, comprising: an input/output device that controls input/output to and from the processing device; and transfers a write address and data from the write buffer in the processing device by one bus arbitration.