JPS60120458A - Data transferring device - Google Patents

Abstract

PURPOSE:To lighten burden and to shorten the processing time of a microprogram, by outputting a terminate signal when data transfer is terminated before prescribed data are completely transferred and terminating the interrupted data transfer by means of hardware. CONSTITUTION:When termination of data transfer is informed to a control circuit 22 from an input-output device through a signal line 112 in the middle of the data transfer, a signal S104 which indicates that the final transfer data is on a data bus 101 is not outputted, since the content of a counter is not zero. In this case, a control signal S105 is outputted from a control circuit 22 after all data remaining in a data buffer circuit 21 are sent out to another data buffer circuit 11. Upon receiving the signal S105, a control circuit 12 sends out a control signal S111 to data registers 13-16 and stores the interrupted final data in the data registers. Then the control circuit transfers the final data to a main storage device as final transfer and terminates the interrupted transfer.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a data transfer device, and relates to a data transfer path rc of a data processing device P'i. This signal is sent to notify the data transfer circuit on the receiving side that the final transfer data to be transferred is the last data when the content of the preset counter reaches zero in data transfer. End signal from side data transfer circuit? The data transfer is completed by sending the data. Now, the data transfer circuit on the receiving side is asking me if the width of the bus is different from the width of the bus between both data transfer circuits. For example, when transmitting data to another device via a 1-byte data transfer bus width, it is necessary to send data in units of 4 bytes, so every time 4 bytes of data accumulate in the data transfer circuit on the receiving side, The other device/C data will be transferred. If the final transfer data does not end at every 4-byte break, for example, if it ends at the 2nd byte, the a end signal is
Recognizing that it is the final data, without waiting for 4 bytes to be collected, the other device (C data transfer wh) ends the transfer sound.Here, the content of the counter on the sending side transfer (B) path becomes zero. If data transfer is interrupted for some reason, 4 bytes are aligned when the received data is not at the break of every 4 bytes. The MU is in a waiting state for data transfer to other devices.In this case,
When the data transfer is interrupted in the conventional device, the microprogram is notified, and all data remaining in the receiving side data transfer circuit is sent to the other device, and the interrupted data transfer is completed. There is 0 Therefore,
Putting a large burden on the microprogram and requiring a large amount of processing time for microprogram processing? In need of.

[Purpose of the invention]

An object of the present invention is to eliminate the above-mentioned drawbacks without the intervention of a microprogram/remaining data transfer circuit. Is there any other device that can send out pages? [Structure of the Invention] An uninvented data processing device, a first data transfer means,
Predetermined number of data? When the first data transfer means rc has completed the transfer, a first end signal is outputted, and before the predetermined data has been transferred to the first transfer means, a second end signal is output when the data transfer is completely completed. [Embodiment] The present invention will be described in detail with reference to all the drawings. Figure a is a block diagram showing an embodiment of the present invention.

The data transfer circuit 2a is connected to an input/output device (not shown) via a 1-byte wide data bus 109', and is connected to the data transfer circuit trr main memory (not shown) via a 4-byte wide data bus 109'e. The data buffer circuit 21, the data buffer circuit 11, and the data buffer circuit 11 are connected via a data bus lO1''ft of a1 byte width.A valid display signal 8102 indicates that the data on the data bus 101 is valid. ,
Is the final transfer data on data bus lO1? A first end signal 8104 indicating that the data sent immediately before the transfer was the final transfer data
o5 connects the signal lines 102 and 104 from the control circuit 22.
05 and given to the control circuit 12.

Data from data bus l 01? Reception signal 8to31'J indicating reception from control circuit 12 to signal line 103
The rc output is small, so it cannot be applied to the control circuit 22.

Control signal 8106μ Control (b) path 12 to signal line 106
is provided with a data buffer (b) path lll'c through the
Control signal 811+D control circuit 12 to data register 1
3゜14.15,16vc given h-1 control value number 5so
It is applied from the r-side control circuit 22 to the data buffer circuit 21/c via a signal line 107'. Data buffer circuit 1
It is connected to the data registers 13, 14, 15, and 16 in 1 byte via a data bus 108' with a width of 1 HI/2.

In this embodiment, there is one data transfer circuit 2 on the input/output device side, but a plurality of data transfer circuits 2 may be provided.

Next, the operation 9 will be explained. Data is transmitted from the input/output device via the data bus 110. Captured data transfer circuit 2 Data buffer circuit 21 Control signal 8 of control circuit 22
107 instructions 1c editor pass to t vc put on the teddy. At this time, the control circuit 225-V'X is outputted to the valid display signal 51o2. This signal 5s
A control signal 51o6vcxr) is sent to the control circuit 12 of the data transfer circuit 1yen accepted by o2) data buffer 7alal*1l
Instructs to take in all the data on the rc data bus 101, and takes the data into the exact data buffer circuit 1lrr.

Data on control circuit 12r1' data bus? A reception signal 51oa'& output indicating that it has been received, and this signal 810
The control circuit 22 receives the next data from the data bus l.
Data buffer circuit 21 VC to place OI Ic
and outputs the signal 8102 again. By repeating this process, nine consecutive data transfers are performed. The data stored in the data buffer circuit 11 is sequentially sent to the data registers 13, 14, 15 and 16 via the data bus 108Th in 1 bar units, and the control signal ν is sent from the control circuit 12. When data is stored in the IC engineering V all data registers 13 to 16, it is sent to the 4-byte parallel RC main storage device via the data bus 109.A counter is provided in the control circuit 22, and when the contents are zero, When this happens, that is, when the data sent from the data buffer circuit 21 is the final data, the control circuit 22 outputs the final transfer data to the signal 81o4 indicating that there is a VC on the data bus l01, and the control circuit 12 Geko signal 810
4, even if the final transfer data is not stored in the data register 16 at every 4-byte interval, the V data register 13 is output by outputting the control signal 5ill.
~1fitc Instructs all data transfer to the main storage device and completes all data transfer.

Is the signal line 112 from the input/output device currently in the middle of data transfer? If the end of the transfer is notified via the counter, the contents of the counter will not reach zero, so the signal 5104r cannot be output. At this time, 1 burnt and the data remaining in the data buffer circuit 21 yen? After all data is sent to the data buffer (b) path 11, the control circuit 22 outputs the control signal 5lo5. Signal 8to5'
The control circuit 120 and data registers 13 to 16 accepted by
9 control signal 8111 is sent, the last interrupted data is stored in the data register 9, and transferred to the main storage device as the final transfer to complete all interrupted transfers.

〔Effect of the invention〕

That's all for the present invention, interrupted transfer? Is it possible to reduce the burden on the VC Eli micro program and shorten the processing time by terminating it with hardware? It has the effect of being able to achieve 0

[Brief explanation of the drawing]

Figure a is a block diagram showing one embodiment of the present invention;
2...Data transfer circuit, 11.21...Data buffer circuit, 12.22...Control (b) path, t3, 14
゜15.16...Data register, lot, 108゜109.110...Data bus, 102~107゜1
11.112...Signal line 0

Claims (1)

[Claims] a first data transfer means; a predetermined number of data transfer means;
When the data has been transferred to the data transfer means of v! ! First end signal? and a second transfer means that outputs a second end signal when the transfer sound of the nine data before the end of transferring the predetermined data to the first transfer means is completed; Transfer device 0