SU1539787A1 - Multichannel processor-to-subscribers interface - Google Patents

Abstract

The invention relates to computing and can be used in data processing systems as a subprocessor of information exchange between subscribers and the central processing unit. The aim of the invention is to improve the speed of the device. The device comprises an operation unit 1, a memory unit 2, a communication unit with subscribers, a communication unit 4 with a processor, an address register 5, a microprogram control unit 6. The device provides, under the control of the firmware in block 6, a high-speed bidirectional exchange of information between the processor and the subscriber. 1 hp f-ly, 3 ill.

Description

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The invention relates to computing and can be used in data processing systems as a subprocessor of information exchange between subscribers and the central processing unit.

The aim of the invention is to increase the speed of the device.

FIG. 1 shows a block diagram of the proposed device; Fig. 2 is a diagram of the operational unit 1; in fig. 3 is a schematic diagram of a firmware control unit.

The device contains (FIG. 1) an operation unit 1, a RAM unit 2, a communication unit with subscribers, a communication unit 4 with a processor, an address register 5, a firmware control unit 6, inputs 7 and 8 of the device for connection to the start outputs and interrupt the processor, device output 9 for connecting to the subscriber control input, device inputs 10 and 11 for connecting to the subscriber and processor information inputs and outputs, respectively, device outputs 12 and 13 for connecting to the address and subscriber request inputs, input 14 devices for n Connections of the synchronization output of the processor, output 15 of the device for connecting the subscriber interrupt input, the fifth 16, the sixth 17, the fourth 18, the third 19 and the second 20 outputs of the sample of the microprogram control unit 6 and the condition input 21 of the microprogram control unit 6.

Operational unit 1 contains (Fig. 2) a decoder 22, registers 23-30 from first to eighth, switch 31, arithmetic logic unit 32, 33rd and 34th registers 34, pulse shaper 35.

The firmware control unit 6 contains the first and second registers 36 and 37, the trigger 38, the second memory block 39, the first and second blocks of AND 40 and 41 elements, the first and second And 42 and 43 elements, the OR elements block 44, the OR 45 element and first memory block 46.

The communication unit 3 with the subscriber and the communication unit 4 with the processor are bi-directional bus drivers.

The device operates in the following main modes:

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executing the procedure Download task to the subchannel;

executing the procedure Delete a task from the subchannel;

executing a command to transfer data from the external memory to the subscriber;

executing a command to transfer data from the subscriber to the external memory;

executing a command for transmitting a control byte to the subscriber;

executing a program termination command.

In addition, the presence of firmware control allows you to create more complex commands to transfer information from the central processor to the subscriber and back with various types of information conversion.

The device works as follows.

On the Start signal, which enters device 7, the register 36 of unit 6 is nullified. As a result, the first microcommand is selected at zero address from memory block 39, which is the beginning of the firmware program.

As a result, the signals of the logical zero are formed at the second, third and sixth outputs of the block 39, the signal of the logical unit at the fifth output, and the micro-command code at the first output. The higher bits of the address of the next micro-command come from the fourth output of block 39 through the block of elements OR 44 to the information input of register 36, and the low-order bit of the address of the next micro-command from the second output of the block of elements OR 44 is fed through elements AND 42 and OR 45 to the second information input of the register 36. On the falling edge of the sync pulse arriving at the synchronous input of block 6, a microcommand from the zero address is written to the register 37, and the address of the next microcommand is written to the register 36. Thus, at the outputs 9, 13, 15-20 of block 6, signals are generated that provide control of the units of the device.

The entire memory of block 2 is divided into groups of six memory cells, called subchannels. The null cell of the subchannel contains information on the presence (unit in the lower order of the cell) or the absence of a task (zero in the minor order of the cell) in the subcloth5

le. Therefore, in order to bring the subchannel back to its original position, it is enough to zero the zero cells of all subchannels. The contents of the remaining cells in this case does not matter. This procedure is performed as follows. To the input of node 32 of block 1, a code is output from output 17 of block 6, which ensures the formation of a zero code at the output of node 32, arriving at the information input of register 26. To the input of the decoder 22 from output 17 of block 6, a code is supplied that provides in conjunction with a sync pulse the synchronous input of the decoder 22, the generation of a pulse signal at the fourth output of the decoder 22. As a result, the register 26 is zeroed. The register 27 of unit 1 is likewise nullified. Then a code is applied to the input of the switch 31 from the output 17 of the block 6, ensuring the passage of pulses to the output of the switch 31.

In the first micro-command, the register 27 of block 1 is zeroed, and then a cycle is started in which the presence of an interrupt from the central processor 5 or the incomplete task in the subchannel is analyzed. In the first micro-command of this cycle, the signals of the logical unit and logical zero are formed at the second and third outputs of block 39 of block 6, respectively, which ensures the formation of the address of the next micro-command taking into account the interrupt signal at input 8 of the device. In the event that such a signal exists, then the trigger 38 of block 6 is set to

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unit, as a result of which, from block 46, a code is selected, which through block 40 of elements AND goes to the first input of block 44 of elements OR. As a result of the logical summation of this code with the address of the next microcommand arriving at the third input of the block 44 of the OR elements,

Simultaneously to the input of node 32 from output 25, the initial address of the firmware Reception

17 of block 6, a code is provided to allow information to pass from the first input of block 32 to its output without distortion. A code is supplied to the second input of the decoder 22, which, together with the sync pulse, provides the generation of a pulse signal at the ninth output of the decoder 22, which records information at the output of node 32 (register value 26) into register 33. In the same way, the contents of register 27 are copied to register 34.

In the next microcommand, a sample 1 signal is sent to the input of the sampler - 35 of block 1, which opens the shaper 35. At the same time, the address and information inputs of block 2 receive codes from the address and information outputs of block 1. At output 16 of block 6, a signal is provided that provides recording zero information at zero address.

Further, the contents of register 27 of block 1 are increased by six (the size of the subchannel) by submitting the corresponding codes to output 17 of block 6, and then rewritten into register 34 of block 1 and the zero information is again written to block 2 at the address specified in register 34 of block 1. Thus, all zero cells of all subchannels of block 2 are zeroed.

Next, the Analysis of the presence of the task on the subchannel is executed.

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In the first micro-command, the register 27 of block 1 is zeroed, and then a cycle is started in which the presence of an interrupt from the central processor 5 or the incomplete task in the subchannel is analyzed. In the first micro-command of this cycle, the signals of the logical unit and logical zero are formed at the second and third outputs of block 39 of block 6, respectively, which ensures the formation of the address of the next micro-command taking into account the interrupt signal at input 8 of the device. In the event that such a signal exists, then the trigger 38 of block 6 is set to

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unit, as a result of which, from block 46, a code is selected which, through block 40 of elements AND, goes to the first input of block 44 of elements OR. As a result of the logical summation of this code with the address of the next microcommand arriving at the third input of the block 44 of the OR elements,

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the task that arrives at the first and second information inputs of the register 36 and is recorded in this register by the rear Aurontu sync pulse. In this way, the transition to the job acceptance firmware is carried out.

If there is no interrupt signal at input 8, the address of the next micro-command is not modified and the second micro-command of the cycle is executed, in which the contents of register 27 are sent to register 34 and then information is read from block 2 to the address specified in register 34 which is written to register 26. Then the contents of register 26 are checked for equality to zero. If this condition is not fulfilled, then the output of the transfer of node 32 forms a signal of a logical unit, which is fed to the input 21 of block 6, resulting in a modification of the lower-order bit of the address of the next microcommand arriving at the third input of the block 44 OR elements. To perform the modification, the low-order bit of the address of the next micro-instruction is necessarily zero. Thus, the transition to the beginning of the microprogram Reading subchannel is performed. If the contents of register 26 is zero, then the transfer signal at the output of node 32 is not about

is developed, and therefore a transition is made to the next cycle microcommand in which the contents of register 27 are increased by six and the transition to the beginning of the cycle is made.

Firmware Reception of the task is performed as follows.

The register 33 is zeroed out, and in the working register 30 of block 1, a fixed address No. is formed, which is the starting address of the external memory area (not shown in Fig. 1) for communicating the central processor with the device. Next, the contents of the memory cell No. are read, for which the output signal 13 of the device generates a signal Read, and the output 19 of block 6 is a code that selects the reading of block 4. As a result, the contents of the cell No. go to input 11 of the device and through block 4 to the information inputs of blocks 1 and 6. The least four, the code from cell No. are recorded in register 27} the next four bits (the subscriber number is No. VU in register 29, and the senior eight bits are in register 28 of block 1.

Then a message is sent to the central processor about the completion of the task reception. To do this, the Record signal is generated at the output 13 of the device, and the block 6 at the output 19

the code that opens block 4 to write, causing the cell No. to zero. At the first output of register 37 of block 6, a signal is generated that sets the trigger 38 of block 6 to the zero state.

After this, the contents of register 28 of block 1 are transferred to register 33, the shaper 35 of block 1 is opened, and the command code is fed to the information input of block 6 to perform an analysis of the type of I / O command.

At the same time, a unit is formed at the third output of block 39, and at the fourth output, the address of the next microcommand, which, passing through the block 44 of OR elements, is modified depending on the code received at the information input of block 6. As a result, either the initial address of the microprogram is generated. (when the Start I / O command is received), or the starting address of the firmware.

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nor (when a Stop I / O command is received).

If the Stop I / O command has been received, the zero cell of the specified subchannel is zeroed out, for which register 34 registers the value of register 27 multiplied by six by. the output 16 of block 6, a write signal is generated. After that, the transition to the firmware

If the Start I / O command has been received, the working register 30 of block 1 is configured with address no. + 1, which is then rewritten into register 34. At output 13 of the device, a read signal is generated, and the contents of cell K + 1 are read into register 23 of block 1. Thus, in register 23, the initial address of the program is formed, through which information is exchanged with the subscriber. The next step is to go to the firmware. Processing the command code.

The firmware Reading subchannel is designed to restore the contents of registers 23-25, 28 and 29 of block 1, performed by reading from the area allocated for this subchannel in block 2. To do this, the corresponding output 17 of block 6 at the output output of block 1 sequentially generates Five addresses of this subchannel (M + 1-M + 5), the contents of which are rewritten respectively into registers 23-25, 28 and 29. Next, the contents of register 25 are checked for equality to zero. If the condition is fulfilled, then it indicates that the command has been completed (all data has been transmitted), and therefore a transition is made to the firmware. The command is received. Otherwise (data transfer is not completed), the transition to the firmware is executed. Execution of the command.

Firmware The command is received as follows.

Using signals from output 17 of block 6, the contents of register 23 are sent to register 34 of block 1. At output 13 of the device, a Read signal is generated, and the command code is read from the external memory. At the same time, the output 19 of block 6 generates a signal that opens the block 4 for reading. As a result, the command code goes to the information inputs of blocks 1 and 6. The upper eight bits are written to register 28, and the lower eight bits are written to register 25 of block 1. The address of the next microcommand is determined by the code received at information input of block 6, for which. the second inputs of the block of 41 elements And the signal of the logical unit is supplied from the corresponding output of the block 39.

In the event that an unconditional jump command is received, the jump is made to the Unconditional Jump firmware. In the second word of this command, the address of the next program command is indicated. Therefore, using signals at output 17 of block 6, the contents of register 23 of block 1 are incremented by one and written to register 34. Next, the read operation of the external memory at the address in register 34 is performed, and the information is written to register 23 of block 1, i.e. The address of the next program command is recorded. At this action, the commands end and the transition to the firmware is carried out. Reception of the command.

In the event that commands are received to transfer data from an external memory to a subscriber or transfer data from a subscriber to an external memory, the transition is made to the beginning of the microprogram, in which the contents of the register 23 of unit 1 are increased by one, and then from the external memory by The address indicated in register 23 is read into information and is written to register 24 of block 1. By meaning, this information is the starting address of the external memory area to which or from which data is transmitted from or to the subscriber, respectively. Next, the contents of register 23 are incremented by one, and the transition to the microprogram is executed. The command is executed.

If a control byte is sent to the subscriber, a transition is made to the microprogram, where the contents of register 23 are incremented by one, and then the transition to the microprogram is executed. Execute the command.

If the command Completion of an I / O program has been received, the transition to the firmware is performed, which is performed as follows:

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zom. In register 34, the address no. + 2 is formed, according to which the previously formed contents of register 33 are written into the external memory, which is the exit code of the I / O program upon the command Completion of the I / O program. Register 26 is zero, i.e. the indication of the presence of the task in the subchannel is canceled. In addition, at the output 15, an Interrupt signal is generated, by which the CPU is notified of the completion of the I / O program, and the external memory location cell Kch2 indicates the reason for which the I / O is completed. A transition is then made to the firmware. Write the registers to the subchannel.

Firmware The execution of a command performs data transmission between the device and the subscriber and the transmission of data. According to the synchronization signal received by one 25 of the lines to exit 9 (on the remaining lines the code is the subscriber number), the subscriber whose number is formed at the input-output 10 is switched on to continue the communication session. Then, at output 9, a code is set which is decoded by the subscriber as a sign of the need to form an answer about

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that it is included. As a result, an input subscriber number is formed at the input-output 10, which enters through information block 3 on information input of block 1 and is written to register 30. Next, the numbers of the subscribed and requested subscribers are compared by comparing the contents of registers 29 and 30. In the event that these numbers do not match, in the register 33 an error code is formed Incorrect addressing. This action of the program ends, since the continuation of the communication session is impossible. A transition is made to the firmware where actions are taken to bring this message to the central processor.

If the transmitted number and the received subscriber number coincide, this indicates that the subscriber is turned on correctly, and at output 9 a code is generated that is decoded by the subscriber as a signal that information is being sent to the input / output 10 about the state (free - busy) of the subscriber. . In this case, the input sample block 3 receives

The opening block 3 and the information are fed to the information input of block 6. At the same time, the second and fourth outputs of block 39 of block 6 form codes that ensure the formation of logical zeros on the first and third inputs of block 44 of the OR elements. As a result, the transition to the next micro-command is made taking into account the subscriber's status information. If the subscriber is busy, a transition is made to the firmware. Writing registers to the subchannel. If the subscriber is free, the contents of register 28 (command code) is sent to register 33, shaper 35 is opened, and information is received at information input of block 6 and then through the block of elements AND 41, the block of elements OR 44, the element 42 and the element OR 45 is applied without distortion to the inputs of the register 36, where it is fixed by another sync pulse. Thus, the code analysis of the executed command is performed, i.e. selection of the initial microprogram address to continue communication with the subscriber depending on the command code being executed.

The command continued to transmit the control byte to the subscriber consists in forming at output 9 a code that is decoded by the subscriber as receiving the control byte, and at input-output 10 - directly the control byte code stored in register 25 of block 1. By the synchronization signal the control the byte is transmitted to the subscriber, and a transition is made to receive the next program command.

The command continuation Transferring data from external memory to the subscriber consists in reading information from the external memory at the address stored in register 24 and writing it to register 33 of block 1, and then transferring it to input-output 10 of the device. At output 9, a code is generated that is decoded by the subscriber as data transmission to the subscriber. According to the synchronization signal data from the input-output 10 for-; to the subscriber.

Then the contents of the register 24 of block 1 are incremented by one (the address of the data in the external memory), and the counter of the amount of information transferred (register 25) is decreased by one, after which the contents of register 25 pro5

is believed to be equal to zero. If this condition is fulfilled, then all the information by this command is transmitted and therefore a transition is made to the firmware. The command is received. Otherwise, the command is not completed and therefore the transition is made to the firmware. Write registers to the subchannel. Such a variant of building a command is possible if the subscriber speed is significantly lower than the device.

 Continuing the command. The transfer of data from the subscriber to the external memory consists in the formation at output 9 of a code which informs the subscriber that the device is ready to receive information from it. As a result, the information from the subscriber through the unit 3 enters the information input of unit 1 and is written to the register 33 of this block, and then written to the external memory at the address stored in

5 register 24. Further actions are similar to those of the command Transfer data from external memory to subscriber1.

Firmware Writing registers to the subchannel provides a fixation

Q contents of registers 23-26, 28 and 29 in block 2 in the corresponding subchannel. To form the start address of the subchannel, the contents of register 27 are reduced by five. At the end of this firmware is carried out

transition to the microprogram Analysis of the presence of the task in the subchannel, which determines the presence of the task in the next 1 subchannel, since the contents of the register in Q 27 after writing all the registers to the subchannel contain the starting address of the next subchannel.

Claims (2)

1. A firmware device for interfacing the processor with subscribers, comprising a firmware control unit and a communication unit with subscribers, the setup and synchronization inputs, and the first output of the firmware control unit, are respectively the device inputs for connecting to the processor start and synchronization outputs and the device output for connecting the subscriber's control input, sample input, the first and second information inputs-outputs of the communication unit with the subscriber 13- connected to the second output of the sample, the information input of the microprogram control unit and the input-output of the device for connection to the information input / output of the subscriber, characterized in that, in order to increase the speed of the device, an operational block, an operating memory block, an address register are entered into it and the communication unit with the processor, the interrupt input, the interrupt outputs and the request for the firmware control block are respectively an output of the device for connecting the interrupt output of the processor and The outputs of the device for connecting the interrupt and processor readiness inputs, input conditions, the third, fourth, five and sixth outputs of the firmware control block sample are connected respectively to the transfer output of the operation unit and the synchronization inputs of the communication unit with the processor, address register and the sample inputs of the operational memory operating unit whose synchronization input is the input of the device for 14 0 five 0 five The rator is connected to the synchronization inputs of the first to ten registers respectively, the information output of the arithmetic logic unit is connected to the information inputs of the first to ten registers, the first information input of the switch and the output of the pulse former are connected to the information input-output of the block, the outputs of the first through the eighth registers are connected respectively from the second to the ninth information inputs of the switch, the output of which is connected to the first information input of the arithmetic logic node, W The information input and transfer output of which are connected respectively to the output of the ninth register and the transfer output of the block, the output of the tenth register is the address output of the block. 2. A device according to claim 1, characterized in that the microprogram control unit comprises first and second registers, first and second memory blocks, a trigger, first and second blocks of AND elements, a block of OR elements, first and second elements connecting the sync output of the pro AND and the OR element, the synchro controller inputs, the output output of the operation unit are connected to the address input of the operational memory unit and the information input of the address register, the output of which is the output of the device for connecting to the subscriber’s address input, information inputs / outputs the operating unit and the operating memory unit and the first information input / output of the communication unit with the processor are connected to the information input of the microprogram control unit, the second information input The output of the communication unit with the processor is the input-output of the device for connection to the information input-output of the processor, the operating unit contains a decoder, a switch, an arithmetic logic unit, a pulse shaper and the first to ten registers, and the inputs to the operating unit sampling arithmetic logic node pulse shaper controlling the input of the switch and the first input is the decryption-55 input of the first register and The rator is connected to the sample input of the block, the second input of the decoder is connected to the synchronization input of the block, from the first to ten outputs by the decrypting second input of the first element AND whose stroke is connected to the first input of the OR element, the second input and output of which are connected five 0 five 0 The initialization of the first and second registers is the synchronization input of the block, the zero input of the first register is the setup input of the block, the single and zero inputs and the trigger output are connected respectively to the block interrupt input, the first output of the second register and the first memory block output of which is connected to the first input of the first block of elements And, the second input and output of which are connected respectively to the first output of the second memory block and the first input of the block of OR elements, from the second to the sixth outputs of the second memory block and connected respectively to the information input of the second register, the first inputs of the first and second elements And the second block of elements And the second input of the block of elements OR, the third input and the first and second outputs of which are connected respectively with the output of the second block of elements And, the first information input of the first register and the second input of the first element AND, the output of which is connected to the first input of the element OR, the second input and output of which are connected respectively 151539787. sixteen With the output of the second element And the second information input and the input as the condition information input of the first register, the output of which is connected to the input of the second memory block, the second inputs of the second block of elements And and the second element And are respectively 23 2b 25 sn - - - & 26 12 : 27 28 The second and ninth outputs of the second register are the request, interrupt, and the first through sixth sample outputs of the block, respectively. one Kkhod 21blok 32 33 31 Sc FIG. 2