JPS60117983A - Transmission method of component video signal - Google Patents

Abstract

PURPOSE:To prevent the deterioration of the reproduced picture quality by inserting a reference signal having a prescribed frequency to each blanking section of a component video signal to transmit it together with a time division multiplex signal after compressing it down to a prescribed ratio and matching the phases of reference signals with each other. CONSTITUTION:The reference signals REF.Y and REF.C serving as the standards of each time axis are inserted in a prescribed vertical blanking period before the time axis compression is given to a luminance signal Y and a pair of color difference signals R-Y and B-Y. This inserting period is set at 1H - several H, and sine wave-shaped reference signals REF.Y and REF.C are inserted within a 1H period in this example. Therefore the signal REF.Y of 2X64fh is inserted in the first half 0.5h period of the 1H period after compression of time axis together with the signal REF.C of 4X64fh inserted in the latter half 0.5h period respectively. As a result, a clock generator 20 supplies a switching pulse Pe to switch a switching circuit 3Y-3B only in a prescribed horizontal period of a vertical blanking period V.BLK.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a component video signal transmission method that allows the component video signal to be transmitted over a single transmission path.

BACKGROUND TECHNOLOGY AND PROBLEMS There are two ways to transmit a video signal: one is to transmit the component video signal as it is, and the other is to convert it to a composite video signal and then transmit it.Recently, the former signal transmission method is preferred over the latter. has been adopted. This is because the former transmission method causes less deterioration in image quality during signal transmission and recording, and does not have the problem of color framing.

However, when the former signal transmission method is adopted, there is a drawback that three transmission lines are generally required.

Therefore, an attempt has recently been announced to compress each line of component video signals and transmit and record them over a single transmission path.

For example, as shown in FIG. 1A-C, a luminance signal Y1 and a pair of component color signals, for example, a pair of color difference signals R-YS
In the case of a component video signal consisting of B-Y, the time axis of the luminance signal Y is compressed twice, and a pair of color difference signals R-Y
, B-Y are compressed four times to form a time division multiplexed signal as shown in the first diagram. In this case, the signal band of the component video signal becomes a wide band (the band of the luminance signal Y is 4.5 MH2, so approximately 9.OMflz), but it can be transmitted through one transmission path.

When receiving this time division multiplex signal and converting it into the original component video signal, a reference signal for time axis conversion inserted into the time division multiplex signal is used. A horizontal synchronization pulse PH is generally used as the reference signal.

However, when using the horizontal synchronizing pulse PR, if the phase of the horizontal synchronizing pulse PI (PI) shifts slightly due to passing through the signal transmission system and recording system, the luminance signal Y, color difference signal RY,
Since the compression ratios of BY are different, the luminance signal Y after signal conversion and the pair of color difference signals R-Y and B-Y are out of phase.

That is, as shown in FIG.
By causing a phase shift by t, the sampling start point of the time-division multiplexed signal is at the same point Δ, as shown in Figure 2C.
Since there is a difference of t, the difference between the decoded luminance signal Y and color difference signal R-Y (same for B-Y) is 4Δt (second
Figure, E). This shift causes a significant deterioration in image quality.

Purpose of the Invention Therefore, the present invention uses a simple configuration to eliminate the Y/C phase shift that occurs when transmitting and recording time-division multiplexed signals.

SUMMARY OF THE INVENTION Therefore, in the present invention, a reference signal having a predetermined frequency is inserted into each vertical blanking section of a component video signal, and this reference signal is compressed by the predetermined compression ratio and transmitted together with the time division multiplexed signal. By adjusting the phase of each reference signal during encoding,
This eliminates the phase shift between Y and C during encoding.

EmbodimentNext, an example of the invention will be described in detail with reference to FIG. explain.

FIG. 3 is an example of a digital time division multiplex signal forming circuit αφ provided in a recording system that converts a component video signal into a time division multiplex signal and records the signal.

The luminance signal Y supplied to the terminal (IY) is sent to the A/D converter (
2Y) is converted into a digital signal. The sampling frequency is 826N+' (fh is the horizontal frequency) in this example. The digital signal is sent to the memory device (4Y) via a switching circuit (3Y) for reference signal insertion, which will be described later.
supplied to

The memory device (4Y) is composed of two memories (5AY) and (58Y) having an IH memory capacity, and is controlled so that when one memory is in the write mode, the other memory is in the read mode.

For this purpose, there is a switching circuit (5AY>, (5BY)) that is switched alternately for each IH on the exit side of the memo (5AY>, (5BY).
6v) (7v) is provided. Memory (5AY),
(58Y) is controlled by a control signal from a clock and control signal generator (20). (30) is a mode control circuit, which includes a pair of AND circuits (318) and (31B) and a pair of switches (34A) for the memory device (4Y).
), (34B). First, 626f
The write clock of h is connected to a pair of switches (34A), (
34B) via a pair of AND circuits (31A), (
31B ), and a changeover switch (37) to which the 1252fh read clock is switched according to the read mode, and a pair of switches (34A) and (34B
) through a pair of AND circuits ((31A), (31
B).

All these controls are performed by the output of a clock generator (2o) that includes a memory control function.

The digital luminance signal Y whose time axis has been compressed to 1/2 is supplied to the switching circuit (38).

A pair of color difference signals R supplied to terminals (IR) and (IB)
-Y and BY are also subjected to similar signal processing. That is, these pair of color difference signals R-Y and B-Y are converted into digital signals by A/D converters (2R) and (2B), respectively, and sent to the memory via the next switch circuits (3R) and (3B). It is supplied to devices (4R) and (4B) and time-axis compressed.

These memory devices (4R) and (4B) have the same configuration as the above-mentioned memory device (4Y). (5AR), (5
BR), (5AB), (58B) are memory,
(6R), (6B), (7R), and (7B) are switch circuits.

In addition, in order to control these, AND circuits (32
A) to (3211), and four switch circuits (3
5A) to (36B> are provided. These are directly or indirectly supplied with a write clock of 313fh and a read clock of 1252fh.

Since the read clock has a frequency four times that of the write clock, a digital color difference signal RY 5B-Y whose time axis is compressed four times is obtained from the memory devices (4R) and (4B).

The digital luminance signal Y and the digital color difference signals R-Y, B-Y whose time axes have been compressed are supplied to a switch circuit (38), and the digital luminance signal Y and the digital color difference signals R-Y and B-Y are supplied to the switch circuit (38), and the digital luminance signal Y and the digital color difference signals R-Y and B-Y are supplied to the switch circuit (38), and the digital luminance signal Y and the digital color difference signals R-Y and B-Y are supplied to the switch circuit (38), and, as shown in FIG. Signal Y is inserted, and the second half (j, 5
Of the 11 periods, the digital color difference signal R-Y is inserted in the first half of the 0.25H period, and the digital color difference signal B-Y is inserted in the second half of the 0.25H period, resulting in the time series shown in the first diagram. A digitized time division multiplexed signal is formed. Therefore, the gate pulse Pa shown in FIG. 4C is supplied to the AND circuits (31A) to (33B), and
The pair of switch circuits (34A) and (34B) receive the gate pulse pb of the same figure, and the pair of switch circuits (35
A) and (35B) are supplied with the gate pulse Pc of E in the figure, and the remaining switch circuits (368) and (36B) are supplied with the gate pulse Pd of F in the same figure, respectively.

In addition, the switch circuit (37) is a clock generator (20)
Switching is controlled by a control pulse Py from . In other words, the memory device (4Y) is in read mode during the first half of the 0.5H period, and the memory device (4R) is in the read mode during the first half of the second half of the 0.5H period.
is in the read mode, and the memory device (4B) is controlled to be in the read mode during the latter half period of 0.25H.

A synchronization signal is added to the digital time-division multiplexed signal output in a time-division manner by the switch circuit (38) by a synchronization addition circuit (39) at the subsequent stage. This time-division multiplexed signal is converted into an analog time-division multiplexed signal by a D/A converter (40), and then this time-axis compressed analog time-division multiplexed signal is recorded using a recording head (not shown). be done.

Now, in this invention, a pair of color difference signals R-
Before compressing the time axis of Y, B-Y, the reference signal R1, which becomes the reference of each time axis, is generated during a predetermined period of the vertical blanking period. F-'l, REF-C is inserted. The insertion period is from IH to several H, and in this example 11
A sine wave-like reference signal Rf over a period of ! F-Y.

REF-C is inserted (Fig. 5A, B). Reference signal R
The frequencies of EF-Y and REF-C are intermediate frequencies in the frequency band of the luminance signal Y, for example, 64f.
h (#IMHz). Therefore, after time axis compression, as shown in Figure 5C, during the IH period, the first half of 0.5 hours
The period is 2X64fh(7) reference signal R1! F-Y is
The second half (7) 0.5h period is a 4x64fh reference signal R.
This means that each EF-C has been inserted.

Therefore, the clock generator (20) supplies a switching pulse Pe for switching the switch circuits (3Y) to (3B) only during a predetermined horizontal period of the vertical blanking period ν.BLK.

In fact, these reference signals REF -Y, REF
・C is inserted in a digitally processed state.

(42) is its digital generator. Of course, the reference signals REF-Y 5REF-C are converted to A/D converters (2Y
) to (2B) may be inserted in the form of an analog signal.

Further, the reference signal REF-C is one of the color difference signals, for example, R-
It may be inserted only in Y.

FIG. 6 shows an example of a reproduction system (50).

The reproduced analog time-division multiplexed signal is supplied to the A/D converter (52) through the terminal (51), where it is once converted into a digital signal, and is also stored in a memory device (41 ( (4Y) to (4B)).The time division multiplexed signal is also supplied to a synchronization separation circuit (53) to separate the horizontal and vertical synchronization signals H1■, and the horizontal synchronization signal H is phase-shifted. PLL via the device (54)
(55).

,: (7) PLL (55) includes a VCO (56) that oscillates 1252fh, a counter (57) that steps down this to 1/1252, and its output signal fh and input signal fh.
fh, which is phase-locked to the human input signal fh, and a phase comparator (58) that performs phase comparison with the human input signal fh.
The output signal of 125 h is supplied to the memory control circuit (60), and the digitized time division multiplexed signal is
The data is written to the memory device (4) in synchronization with 2fh.

The writing timing to the memory device (4) is delayed by 126 samples from the rising edge of the horizontal synchronizing signal PH.

Reading is performed based on a clock generated by a clock generator (61). That is, the digital luminance signal V
is read out with a clock of 626fh, and the digital color difference signals R-Y and B-Y are read out with a clock of 313fh. This returns the time axis to the original time axis. And D/A
The signals are converted into analog signals by converters (62) to (64). These are band-limited by low-pass filters (65) to (67) and then supplied to each output terminal (68) to (70). Gate circuits (72) and (73) are further provided at the output ends of the low-pass filters (65) and (66) to gate the respective reference signals RHF-Y and REF-C. (74) is a gate pulse forming circuit.

Gated reference signals REF-Y, REF-C
The phases of the two are compared in a phase comparator (75), and the phase shifter (54) is controlled by the phase comparison output, and the input signal f
The phase of h is controlled.

Here, the timing for writing data into the memory device (4) is determined based on the rising edge of the horizontal synchronizing pulse PH, as described above. Since the horizontal synchronizing pulse PH is separated by comparing the rising edge of this pulse I'H with a reference level, if the waveform of the horizontal synchronizing pulse PH is slightly distorted by passing through the recording system, Because the horizontal synchronization pulse pH is separated at the same reference level, the result is the same as the phase shift of the horizontal synchronization pulse (5th
(Illustrated with dashed lines in Figure C). Therefore, when the data write timing is at the regular timing, the phases of the reference signals REF-Y and REF-C match as shown in Figure 5 and E, whereas the data write timing is at the regular timing. If the reference signals REF-Y and RHF-C deviate from each other, the reference signals REF-Y and RHF-C are reproduced out of phase, as shown in F and G in the figure. This phase difference results in color shift, and if left as is, the reproduced image will deteriorate significantly.

Therefore, in the present invention, the phase of the input signal fh is shifted until the two phases match. Specifically, the amount of phase shift of the phase shifter (54) is controlled by the phase comparison output, and the output signal f
The phases of h and 1252fh are controlled. As a result, the write timing to the memory device (4) is shifted in the direction of regular write timing, so that the relative time difference between the reproduced luminance signal y and the reproduced color difference signals R-Y, B-Y is reduced. Corrected.

Reference signal R11: F-Y and REF-C do not need to have the same frequency. For example, the reference signal REF-Y is set to 64f.
h, the other reference signal REF-C is selected as
If the frequency 32fh of /2 is selected, the frequency after time axis compression becomes the same and receives the same transmission distortion, so the group delay distortion also becomes the same, and the influence of different group delay distortions can be removed. At this time, the reference signal R[! The other reference signal R[! is based on the extraction gate pulse of P-C. A gate pulse for FC is formed.

In addition, if the first half frequency and the second half frequency of the reference signal REF-Y inserted at a predetermined position of the vertical blanking period V-BLK are changed as shown in FIG. Since it is also possible to detect deviations in group delay caused by transmission, distortion in frequency characteristics and group delay distortion caused by passing through the transmission system can be easily corrected.

In the example of FIG. 7, the frequency of the reference signal RHF4a inserted in the first half period of 0.5H is selected to be 64fh, while the frequency of the reference signal REF4a inserted in the second half period of 0.511H is selected as 64fh.
- The frequency of Yb is selected to be 256fh, which is four times that frequency.

As described in detail, according to the present invention, it is possible to easily and accurately correct the YZC deviation caused by passing through a transmission system such as a recording system, thereby preventing deterioration of reproduced image quality. In addition, according to another embodiment, the distortion itself in the transmission system can be detected, so that a high-quality reproduced image can be obtained.

[Brief explanation of the drawing]

1 and 2 are waveform diagrams for explaining the present invention, and FIG. 3 is a digital time division multiplex signal forming circuit provided in a recording system showing an example of the case where the present invention is applied to a VTR.
FIG. 4 is a waveform diagram for explaining its operation, FIG. 5 is a system diagram showing an example of its reproduction system, and FIGS. 6 and 7 are waveform diagrams for explaining its operation. Qω is a digital time division multiplex signal forming circuit, (50) is a reproduction system, and REF-Y 5REF-C is a reference signal. Figure 1 tlJ Figure 4 Figure 5

Claims (1)

[Claims] In a device in which component video signals are compressed using different compression ratios and transmitted as time division multiplexed signals, a reference signal having a predetermined frequency is inserted into each vertical blanking section of the component video signal, and this reference signal is transmitted as a time division multiplexed signal. A method for transmitting a component video signal, wherein the component video signal is compressed at the compression ratio and transmitted together with the time division multiplexed signal.