JPS60117878A - Facsimile signal processing circuit - Google Patents

Abstract

PURPOSE:To attain ease of processing by means of a microprocessor by providing a counter circuit constituted to be restored to the initial value at each detection of a line synchronizing code and a processing circuit including the microprocessor or the like and allowing the processing circuit to process an n-bit parallel output of a shift register every time the counter circuit takes the initial value so as to make the line synchronizing code in a facsimile signal coincident with a byte or word boundary. CONSTITUTION:A facsimile signal subject to redundancy compressing coding is inputted to a shift register 1 via a terminal 11, shifted one by one bit sequentially in matching with the timing signal inputted via a terminal 12 and 12-bit parallel outputs Q0, Q1,..., Q11 are obtained. The outputs Q0,..., Q11 of the shift register 1 are inputted to a line synchronism detecting circuit 2, where the pattern of the line synchronizing code is detected, the line synchronism detection signal is outputted and a counter circuit 3 is reset. On the other hand, the counter circuit 3 applies 1/8 frequency-division to a timing signal inputted from the terminal 12. An output of a register 4 sectioned into 8-bit and an output pulse of the counter circuit 3 are inputted to a processing circuit 5 so as to attain the signal processing in the unit of 8-bit by means of the microprocessor or the like.

Description

DETAILED DESCRIPTION OF THE INVENTION A. Field of Industrial Application The present invention relates to a redundancy compression encoded facsimile signal processing circuit. The present invention relates to a circuit for matching a synchronization code (EOL code) to a byte or word boundary, which is a processing unit of a microprocessor.

Conventional technology As a redundancy compression encoding method for facsimile signals, the Modified Huffman encoding (MH encoding) method, and the Modified Read encoding (MR encoding) method is an international standard encoding method. It is well known as.

These encoding methods are described in, for example, the Institute of Electronics and Communication Engineers, ed. 1, New Edition: Fundamentals and Applications of Facsimile @ (published September 10, 1980). According to its contents, for example, M
H-encoding is a method that encodes one scanning line (continuous white or black run) with a variable length code according to the statistical probability of appearance of a white or black run. A line synchronization code (EOL code) is inserted. Therefore, the above-mentioned MH-encoded facsimile signal has a different amount of data for each -scanning line.

On the other hand, in order to meet various recent market demands, facsimile signals are often processed by microprocessors. As is well known, microprocessors are generally 8-bit (
It is suitable for processing on the basis of some suitable unit of 16 bits (bytes) or 16 bits (words). It is not very suitable for processing that requires bit-by-bit processing and involves real-time processing, such as the MH encoded facsimile signal. However, if a microprocessor must be used to satisfy the diversity of services, the above bits can be achieved by using a very high-speed microprocessor or by adding dedicated large-scale hardware. Processing is in progress.

C.1 OBJECTS OF THE INVENTION An object of the present invention is to provide a facsimile signal processing circuit that allows line synchronization codes in facsimile signals to coincide with byte or word boundaries to facilitate processing by a microprocessor.

20 Structure of the Invention The present invention takes as input a facsimile signal encoded with redundancy compression, and uses the number of bits (12
A shift register capable of parallel output having a number of bits (bits) or more and a parallel processing unit of n bits (byte or word unit, etc.) or more by a predetermined microprocessor, etc., and a parallel output of this shift register. A line synchronization detection circuit detects a line synchronization code as an input, counts the number of facsimile signal nobits input to the shift register, returns to the initial value every n, and detects a line synchronization code by the line synchronization detection circuit. A counting circuit configured to return to an initial value each time a value is detected, and a processing circuit including a microprocessor, etc., and each time the counting circuit takes an initial value, the n-bit parallel output of the shift register is processed by the processing circuit. configured to process.

E, Example Next, the present invention will be explained by examples.

FIG. 1 is a circuit block diagram of an embodiment of the present invention, and FIG. 2 (
a) to (f> are time charts for explaining the operation of the embodiment in FIG. 1. First, in FIG.
A redundancy compression encoded facsimile signal shown in FIG. 2(a) is input to the shift register 1 via the shift register 1.

Figure 2(a) shows 1667 bits of white (16 bits of make-up).
64 + termination 3) followed by black 61 bits representing the MH encoded facsimile signal for one scan line, including the line sync code (EOL), -3 per scan line.
Contains 4 bits of information. Such a facsimile signal inputted to the shift register 1 via the terminal 11 is sequentially shifted by one bit in accordance with the timing signal inputted via the terminal 12 in FIG. 12-bit parallel output (Q,,Q,.

..., Qth) is obtained. In FIG. 2(b), for convenience, "01" is represented by white and 111 is represented by black.The output Qo+...+Qll of the shift register 1 is input to the line synchronization detection circuit 2.The line synchronization detection circuit 2 , that is, a pattern of (000000000001) is detected and a line synchronization detection signal as shown in FIG. On the other hand, the counting circuit 3
The frequency of the timing signal input from the oscilloscope is divided into 1/8.

Therefore, counting is performed as shown in FIG. 2(d) while being reset each time the line synchronization detection signal is input. Then, the counting circuit 3 outputs a pulse as shown in FIG. 2(e) when the initial value is -0'. This pulse is input to register 4, and the 8-bit output Q on the MSB side of shift register 1
4°..., remember Qll. Therefore, the output of register 4 is (00, 16, 20,
16°80 (in hexadecimal notation, Q+1 is the MSB). This is the same as the code in which the EOL code is divided into 8-bit units starting with the first bit ih, and G bits of fill bits for byte boundary adjustment are added to the end of the black terminating code. The output of the 8-bit divided register 4 and the output pulse of the counting circuit 3 are input to the processing circuit 5, and the microprocessor! #
= signal processing can be performed in 8-bit units.

6 Effects of the Invention As described above with respect to an embodiment of the present invention, according to the present invention, line synchronization codes can be aligned with byte boundaries by adding a simple circuit. It becomes possible for the processor to process line synchronization code detection on a byte-by-byte basis, and the processing ability of the microprocessor can be further improved. Moreover, 101 is added to the end of the significant code of one scanning line for byte boundary alignment, but this IQI signal is treated as a meaningless signal in the redundancy compression code, that is, a fill bit, so it is processed as a factor-only signal. It does not affect the processing of the example.

Note that although the above explanation deals with aligning the position of the line synchronization code with a byte boundary, it goes without saying that the same process can be performed even on a word boundary, etc., and the same applies to MR codes, etc. do not have.

[Brief explanation of drawings]

Fig. 1 is a block diagram of an embodiment of the present invention, Fig. 2(a)
-(f) are time charts for explaining the operation of the facsimile signal processing circuit shown in FIG.

Claims (1)

[Claims] Inputs a facsimile signal encoded with redundancy compression,
A shift register capable of parallel output, which has more than the number of bits required for line synchronization code detection (12 bits) and more than n bits (byte or word unit, etc.) in a predetermined parallel processing unit by a microprocessor, etc. , a line synchronization detection circuit that receives the parallel output of the shift register and detects a line synchronization code, and counts the number of bits of the facsimile signal input to the shift register and returns to the initial value every n, and A counting circuit configured to return to an initial value each time a line synchronization code is detected by a line synchronization detection circuit, and a processing circuit including a microprocessor, etc., each time the counting circuit takes an initial value. A facsimile signal processing circuit characterized in that the processing circuit processes n-bit parallel output.