JPS6010939A - Data transmission equipment - Google Patents

Abstract

PURPOSE:To attain fault location by checking the propriety of a reception frame independently of whether a frame is addressed to the own station or not in data transmission. CONSTITUTION:An optical signal from a transmission line 14 is converted into an electric signal by a photoelectric converting circuit 30 and the result is fed to a control circuit 32. A signal from the control circuit 32 is converted into the light signal by the electrooptic converting circuit 30 and the result is transmitted to a transmission line 11. The control circuit 32 fetches a data addressed to the own station and transmits the transmission data to an opposite station after adding an address. Further, the controller 32 executes frame check of all reception frames and if a fault exists, the frame is erased and it is informed to a supervising station at the same time.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical field to which the invention pertains] The present invention relates to a method for detecting failures due to pit sequence frames in a data transmission system formed in a loop.

[Description of prior art]

Conventionally, failure detection methods using pit sequence frames in this type of loop data transmission system have been configured to check the validity of frames only for frames addressed to the own station, and count each time an abnormality is detected. Ta. This method is certainly effective if there is an abnormality in the receiving circuit, but if there is an abnormality in the loop transmission line or the through circuit of each data transmission device, each data Since data can be freely transferred between transmission devices, there is a drawback that it is difficult to know in which section an error occurred. Another conventional failure detection method is to simply detect a frame validity error and manage it only at the station that detected the error, or to detect that there is a frame validity error somewhere in the loop. Because the system only reports on errors, even if it is possible to know that there is an abnormality on the transmission path, the system has the disadvantage that it cannot tell which part of the looped transmission path is causing the temporary failure. Ta.

In devices that use ICs as component parts, it is often the case that a temporary failure occurs at first, and then the circuit gradually breaks down, rather than causing a fixed failure immediately.

These methods have the disadvantage that it is difficult to know the location of an abnormality at the stage of a temporary failure.

[Purpose of the invention]

The present invention improves on this and aims to provide a data transmission system capable of detecting the location of a temporary fault.

[Features of the invention]

In other words, the present invention checks the validity of the frame regardless of the signal frame addressed to the local station in order to quickly detect the situation of temporary power failure in the transmission path, and when an abnormality is detected, This frame is erased so that the data transmission device connected to the lower level does not check the validity of this frame, and further configured to notify a specific data transmission device that an abnormality has been detected. It is characterized by

That is, the present invention checks the validity of a frame regardless of whether the frame is addressed to the own station in a data transmission device that transmits data between a plurality of devices and transfers frames of a pit sequence via a loop-shaped transmission line between the transmitting devices. If there is an abnormality when checking the validity of the frame,
A means for erasing a frame without transmitting the frame to a data transmission device connected to a lower level of a loop-shaped transmission path, and every time an abnormality in the validity of the frame is detected, this is notified to a specific data transmission device. It is characterized by comprising means.

[Explanation of Examples]

Next, an embodiment of the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 is a diagram showing a configuration model of a system to which the present invention is applied. The data transmission devices 1 to 4 are connected in a loop-like manner by transmission lines 11 to 14, and the transmission lines 11 to 14 are optical fiber transmission lines in this example.

Next, referring to FIG. 2, in the apparatus according to the embodiment of the present invention, an optical-to-electric conversion circuit 30 is inserted into a path from which the transmission line 14 inputs and outputs to the transmission line 11, and the signal converted into an electric signal is
It is coupled to the transmission line control circuit 32 by a clock line 51 that transmits a clock signal and a data line 52 that transmits data. Further, a clock line 54 for sending a clock signal to the transmission line 11 and a data line 55 for sending data to the transmission line 11 are connected to the transmission line control circuit 32 and the optical-to-electric conversion circuit 30.
Connect between.

FIG. 3 is a detailed diagram showing the block configuration of the transmission path control circuit 32. As shown in FIG. This circuit includes a frame detection circuit 101 that detects frames coming in from a transmission path, a FOE (frame check sequence) check circuit 102 that checks the validity of received frames, and sends received frames to data transmission equipment of other stations. FO circuit 103 for temporary storage. Also, a crystal oscillation circuit 106 that generates a clock signal that is the basis for sending out the transmission frame;
Converts the received serial data to parallel data and
A shift register 111 that sends serial data to the CS check circuit 102 is provided. Furthermore, it is set when a validity error (hereinafter referred to as Foe error) occurs in the abort (failure) pattern generation circuit 112 for erasing passing frames and the WaS check circuit 102, and the abort generation circuit 112 It includes a seven flip-flop 114 that is the source of activation and frame erasure, flip-flops 115 and 116 that synchronize the clocks of the flip-flop 114, and a flip-flop 117 that temporarily stores transmission data.

A frame transmitting circuit 104 that creates a frame to notify Sarani and FOE errors and sends it to the transmission path.
Equipped with Furthermore, for each signal, 301 is the activation signal of the Fos check circuit, 302 is the FCS check end signal indicating the end of the calculation of the Fcs check circuit, and 3 is the mismatch signal that occurs when the FO8 calculation result does not match the correct value.
04, the abort end signal that is generated when the abort pattern generation circuit 112 finishes generating the abort pattern.
05 (pulse generated) A transmission end signal indicating the end of the operation of the frame transmitting circuit 104 is displayed as 306 (pulse generated).

Furthermore, the flip-flop 11 is set by the abort end signal 305 and activates the frame generation circuit 104.
8, selectors 121 and 122, a receiver 201, a driver 202, and a NAND circuit 203.

Next, the overall configuration of each of the above parts will be explained. The data line 52 and the clock line 51 are connected to the frame detection circuit 101, the F/FO circuit 103, and the shift register 111 via separate receivers 201, respectively. Connected to input. One signal 3 of the frame detection circuit 101
01, the output of the shift register 111, and the clock pulse input of the shift register 111 are input to the FOS check circuit 102. the other output via the signal 302 of the frame detection circuit 101 and the clock pulse input of the shift register 111;
The output of the FCS check circuit 102 via the signal 304 is input to the NAND circuit 203. The output of the FO circuit 103 is input to the selector 121.

The output of the NAND circuit 203 is a flip-flop.

Input to 1140S terminal. The output of the crystal oscillator circuit 106 is coupled to the C terminals of flip-flops 115 and 116 cascaded to the flip-flop 114, and also coupled to the inputs of the abort (fault) turn generation circuit 112 and frame transmission circuit 1040.

The output of the flip-flop 116 is the selector 121
and is input to the abort pattern generation circuit 112 and the F/FO circuit 103, respectively.

One output of the aport pattern generating circuit 112 is input to the selector 121, and the other output is input to the flip-flops 114 and 118.

The R input and output of the flip-flop 118 are
0"6・1ゞl;+e7!J/2 to 7901104
.

The output of the flop 118 and the output of the frame transmission circuit 104 are connected to the selector 121K and the selector 1 connected in cascade.
22 respectively.

The output of the crystal oscillator 106 is input to a flip-flop 117 connected in cascade to the selector 122, and is also output to the clock line 54 via the driver 202.

The output of the selector 122 is the above Fritz 7" 7 o y
It is output to the data line 55 via the driver 202 and the driver 202.

FIG. 4 is a diagram showing an example of the structure of a signal frame applied to the present invention. “F” is a flag turn [011111
10J, "DA" indicates the destination address, and "
sAJ indicates the source address, rOJ indicates control information, "I" indicates data information, and "FC8" contains a cyclic redundancy check bit to check whether the frame was transferred correctly in the frame check sequence. show.

Here, the FOEI error is caused by the PCB check circuit.
This means that the sent data DA to Foe are decoded and do not match the correct value (see J-Eng. 80636B).

Next, the operation of the embodiment of the present invention will be explained. Now, in Figure 1,
The operation of the data transmission device 1 will be described in the case where a frame is transferred from a specific data transmission device to the data transmission device 2 and from the data transmission device 4 to the data transmission device 3. The optical signal input through the transmission line 14 is converted from an optical signal to an electrical signal in the optical-to-electrical conversion circuit 30, and an information frame is transmitted to the control circuit 32 via a clock line 51 and a data line 52. This signal frame is shifted bit by bit into the shift register 111 according to the reception clock 51, and at the same time, the frame detection circuit 101 detects a flag and turns on the FOE check circuit activation signal 301. , Foe check circuit 102 starts calculating (decoding) F, O8. When the frame detection circuit 101 eventually detects a flag indicating the end of the frame, FoS check end signal 302
The mismatch signal 304 is checked. At this time, the discrepancy signal 304 d! If it is on, the output signal of the NAND circuit 203 sets the F1) block flop 114.

On the other hand, the bit serial data arriving on the data line 52 is also input to the FO circuit 103. Crystal oscillation circuit 106
According to the clock generated from the FO circuit 103, bit serial data is sent to the selector 122 in order
, the flip-flop 117, the driver 202, and the optical/electrical conversion circuit 30, and then sent to the transmission line 11.

If the frame is normal, the flip-flop 114 is not set, so the frame addressed to the data transmission device 3 is correctly transmitted to the transmission line 11. However, if one bit in the frame causes what is called "one data garbled" due to a temporary failure in the transmission line 11, etc.
The FOE check circuit 102 detects a FOEI error,
The mismatch signal 304 is turned on. At the same time that the FCS check end signal 302 turns on, the flip-flop 114
is set and activates the aport pattern generation circuit 112. As a result, the aport pattern data "1111111100000000" is sent to the selector 121 in order in the pit sequence. While the flip-flop 114 is set, the selector 121 selects the aport pattern data and erases the frame being transmitted from the FO circuit 103.

Here, "6 erasure" means when seven or more "1"s continue in a frame.

When the aport pattern has been sent, the aport end signal 30
5 line is turned on, flip-flop 114 is reset, flip-flop 118 is set, and frame transmitting circuit 104 is activated. flip flop 118
When is set, the selector 122 selects the take coming from the frame transmitting circuit 104, and when the frame transmitting circuit 104 is activated, "F", rDAJ (address of specific data transmission device 2), "SA" (address of own station's data transmission device 1), "C" (command representing control information), "J" (information indicating that a FoS error has occurred), "FC8", and rpJ are automatically sent in sequence. do. This frame passes through the optical/electrical conversion circuit 30 and becomes a transmission path.

11 and is transmitted to the specific data transmission device 2.

When the transmission ends, the transmission end signal 306 is turned on, the flip-flop 118 is reset, and the operation ends. Therefore, the "pass-through frame" is erased from the transmission line 11, and a frame indicating that a FoS error has been detected is sent to the data transmission device 2 instead.

In this way, each time a FOEI error is detected,
The above operation is performed to cause the specific data transmission device 2 to report. Therefore, in a particular data transmission device 2 that normally performs loop monitoring, by counting the number of Fos errors, it is possible to estimate where in the loop a temporary failure is occurring from the system's perspective.

Note that the present invention can be implemented in the same manner even when a FOEI error is detected by the specific data transmission device 2 itself. In the above description, only one loop-shaped transmission line is used, but the present invention can be implemented in the same manner even if there are a plurality of loop-shaped transmission lines.

[Explanation of effects]

As explained above, the present invention checks the validity of the frame regardless of whether it is a frame addressed to the local station, and stores the number of frame erasures and FCS errors. This has the effect of being able to identify whether the

[Brief explanation of the drawing]

FIG. 1 is a schematic diagram showing a loop-shaped transmission system to which the present invention is applied. FIG. 2 is a block diagram showing an embodiment of the present invention. FIG. 6 is a detailed block diagram showing an embodiment of the transmission control circuit of FIG. 2. FIG. 4 is a diagram of the frame shape of the signal of the present invention. 1-4... Data transmission device, 11-14... Transmission line, 30... Optical/electric conversion circuit, 32... Transmission line control circuit, 101... Frame detection circuit, 102... F
oS check circuit, 103...F engineering FO circuit, 104
...Frame transmission circuit, 106...Crystal oscillation circuit,
111...Shift register, 112...Aport pattern generation circuit, 114-118...Flip-flop, 121/122...Selector, 201...Receiver, 202...Driver, 203...NAND ;circuit.

Claims (1)

[Claims] (1) In a data transmission device that transfers pit sequence signal frames between multiple data transmission devices via a loop path, check the validity of incoming signal frames addressed to the own station and other stations. and when an abnormality 75 is detected by checking the validity of the frame, transmitting the frame in which the abnormality is detected to a data transmission device connected to a lower level than the local station on the loop-shaped transmission path. A data transmission device characterized by comprising: means for erasing the abnormality at a previous stage; and means for notifying a specific data transmission device connected to the loop-shaped transmission path of the abnormality every time the abnormality is detected.