JP2932359B2 - Fault notification circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a failure notification circuit, and more particularly to a failure notification method in a system in which a plurality of nodes are connected by an optical fiber interface to enable data transfer between main storage devices of each node.

[0002]

2. Description of the Related Art Conventionally, as a system of this kind, FIG.
As shown in (1), there is a type in which the transmitting node 5 and the receiving node 6 are connected by an optical fiber interface 200 to transfer data.

In this system, the transmitting node 5 includes a data register 50, a check bit generation circuit 51,
A transmission data register 52 and a transmission ECC (Error
(Checking and Correction) register 53, an encoding circuit 54, a parallel / serial conversion circuit 55, an electric / optical conversion circuit 56, and a transmission error register 57. Further, a failure processing device 7 is connected to the transmitting node 5, and a service processor device 8 is connected to the failure processing device 7 via a data line 231.

On the other hand, the receiving node 6 comprises an optical / electrical conversion circuit 60, a serial / parallel conversion circuit 61, a decoding circuit 62, a reception data register 63, a reception ECC register 64, a reception data buffer 65, ECC
Buffer 66, synchronous data register 67, synchronous EC
It comprises a C register 68, an error check circuit 69, a correction data register 70, and a reception error register 71.

[0005] An operating system 4 is connected to the receiving node 6, a fault handling device 3 is connected to the operating system 4 via a data line 234, and a fault handling device 3 is connected to the fault handling device 3 via a data line 233. And the service processor device 9 is connected. The service processor 9 is connected to the service processor 8 via a data line 232.

The transmitting node 5 and the receiving node 6
Since the data transfer width during the data transfer is 84 bytes and the optical fiber interface 200 is 1 byte wide for each,
The transmission side node 5 and the reception side node 6 are connected by four optical fibers.

The above-mentioned 84-byte data is transferred data 72
Byte and check bit 12 bytes,
Three bytes of check bits are allocated to 18 bytes of transfer data, and error checking is performed in units of 21 bytes. The check bit is such an E that enables one-byte error correction and two-byte error detection in 21-byte units.
It is generated using the CC code.

When the transmitting node 5 receives the transfer data of 18 bytes from the main storage device (not shown), the transfer data is stored in the data register 50. The data register 50 sends the transfer data to the transmission data register 52 via the data line 201 for storage, and sends the transfer data to the check bit generation circuit 51 via the data line 202.

The check bit generation circuit 51 generates a 3-byte check bit for the data sent from the data register 50 via the data line 202, and sends the check bit to the transmission ECC register 53 via the data line 203. Store.

The encoding circuit 54 converts the transmission data transmitted from the transmission data register 52 through the data line 204 and the check bits transmitted from the transmission ECC register 53 through the data line 205 into 8-bit data per byte. The data is converted into 10-bit data per byte and sent to the parallel / serial conversion circuit 55.

The parallel / serial conversion circuit 55 performs a process of converting parallel data in units of bytes into serial data in units of bits with respect to the data converted by the encoding circuit 54, and sends the data to an electric / optical conversion circuit 56.

The electrical / optical conversion circuit 56 performs a process of converting the data converted into serial data by the parallel / serial conversion circuit 55 from an electrical signal to an optical signal, and converts the data through the optical fiber interface 200 to the receiving side. Send to node 6. The transmission error register 57
Holds the fault information when a fault occurs in the transmitting node 5.

The optical / electrical conversion circuit 60 of the receiving node 6 performs a process of converting an optical signal into an electric signal with respect to the data received through the optical fiber interface 200, and sends the data to a serial / parallel conversion circuit 61. .

The serial / parallel conversion circuit 61 performs a process of converting serial data in units of bits into parallel data in units of bytes with respect to the data converted into an electric signal by the optical / electrical conversion circuit 60, and converts the parallel data. It is sent to the decoding circuit 62.

The decoding circuit 62 converts the data converted into parallel data by the serial / parallel conversion circuit 61 from 10-bit data per byte to 8-bit data per byte. The data is transmitted to and stored in the reception data register 63 via the data line 211, and the 3-byte data is transmitted to and stored in the reception ECC register 64 via the data line 212.

The reception data register 63 and the reception ECC register 64 transmit the data decoded by the decoding circuit 62 to the reception data buffer 65 and the reception ECC buffer 66 through the data lines 213 and 214, respectively.

The reception data buffer 65 and the reception ECC buffer 66 synchronize the data sent from the reception data register 63 and the reception ECC register 64 with each other between the 21 bytes of the received data, and transfer the data synchronously. Data and check bits are transferred to data lines 215 and 2
The data is transmitted to and stored in the synchronous data register 67 and the synchronous ECC register 68 through the respective sections 16.

The synchronous data register 67 and the synchronous ECC register 68 send the transfer data and check bits sent from the receive data buffer 65 and the receive ECC buffer 66 to the error check circuit 69 via the data lines 217 and 218, respectively.

The error check circuit 69 checks the transfer data and the check bit sent from the synchronous data register 67 and the synchronous ECC register 68 for garbled data, and removes the check bit if no error is detected. The 18-byte data is stored in the correction data register 70.

When the error check circuit 69 detects a one-byte error, the error check circuit 69 stores the error-corrected data in the corrected data register 70 based on the check bit. Further, when the error check circuit 69 detects an error of 2 bytes or more, it sets "1" in the reception error register 71.

In the system configured as described above, when a failure occurs in the transmitting node 5, “1” is set in the transmission error register 57, so that the transmitting node 5 performs optical communication using the optical fiber interface 200. Is interrupted, and the fault information held in the transmission error register 57 is transferred to the fault processing device 7 via the data line 206.
Notify.

The fault processing device 7 has a transmission error register 57.
Is notified of the occurrence of a failure, the service processor 8 sends the notification of the occurrence of the failure to the failure processor 3 via the service processor 9. Fault handling device 3
Notifies the operating system 4 of the notification of the occurrence of the failure.

[0023]

In the above-described conventional failure notification system, when a failure occurs in the transmitting node, the occurrence of the failure is determined by the failure processing device and service processor of the transmitting node and the service processor of the receiving node. Since the operating system is notified through the device and the fault handling device, the fault notification is passed to the operating system after passing between devices having a slow operation clock.

Therefore, it takes an enormous amount of time to pass the notification of the occurrence of the failure of the transmitting node to the operating system of the receiving node. There is a risk of being thrown.

Therefore, an object of the present invention is to solve the above-mentioned problems, to quickly notify a receiving node of the occurrence of a failure in a transmitting node, and to provide a new job to a failed device. It is an object of the present invention to provide a failure notification circuit that can prevent the input of a fault.

[0026]

A failure notification circuit according to the present invention is a failure notification circuit of an information processing system for performing data transfer between a transmission side node and a reception side node by optical communication, wherein the transmission side node is provided. And is set in advance as a transfer bit to the receiving node and a check bit for error correction / detection of the transferred data when a fault occurs in the own node so that an uncorrectable fault is detected in the receiving node. Transmission means for transmitting the predetermined pattern.

In another fault notifying circuit according to the present invention, in the above-mentioned configuration, the predetermined pattern is formed of the same value in which all values of each bit data are set in advance.

Another fault notifying circuit according to the present invention, in the above-mentioned configuration, is provided in said transmitting means, wherein said transmitting means generates a predetermined pattern, and said first means selects one of said predetermined pattern and said transfer data. Selection means, second selection means for selecting one of the predetermined pattern and the check bit, and control so that each of the first and second selection means selects the contents of the holding means when the fault occurs. Control means for performing the operation.

Still another fault notification circuit according to the present invention is:
In the above configuration, the control unit includes a holding unit that holds the information indicating the occurrence of the failure, and the selecting operation of each of the first and second selecting units is performed according to the held contents of the holding unit. Make up.

[0030]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First, the operation of the present invention will be described below.

When a failure occurs in the transmission side node, all "1" data set in advance so that an uncorrectable failure is detected in the reception side node is transmitted as transfer data to the reception side node and its check bit.

Thus, the error check circuit of the receiving node forcibly detects a failure by the same method as in the normal data transfer, and reports the occurrence of the failure from the error check circuit to the failure processing device via the reception error register. It is possible to do.

Since the transmitting node and the receiving node operate at 1/16 of the operation clock of the fault handling device,
Failure notification can be performed 16 times or more faster than the conventional failure notification method. For this reason, it is possible to prevent a new job from being input to a device that has failed due to a delay in failure notification.

Accordingly, it is possible to promptly notify the receiving node of the occurrence of a failure in the transmitting node,
It is possible to prevent a new job from being input to a device that is in trouble.

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of one embodiment of the present invention. In the figure, in a system according to an embodiment of the present invention, data transmission is performed by connecting a transmitting node 1 and a receiving node 2 by an optical fiber interface 100.

In this system, the transmitting node 1 includes a data register 10, a check bit generation circuit 11,
The transmission data selector 12 and a transmission ECC (Error
Checking and Correction) selector 13, transmission data register 14, transmission ECC
Register 15, encoding circuit 16, parallel / serial conversion circuit 17, electric / optical conversion circuit 18, transmission error register 19, all "1" data generation circuit 2
0.

On the other hand, the receiving node 2 includes an optical / electrical conversion circuit 21, a serial / parallel conversion circuit 22, a decoding circuit 23, a reception data register 24, a reception ECC register 25, a reception data buffer 26, ECC
Buffer 27, synchronous data register 28, synchronous EC
It comprises a C register 29, an error check circuit 30, a correction data register 31, and a reception error register 32.

An operating system 4 is connected to the receiving node 2, and a fault handling device 3 is connected to the operating system 4 via a data line 122.

The transmitting node 1 and the receiving node 2
Since the data transfer width during the data transfer is 84 bytes, and the optical fiber interface 100 is 1 byte wide per cable, the data transfer width is 8 bytes.
The transmission node 1 and the reception node 2 are connected by four optical fiber interfaces.

The above 84 byte data is the transfer data 72
Byte and check bit 12 bytes,
Three bytes of check bits are allocated to 18 bytes of transfer data, and error checking is performed in units of 21 bytes. The check bit is such an E that enables one-byte error correction and two-byte error detection in 21-byte units.
It is generated using the CC code.

When the transmitting node 1 receives the transfer data of 18 bytes from the main storage device (not shown), the transfer data is stored in the data register 10. The data register 10 sends the transfer data to the transmission data selector 12 via the data line 101, and sends the transfer data to the check bit generation circuit 11 via the data line 102.

The check bit generation circuit 11 generates a 3-byte check bit for the data sent from the data register 10 through the data line 102, and sends the check bit to the transmission ECC selector 13 through the data line 103.

The transmission data selector 12 transmits the transmission data sent from the data register 10 through the data line 101 and the transmission data selector 12 from the all-ones data generation circuit 20 to the data line 10.
9 is selected from the transmission error register 19 according to the failure information transmitted through the data line 108, and the selected data is transmitted to the transmission data register 14 through the data line 104. Send and store.

The transmission ECC selector 13 selects one of the check bits sent from the check bit generation circuit 11 through the data line 103 and the all “1” data sent from the all “1” data generation circuit 20 through the data line 109. One of them is selected according to the fault information sent from the transmission error register 19 through the data line 108,
The selected data is transmitted to the transmission ECC register 15 via the data line 105 and stored.

The encoding circuit 16 converts the data transmitted from the transmission data register 14 through the data line 106 and the check bits transmitted from the transmission ECC register 15 through the data line 107 into 8-bit data per byte. The parallel / serial conversion circuit 1 converts the data into 10-bit data per byte.
7

The parallel / serial converter 17 converts the data converted by the encoder 16 from parallel data in byte units to serial data in bit units, and sends the data to the electrical / optical converter circuit 18.

The electric / optical conversion circuit 18 performs a process of converting the data converted into serial data by the parallel / serial conversion circuit 17 from an electric signal to an optical signal, and converts the data through the optical fiber interface 100 to the receiving side. Send to node 2.

The transmission error register 19 stores the transmitting node 1
When a failure occurs in the data, the failure information is held, and the all "1" data generation circuit 20 generates all "1" data as transfer data and check bits.

The optical / electrical conversion circuit 21 of the receiving node 2 performs a process of converting an optical signal into an electric signal with respect to the data received through the optical fiber interface 100,
It is sent to the serial / parallel conversion circuit 22.

The serial / parallel conversion circuit 22 performs a process of converting serial data in units of bits into parallel data in units of bytes with respect to the data converted into an electric signal by the optical / electrical conversion circuit 21, and converts the parallel data. It is sent to the decoding circuit 23.

The decoding circuit 23 converts the data converted into parallel data by the serial / parallel conversion circuit 22 from 10-bit data per byte to 8-bit data per byte. The data is transmitted to the reception data register 24 via the data line 111 and stored, and the 3-byte data is transmitted to the reception ECC register 25 via the data line 112 and stored.

The reception data register 24 and the reception ECC register 25 transmit the data decoded by the decoding circuit 23 to the reception data buffer 26 and the reception ECC buffer 27 through the data lines 113 and 114, respectively.

The reception data buffer 26 and the reception ECC buffer 27 synchronize the data sent from the reception data register 24 and the reception ECC register 25 with each other between the bytes of the received data of 21 bytes, and transfer the data synchronously. Data and check bits are transferred to data lines 115, 1
The data is transmitted to and stored in the synchronous data register 28 and the synchronous ECC register 29 through the interface 16 respectively.

The synchronous data register 28 and the synchronous ECC register 29 transmit the data sent from the reception data buffer 26 and the reception ECC buffer 27 to the data line 11 respectively.
7 and 118 to the error check circuit 30.

The error check circuit 30 checks the data sent from the synchronous data register 28 and the synchronous ECC register 29 for garbled data, and if no error is detected, removes the check bit from the 18-byte data. Is stored in the correction data register 31.

When the error check circuit 30 detects a one-byte error, the error check circuit 30 stores data corrected based on the check bit in the correction data register 31. Further, when the error check circuit 30 detects an error of 2 bytes or more, it sets "1" in the reception error register 32. The error information (“1”) set in the reception error register 32 is output to the failure processing device 3 via the data line 121, and is notified from the failure processing device 3 to the operating system 4.

In the system configured as described above, when a failure occurs in the transmitting node 1, "1" is set in the transmission error register 19. Next, the transmitting node 1
When 18 bytes of data to be transferred are received, the 18 bytes of data are stored in the data register 10.

The 18-byte data stored in the data register 10 is sent to the check bit generation circuit 11 through the data line 102, and the check bit generation circuit 11 generates a 3-byte check bit based on the 18-byte data. .

However, in this case, the transmitting node 1
Since "1" is set in the transmission error register 19 due to the occurrence of a failure in the transmission error register 1,
From "9", "1" is transmitted to the data line 108.

The transmission data selector 12 is connected to the data line 108
Is transmitted, the all- "1" data from the all- "1" data generation circuit 20 is selected, and the transmission ECC is selected.
The selector 13 also selects all “1” data from the all “1” data generation circuit 20 by transmitting “1” to the data line 108.

All “1” data selected by the transmission data selector 12 and the transmission ECC selector 13 are sent to the transmission data register 14 and the transmission ECC register 15 via the data lines 104 and 105 and stored therein.

The transmission data register 14 has a data line 106
And the transmission ECC register 15 passes a 3-byte check bit to the encoding circuit 16 via the data line 107.

The encoding circuit 16 converts the data from the transmission data register 14 and the transmission ECC register 15 from parallel data of 8 bits per byte to parallel data of 10 bits per byte. Therefore, the transmission data register 14 and the transmission ECC
The 21-byte data from the register 15 becomes 210-bit parallel data.

The parallel data is converted into serial data by the parallel / serial conversion circuit 17 to use the optical fiber interface 100, and is converted into an optical signal by the electric / optical conversion circuit 18. The optical fiber interface 100 transfers 210-bit data to the receiving node 2 using 21 optical fibers.

The optical signal transferred to the receiving node 2 via the optical fiber interface 100 is converted into an electric signal by the optical / electrical conversion circuit 21 and is converted into parallel data by the serial / parallel conversion circuit 22.

The parallel data converted by the serial / parallel conversion circuit 22 is converted by the decoding circuit 23 from parallel data of 10 bits per byte to parallel data of 8 bits per byte. Here, the output data from the decoding circuit 23 becomes the same data as the input data of the encoding circuit 16 of the transmitting node 1.

The decode circuit 23 sends out 18 bytes of data to the reception data register 24 via the data line 111 and stores it, and sends out 3 bytes of check bits to the reception ECC register 25 via the data line 112. Store.

The reception data register 24 and the reception ECC register 25 transfer the stored data to the data lines 113 and 1 respectively.
The data is transmitted to and stored in the reception data buffer 26 and the reception ECC buffer 27 via the data buffer 14. Receive data buffer 2
6 and the reception ECC buffer 27 store data one after another in order to guarantee skew between the optical fiber interfaces 100.

The synchronous data register 28 and the synchronous ECC register 29 store the data which is read out from the reception data buffer 26 and the reception ECC buffer 27 via the data lines 115 and 116 and is synchronized with all 21 bytes, respectively. The resulting data is sent to the error check circuit 30 via the data lines 117 and 118.

The error check circuit 30 performs a 1-byte error correction / 2-byte error detection error check on the data from the synchronous data register 28 and the synchronous ECC register 29.

Normally, when the transfer data of 18 bytes is all "1", the check bit is "006666H".
However, when a failure occurs in the transmission-side node 1, all “1” data (“FFFFFFH”) is selected by the transmission ECC selector 13 as described above, so that the error check circuit 30 An error is detected, an uncorrectable error is determined, and “1” is set in the reception error register 32 via the data line 120.

When "1" is set in the reception error register 32, the data line 1
The failure occurrence is notified to the failure processing device 3 via the communication terminal 21.
When notified of the occurrence of a failure from the reception error register 32, the failure processing device 3 interrupts the operating system 4 via the data line 122 to notify that the failure has occurred. The operating system 4 stops issuing a new job to the node (sending node 1) that has received the failure notification.

As described above, when a failure occurs in the transmission-side node 1, all data which is set in advance so that an uncorrectable failure is detected in the reception-side node 2 as transfer data to the reception-side node 2 and its check bit. By transmitting 1 ”data, the error check circuit 30 of the receiving node 2 forcibly detects a failure in the same manner as in normal data transfer, and the error check circuit 30 detects the failure via the reception error register 32. It is possible to cause the processing device 3 to report the occurrence of a failure.

Since the transmitting node 1 and the receiving node 2 operate at 1/16 of the operation clock of the failure processing device 3, the failure notification is performed at least 16 times faster than the conventional failure notification method. be able to. For this reason, it is possible to prevent a new job from being input to a device that has failed due to a delay in failure notification.

Accordingly, the occurrence of a failure in the transmitting node 1 can be promptly notified to the receiving node 2 and the entry of a new job into the failed device can be prevented.

In implementing the fault notification circuit according to one embodiment of the present invention, a 168-bit two-way selector (transmission data selector 12 and transmission ECC selector 13) and an all "1" data generation circuit 20 are added. Therefore, the above effect can be obtained by adding a small amount of hardware.

The present invention can take the following aspects in connection with the description of the claims.

(1) A failure notification circuit of an information processing system in which a transmitting node and a receiving node are connected by an optical fiber interface to transfer data between their main storage devices by optical communication. An uncorrectable failure is detected in the receiving node as a transfer data provided to the receiving node and a check bit for error correction / detection of the transferred data when a failure occurs in the own node. A failure notification circuit for transmitting a predetermined pattern set in advance as described above.

(2) The failure notification circuit according to (1), wherein the predetermined pattern is such that all values of each bit data are set to the same value set in advance.

(3) The transmitting means includes: generating means for generating the predetermined pattern; first selecting means for selecting one of the predetermined pattern and the transfer data; And a control means for controlling each of the first and second selecting means to select the contents of the holding means when the failure occurs (the present invention). The fault notification circuit according to (1) or (2).

(4) The control means includes a holding means for holding the information indicating the occurrence of the failure, so that the selecting operation of each of the first and second selecting means is performed according to the contents held by the holding means. (3)
Fault notification circuit as described.

[0082]

As described above, according to the present invention, when a failure occurs in the transmitting node, an uncorrectable failure is detected in the receiving node as the transfer data to the receiving node and its check bit. By transmitting a predetermined pattern that has been set in advance, it is possible to promptly notify the receiving node of the occurrence of a failure in the transmitting node and to prevent a new job from being input to the failed device. There is an effect that can be.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Sending node 2 Receiving node 3 Fault handling device 4 Operating system 10 Data register 11 Check bit generation circuit 12 Transmission data selector 13 Transmission ECC selector 14 Transmission data register 15 Transmission ECC register 16 Encoding circuit 17 Parallel / serial conversion circuit 18 Electricity / Optical conversion circuit 19 transmission error register 20 all "1" data generation circuit 21 optical / electrical conversion circuit 22 serial / parallel conversion circuit 23 decoding circuit 24 reception data register 25 reception ECC register 26 reception data buffer 27 reception ECC buffer 28 synchronization data Register 29 Synchronous ECC register 30 Error check circuit 31 Correction data register 32 Receive error register

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H04L 1/12 H04L 29/14

Claims (4)

(57) [Claims] 1. A failure notification circuit of an information processing system for performing data transfer between a transmission side node and a reception side node by optical communication, the failure notification circuit being provided in the transmission side node and receiving the data when a failure occurs in its own node. Transmission means for transmitting a predetermined pattern which is set in advance so that an uncorrectable failure is detected in the reception side node as transfer data to the side node and check bits for error correction / detection of the transfer data. A fault notification circuit. 2. The failure notification circuit according to claim 1, wherein the predetermined pattern is such that all values of each bit data are set to the same value set in advance. 3. The transmitting means includes: generating means for generating the predetermined pattern; first selecting means for selecting one of the predetermined pattern and the transfer data; 2. The image processing apparatus according to claim 1, further comprising: a second selection unit that selects one of the first and second control units, and a control unit that controls the first and second selection units to select the contents of the holding unit when the failure occurs. The fault notification circuit according to claim 1 or claim 2. 4. The control means includes a holding means for holding the information indicating the occurrence of the failure, wherein the selecting operation of each of the first and second selecting means is performed according to the contents held by the holding means. The fault notification circuit according to claim 3, wherein