JPS60103590A - Refresh controller - Google Patents

Abstract

PURPOSE:To apply this controller to a high information processor having a high memory access frequency by providing the 3rd signal generating means generating a refresh operation end signal and a refresh address supply means supplied to a memory device. CONSTITUTION:A timing generating circuit 34 outputs a refresh start signal to a memory device by a refresh permission signal. Timing generating circuit 34 outputs a refresh operation end to an up-down counter 31 and a refresh address counter 33 when refresh is finished to the memory device. Then the refresh address counter 33 increments the count value by 1 to update the refresh address. On the other hand, the up-down counter 31 decrements 1 and the count value reaches ''0'', and a non-zero detection circuit detects ''0'', the timing generating circuit 34 makes a refresh request signal inactive by inactivating an output signal thereby avoiding refresh operation.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a dynamic memory refresh control device, and is particularly applicable to an information processing device in which dynamic memory is frequently accessed from a central processing unit or a direct memory access device (hereinafter abbreviated as DMAC). The present invention relates to a refresh control device.

A conventional control method of this type of refresh control device will be explained with reference to all the drawings.

FIG. g1 is a block diagram of a conventional dynamic memory glue controller. Fig. 1 NoriFlessy control device 1 includes a timer 11 that generates all pulses at regular intervals.
and timer 11. Count directly + by the pulse of t
Refresh address counter 12 and timer 1
1, and a timing generating circuit 13 that generates all refresh timing for the dynamic memory using pulses from 1.

For convenience of explanation, part of the control circuit of the memory device is also shown in FIG. The memory control circuit 14 arbitrates refresh requests from the refresh control device 1, read/write requests from the central processing unit or DMAC, outputs all response signals to the requests, and generates timing for the dynamic memory. . The multiplexer 15 separates and outputs all address information and refresh address information from the dynamic memory, central processing unit, or DMAC under the control of the memory control circuit 14.

A refresh control device l and a memory device configured like this? host system (central processing unit or D
The timing arrangement between the access from the MAC (MAC) and the refresh control device is shown in FIG. First, the timing diagram for accessing the memory device from the host system is shown in the second diagram.
Shown in Figures (a) and (b). First, a memory access request signal from the host system is input to the memory control circuit 14, and the host system also sends a memory address to the multiplexer 15 at the same time as the access request signal. In response to this, the memory control circuit W&1.4 outputs all memory access permission signals to the host system, and also outputs memory control signals (As/CAs) in response to read signals and write signals output from the host system. and all multiplexer control signals are output. On the other hand, the multiplexer 15 divides and outputs the upper and lower addresses from the host system to the memory in response to a control signal from the memory control circuit 14.

This completes accessing one word of data, but as shown in Figure 2 (tb), if all the memory is accessed again in succession, the @ will send the read and write signals again with all memory access request signals active. Seven consecutive accesses can be performed by outputting all the data. On the other hand, when the host system accesses in units of 1 word, as shown in FIG. access can be achieved.

Next, the timing diagram when performing 1 refresh from the refresh control device 1 to the memory device is shown in Fig. 2 (C).
Shown below. First, the refresh control device 1 increments the refresh address counter 12 by 1 using a pulse output from the timer 11, and outputs a refresh request signal to the timing generation circuit 13f/(thus, the entire memory control circuit 14).

When there is no other access request, the memory control circuit 14 outputs a refresh permission signal from the timing generation circuit 13 and outputs the refresh address output from the refresh address counter 12 through the multiplexer 15.

The timing generation circuit 13 generates a refresh start signal sound memory control circuit 14 in response to the supply of the refresh permission signal.
Supply and memory system? In response, the i11 circuit 14 outputs a memory fresh control signal (RAS) to the memory element as a full refresh timing.

As described above, there are two types of memory processing: access by the host system and refresh, and refresh is, of course, an indispensable process for dynamic memory. Therefore, if the above-mentioned access and refresh processing occur simultaneously or (c) when refresh occurs during continuous memory access by the host system, it is necessary to give priority to the refresh processing. Even if refreshing is delayed, it must be done within the pulse interval time of the timer 11. If the waiting time exceeds the pulse interval, the address to be refreshed will be changed by +1 by the pulse of the refresh address counter 12U timer 11. Therefore, the refresh address skipped due to this phenomenon will be A certain memory element cannot be refreshed until all the memory elements have been refreshed, and the refresh time required by the memory element is no longer satisfied, and the contents of the data stored in the memory are It will no longer be guaranteed.

Therefore, the memory control device 1 must either give refresh requests a higher priority than memory access requests from the host system, or make continuous memory accesses from the host system shorter than the time interval of the timer 11.

However, with this more advanced configuration, @ keeps the transfer rate constant for continuous data transfer from the host side, especially the disk and communication line, and keeps the memory for a certain period of time (usually a number of times longer than the time interval of timer 11). Continuous access! System #/c cannot be used.

As described above, it is necessary for the conventional NoriFreshi Kansoyo to output a refresh request sound at fixed time intervals, and to perform the refresh process before the next refresh request occurs. Therefore, it has the disadvantage that it cannot be applied to systems that perform high-speed data transfer and require continuous memory access.

An object of the present invention is to maintain dynamic memory even if the memory device is exclusively occupied by the host system for a certain period of time. It is an object of the present invention to provide a leaf-renometry system which can be applied to an information processing device that performs all 4-add refresh services and frequently accesses memory.

The device of the present invention includes a first signal generating means that generates a first refresh request signal sound for requesting refresh/full at regular intervals, and a refresh operation that counts up in response to the supply of the first refresh request signal. a counting means for counting down in response to supply of an end signal; a second signal generating means for generating a second refresh request signal when the first count of the counting means is other than 0; and a refresh request from the second offender. a third refresh request signal is supplied to all the memory devices in response to the supply of the refresh request signal, and a refresh start signal is supplied to all the memory devices in response to the supply of the refresh enable signal from the memory device; third signal generating means for generating the refresh operation end signal in response to the refresh operation end signal; and a refresh address? in response to the supply of the refresh operation end signal. and fresh address supply means for updating and supplying the fresh address to the memory device.

Next, the refresh control device of the present invention will be explained in detail with reference to the drawings.

FIG. 3 is a block diagram showing an embodiment of the refresh control device of the present invention. The refresh control device shown in FIG. 3 includes a timer 30 that generates a pulse (first refresh request signal) at fixed time intervals.

The up-1-down counter 31 counts +1 by the pulse output from the timer 30 and counts by 1 by the refresh operation end signal from each timer generation source 34, and when the up-down counter 31 is not *O++, the active signal (second -4- by the non-zero detection circuit 32 which outputs all the refresh request signal) and the refresh operation end signal from the timing generation circuit 33.
Refresh address counter 3 increases by 1 count
3, a timing generation circuit 34 that requests the memory device 1 or the central processing unit to insert a refresh cycle, and generates a timing signal such as a necessary refresh request signal (third signal 7 request signal) necessary for refreshing. It consists of

The timing of refresh in the control device (refresh) 51 with such a configuration will now be explained.

Timer 3 (1: Pulses occur at fixed time intervals.

The up/down counter 31 is counted up.

When the initial i'th of the up-down counter 31 is 0'', the count value becomes 1'' due to this pulse, and the non-zero detection circuit 32 detects that the up-down counter 31 is not OL' and activates the output signal sound. In response to this output signal, the timing generation circuit 34 outputs an I-fresh request signal to the memory device or central processing unit.

At this time, if the memory device or central processing unit does not use all the paths, the memory device outputs a refresh permission signal to the full timing generation circuit 34 and adopts the refresh address supplied from the refresh address counter 33. The timing generation circuit 34 outputs a refresh start signal to the gold memory device according to this refresh permission signal. When the memory device is refreshed, the timing generation circuit 34
outputs a refresh operation end signal to the up/down counter 31 and refresh address counter 33.

At this time, the refresh address counter 33 increments the count value by 1 and updates all refresh addresses. On the other hand, the Akugudown counter 31 counts -l and counts 6.
(L is O'l, and the non-zero detection circuit is 'O'ff
By detecting i and making the output signal tone inactive, the timing generation circuit 34 makes the refresh request signal 2 inactive and does not perform any refresh operation.

Next, we will explain the case where the memory device is monopolized by the central processing unit, DMAC, etc., and the refresh a' [enabled signal is not returned within the pulse interval of the timer 30 in response to the refresh request signal from the timing generation circuit 34. do. Due to the pulse from the timer 30, the up/down counter 3171) becomes Kl'1'', and the non-zero circuit detects that the up/down counter 31 is not *0+1, and the timing generation circuit 34 outputs all active signals. -f, the timing generation circuit 34 outputs a refresh request signal to the memory device or central processing unit as described above.
If the refresh W signal is not given within the interval between the pulses of the timer 30, the up/down counter 3111''2' is set by the pulse of the timer 3o. if,
When the refresh request is not permitted even if the timer 3o outputs several pulses, the count value of the up/down counter 31 increases to 113Z14''.

Here, to simplify the explanation, it is assumed that the refresh request is permitted when the count value f)E''2I' of the up/down counter 31.The timing generation circuit 34 uses the refresh address from the refresh address counter 33 in response to the refresh permission signal. and outputs the refresh timing required for the memory device.When refreshing is completed for the memory device, the timing generation circuit 34 outputs a full refresh operation completion signal to the refresh address counter 33 and up/down counter 31. , at this time, refresh address counter 3
3 updates the count value +1L and all refresher addresses. On the other hand, the deep down counter 31 counts -1t'', and the count value becomes +1111.At this time, the non-zero detection circuit cannot detect gold as ``0'', so the output signal tone continues to be activated.This output signal The timing generation circuit 34 continues to generate a refresh request warning sound.If the refresh permission signal is still being output at this time, the refresh operation continues, and if the refresh permission signal is inactive, the refresh operation is started as soon as the refresh permission signal is output. Do everything.

Upon completion of this refresh operation, the timing generation circuit 34 outputs a refresh operation end signal sound, the refresh address counter 33 and the up/down counter 31.
Vc output.

At this time, the refresh address counter 33 updates its count value completely to prepare for the next refresh request. On the other hand, the up-down counter 31 counts 11 and sets the count to "0". The non-zero detection circuit 32 (hairturn down counter 317) detects all the data being "0" and makes the output signal sound inactive. This output signal is input to the timing generation circuit 34, and the timing generation circuit 34 refreshes. Make the request signal inactive.

The example above shows that the refresh permission signal is output when the count value is l121+, but also when the count value is ``2'' or more. It is clear that even if the count value of the up/down counter 31 is further incremented by 1 due to the output of the timer 30 during the refresh operation, the above-described operation is performed.

In the present invention, as described above, the output from the timer 3o is counted up by an up/down counter, and the timer 3o is
Even if the timing generation circuit 34 is unable to execute all refresh services within a pulse interval of 0, it records the number of times the refresh service request 7 could not be executed in response to a request from the timer 30, and determines whether the refresh service is to be executed. When granted, the refresh service indicated by the count value of the upgrade counter 310 can be executed in bulk, especially in systems that require data transfer or memory access that requires exclusive use of memory for a certain period of time. This has the effect of being applicable to systems with high performance.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conventional refresh control device, FIG. 2 (ta) is an access timing diagram for l word units, WJZ diagram (tb) is an access timing diagram for 3 consecutive words, FIG. 2 (C) i, t The refresh timing diagram and FIG. 3 are block diagrams showing one embodiment of the present invention. l... Refresh control device, 11...
・Timer, 12... Refresh address counter, 13... Timing generation circuit, 14...
...Memory control circuit, 15...Multiplexer, 30...Timer, 31...Up-down counter, 32...Non-zero detection circuit, 33...Refresh address counter, 3
4... Timing generation circuit. gu ['lp3

Claims (1)

[Scope of Claims] First signal generating means for generating a first refresh request signal for requesting full refresh at regular intervals. a counting means that counts up in response to the supply of the first refresh request signal and counts down in response to the supply of the refresh 1i17 operation end signal; If the count value of the counting means is other than 0, @VCiff 2
and second signal generating means for generating all refresh request signals. In response to the supply of the second refresh request signal, WJ
3, a refresh request signal tone is supplied to the memory device, and in response, a refresh enable signal is supplied from the memory device (in response, a refresh start signal tone is supplied to the memory device, and in response to the end of refresh, the refresh request signal is supplied to the memory device, and in response to the refresh end, the refresh permission signal is supplied from the memory device)
A signal generating means for the spool 3 that generates an operation end signal. In response to the supply of the above-mentioned 7-receipt operation end signal, the refresh address money is updated and supplied to the memory device.
All features include a receipt address supply means and a V-touch control device.