JP3618249B2 - Data transfer device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a data transfer apparatus that transfers a plurality of types of data.
[0002]
[Prior art]
In recent years, an MPEG decoding apparatus or the like has a large amount of data to be processed and a large number of types of data, and a large-capacity memory is required as data processing becomes complicated. As such a large-capacity memory, DRAM, SDRAM, RAMBUS-DRAM, or the like is used when used for consumer electronic devices. These memories are characterized in that data transfer efficiency with respect to these memories is improved when data is successively accessed with respect to consecutive addresses, rather than with random access. However, in MPEG decoding processing, the transfer rate of compressed data, the output of video signals, the output of audio signals, and the like have the property of being slower in time than the memory access rate. Therefore, when a large amount of compressed data, video data, audio data, etc. are accessed at a low speed with respect to the memory such as the DRAM, the memory transfer efficiency to the memory such as the DRAM is remarkably lowered. For this reason, conventionally, a buffer memory for temporarily storing a large amount of compressed data, video data, audio data, etc. is provided. If a certain amount of data is stored in these buffer memories, the data is continuously stored. In addition, the memory transfer efficiency is increased by transferring the data to a memory such as a DRAM at high speed.
[0003]
However, since the conventional data transfer device has a buffer memory for each type of data such as the large amount of compressed data, video data, and audio data, the number of buffer memories to be used increases as the types of data to be handled increase At the same time, it is necessary to provide a data transfer bus for each type of data, which increases the wiring area of the bus, resulting in a disadvantage that the circuit area becomes large.
[0004]
Therefore, conventionally, a data transfer apparatus is known in which one buffer memory is shared among a plurality of types of asynchronous data. This transfer device is provided with a plurality of data input / output circuits for inputting / outputting a plurality of types of data according to the types, assigning an access priority to the shared buffer memory to these input / output circuits, and an input / output having a high access priority. The shared buffer memory is configured to be accessible in order from the circuit, and a second buffer memory is provided for each data input / output circuit, and data is input between any of the input / output circuits and the shared buffer memory. A configuration is adopted in which other data is stored in the corresponding second buffer memory during output.
[0005]
[Problems to be solved by the invention]
However, in this data transfer apparatus, in the data input / output circuit having a low access priority, access to the shared buffer memory is not performed within a desired time, and access within the desired time is not guaranteed. Specifically, in the data input / output circuit with the highest access priority, access is permitted for each access request and access within a desired time is guaranteed, but in the data input / output circuit with a low access priority, When the access request conflicts with an access request of an input / output circuit having a high access priority, the access request is not permitted, and access within a desired time is not guaranteed. As a result, in the input / output circuit having a low access priority, it is necessary to use a memory having a larger capacity than necessary as the second buffer memory.
[0006]
On the other hand, with regard to access priority, there is a technique disclosed in US Pat. No. 5,533,205. This technique is used to divide the bus into a series of time frames, subdivide each time frame into smaller time intervals and indicate the priority of bus access during the selected time interval. The order of the arbitration level indicators to be changed is temporarily changed in relation to a specific presentation device so as to guarantee bus access at a data transfer rate required for each data input / output circuit. However, in this technique, the priority order of bus access is changed every minute time interval, so that the configuration necessary for the change becomes complicated.
[0007]
SUMMARY OF THE INVENTION An object of the present invention is to provide a data transfer that guarantees that a plurality of types of data can be transferred within a desired period with a simple configuration while sharing a single buffer memory among a plurality of data input / output circuits. To provide an apparatus.
[0008]
[Means for Solving the Problems]
In order to achieve the above object, in the present invention, a memory access priority and a memory access request issue interval are assigned to each data input / output circuit.
[0009]
In other words, the data transfer apparatus of the present invention according to claim 1 is shared by a plurality of data input / output means for inputting or outputting data, and the plurality of data input / output means. Memory means as a buffer memory for inputting / outputting data between them, and arbitrating means for arbitrating access requests from the plurality of data input / output means to the memory means, wherein each data input / output means is connected to the memory means. Access priorities are assigned in advance, and access requests to the memory means can be issued at predetermined time intervals. The arbitration means receives access requests from the plurality of data input / output means, and receives the plurality of data inputs. Before arbitrating the access request from the output means for each unit access cycle of the memory means, For a plurality of data output means, allow memory access in descending order of the access priorityEach of the plurality of data input / output means can access the memory means only for a time equal to the unit access cycle time of the memory means when memory access is permitted by the arbitration means.It is characterized by that.
[0010]
According to a second aspect of the present invention, in the data transfer apparatus according to the first aspect, the arbitration unit is a data input / output unit having the highest access priority among the data input / output units that have received an access request. The data input / output unit issues an access request again regardless of the predetermined time interval when the access request is not permitted by the arbitration unit.
[0011]
In addition, according to a third aspect of the present invention, in the data transfer apparatus according to the first or second aspect, each of the data input / output means includes: an input means for inputting data; an access request interval for the memory means; An input data storage unit having a capacity for storing at least the amount of data input to the input unit during a total period from the issuance of the access request until the access request is permitted And
[0012]
In addition, according to a fourth aspect of the present invention, in the data transfer apparatus according to the first or second aspect, each of the data input / output means includes: an output means for outputting data; an access request interval for the memory means; An output data storage unit having a capacity for storing at least the amount of data output from the output unit during a total period from the issuance of the access request until the access request is permitted And
[0013]
With the above configuration, according to the first to fourth aspects of the present invention, when one memory means is shared by a plurality of data input / output means, a memory access priority and an access request for each data input / output means. And the access request time interval to the memory means of each data input / output means is set to a predetermined interval, so that the access to the memory means of each data input / output means can be reliably performed within a desired time. Is called. Accordingly, the capacity of the second buffer memory (input data storage means or output data storage means) provided in each data input / output means can be clearly grasped in advance, and these capacities can be reduced as compared with the prior art.
[0014]
In particular, since arbitration of access requests from each data input / output unit is performed for each unit access cycle of the memory unit, the capacity of the second buffer memory provided in each data input / output unit can be reduced to the minimum necessary capacity.
[0015]
In the inventions according to claim 3 and claim 4, the data storage capacity of each data input / output unit is input / output during a total period of an access request interval for the memory unit and a period from the issuance of access requests to permission. The amount of data to be determined is clearly determined at least in the capacity for storing.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
[0017]
In the present embodiment, a case where two data streams are transferred in real time will be described as an example, and MPEG audio data decoding output processing and MPEG video data decoding output processing are performed as two processes. Illustrate.
[0018]
FIG. 1 shows a block diagram of a data transfer apparatus according to an embodiment of the present invention. In the figure, a memory means (buffer memory) 10 has a function of storing data. Specifically, it is an SRAM having a minimum access cycle of 20 nanoseconds and a storage capacity of 4 KB. This memory means 10 inputs and outputs data to and from other memory means 6 composed of SDRAM arranged outside one chip surrounded by a broken line in the figure.
[0019]
The first data input / output unit 1 outputs video data, is assigned the highest level “0” as the memory access priority for the memory unit 10, and sends the memory access request signal 20 to the arbitration unit 30 for two cycles. It can be issued with the above interval. Here, it is assumed that the memory access priority is higher as the numerical value is smaller. FIG. 2 shows a block diagram of the first data input / output means 1. In the first data input / output unit 1 of FIG. 2, the output data storage unit 50 stores the data read from the memory unit 10. The data access control means 51 manages the effective data amount of the output data storage means 50 and issues a memory access request signal 20 to the arbitration means 30. The output means 52 has a function of outputting the data from the output data storage means 50 to the CRT, and specifically comprises a video D / A converter.
[0020]
In FIG. 1, the second data input / output means 2 outputs audio data, is assigned a level “1” as a memory access priority for the memory means 10, and sends a memory access request signal 21 to the arbitration means 30. Issued at intervals of 4 cycles or more. However, if the access is not permitted due to arbitration, the memory access request signal 21 is continuously issued. FIG. 3 shows a block diagram of the second data input / output means 2. In the second data input / output means 2 of FIG. 3, the output data storage means 60 stores the data read from the memory means 10. The data access control means 61 manages the effective data amount of the output data storage means 60 and issues a memory access request signal 21 to the arbitration means 30. The output means 62 has a function of outputting the data of the output data storage means 60 to the speaker, and specifically comprises an audio D / A converter or an IEC956 standard data format conversion output circuit.
[0021]
In FIG. 1, the third data input / output means 3 writes the decoded video data in the memory means 10 in order to output the video data on which the MPEG encoded video data has been decoded. The third data input / output means 3 is assigned the level “2” as the memory access priority order, and can issue the memory access request signal 22 to the arbitration means 30 with an interval of 8 cycles or more. However, if access is not permitted due to arbitration, the memory access request signal 22 is issued continuously. FIG. 4 shows a block diagram of the data input / output means 3. In the third data input / output means 2 shown in FIG. 4, the input means 72 inputs data processed by the MPEG video decoding apparatus. The input data storage means 70 stores the input data to be written to the memory means 10. The data access control means 71 manages the effective data amount of the input data storage means 70 and issues a memory access request signal 22 to the arbitration means 30.
[0022]
The third data input / output means 3 inputs the data subjected to the decoding process of the MPEG encoded video data to the third input means 72, and then inputs the third input data storage means from the input means 72. Write to 70. The third data access control means 71 checks the third input data storage means 70, and there is valid data that can be written to the memory means 10, and the current memory access is issued after issuing the previous memory access request. If the interval until the request is issued is equal to or longer than the access request interval assigned to the third data input / output unit 3, a memory access request is issued to the arbitrating unit 30. When the arbitrating unit 30 permits the third data input / output unit 3 to access the memory, the third data access control unit 71 outputs the data of the third input data storage unit 70 to the input bus 12.
[0023]
Further, in FIG. 1, the fourth data input / output means 4 writes the decoded audio data to the memory means 10 in order to output the audio data on which the MPEG encoded audio data has been decoded. The fourth data input / output unit 4 is assigned level “3” as the memory access priority order, and can issue the memory access request signal 23 to the arbitration unit 30 with an interval of 8 cycles or more. However, if access is not permitted due to arbitration, the memory access request signal 23 is continuously issued. FIG. 5 shows a block diagram of the fourth data input / output means 4. In the data input / output means 4 shown in the figure, an input means 82 inputs data processed by the MPEG audio decoding apparatus. The input data storage means 80 stores the inputted data to be written to the memory means 10. The data access control means 81 manages the effective data amount of the input data storage means 80 and issues a memory access request signal 23 to the arbitration means 30.
[0024]
In FIG. 1, an output bus 11 is a bus for transferring data read from the memory means 10 to the first to fourth data input / output means 1-4. The input bus 12 is a bus for transferring the data output from the third and fourth data input / output means 3 and 4 for writing to the memory means 10.
[0025]
The arbitrating unit 30 examines the data access request signals 20 to 23 and, for each minimum access cycle unit (20 nanoseconds) of the memory unit 10 based on the memory access priority assigned to each data input / output unit 1 to 4. The memory access arbitration for the memory means 10 is performed.
[0026]
The access information storage means 31 is access information that each data input / output means 1 to 4 accesses to the memory means 10 (shows address information and write / read operations for the memory means 10 of the plurality of data input / output means 1 to 4 (Including read / write information), and issues access information of the data input / output means to which the memory access permission is given by the arbitration result of the arbitration means 30 to the memory means 10, and then accesses for the next memory access Update information.
[0027]
FIG. 6 shows a block diagram of the access information storage means 31. In the figure, first to fourth access information storage units 90 to 120 store access information of first to fourth data input / output means 1 to 4, respectively.
[0028]
The first, second, third and fourth memory pointer information 91, 101, 111, 121 are written to or read from the memory means 10 by the first to fourth data input / output means 1 to 4, respectively. The address value (address information) to be performed is stored. The first, second, third, and fourth upper limit memory pointer information 92, 102, 112, and 122 are the maximum pointer values (upper limit addresses) that can be taken by the first to fourth memory pointer information 91 to 121, respectively. It is. The first, second, third, and fourth lower limit memory pointer information 93, 103, 113, and 123 are the minimum pointer values (initial values) that the first to fourth memory pointer information 91 to 121 can take. Address). Further, the first, second, third, and fourth read / write information 94, 104, 114, and 124 indicate that each of the data input / output means 1 to 4 performs read access or write access to the memory means 10. Is control information indicating whether or not to perform.
[0029]
The access information control unit 130 updates and controls the memory pointer information managed by the access information storage units 90 to 120, and outputs access information for the data input / output unit adjusted by the arbitration unit 30 to the memory control unit 32.
[0030]
In FIG. 1, the memory control unit 32 generates address information issued by the access information storage unit 31 and a read / write control signal necessary for performing data access to the memory unit 10.
[0031]
FIG. 7 is an operation timing chart of the memory control means 32. In the figure, in step 1, the arbitrating means 30 examines the memory access requests 20 to 23 issued by all the data input / output means 1 to 4, and the data input / output means 1 Access to the data input / output means having the highest priority among the memory access requests issued from 4 is permitted.
[0032]
In step 2, if the data input / output means given the memory access permission by the arbitrating means 30 outputs (writes) data to the memory means 10, the data written in the memory means 10 is output to the input bus 12. To do.
[0033]
In step 3, the access information storage unit 31 outputs access information corresponding to the data input / output unit arbitrated in step 1. The memory control unit 32 outputs address information and a read / write control signal for performing memory access to the memory unit 10 based on the access information output from the access information storage unit 31. The access information control unit 130 updates the memory pointer information of the data input / output means for which memory access is permitted in Step 1 for the next data access.
[0034]
In step 4, if the memory access in step 3 is read, the memory control means 32 outputs the data read from the memory means 10 to the output bus 11.
[0035]
The processes in steps 1 to 4 are sequentially executed for each unit memory access cycle of the memory means 10 and the processes in steps 1 to 4 operate in parallel. Therefore, the same or different data input is performed for each unit memory access cycle. Mediates data from output means,As can be seen from the first to fourth processes in FIG. 7, each of the plurality of data input / output means 1 to 4 grants memory access permission by the arbitration means 30 in the “access arbitration” of the unit memory access cycle in step 1. When given, in any case, regardless of the priority order, in the “memory access” in step 3 two cycles after the unit memory access cycle in which the access arbitration is performed, the time is equal to the unit memory access cycle time. Only the memory means 10 can be accessed. When the unit memory access time of this “memory access” ends, the memory access operation always ends, and the “output data output” operation which is the next unit memory access cycle Migrate to
[0036]
The arbitration unit 30 performs arbitration for each unit memory access cycle. In this embodiment, when the data input / output units 1 to 4 have issued data access requests, the first data input / output with the highest priority is performed. Data access is permitted to the means 1. FIG. 8 is a timing chart of memory arbitration in the present embodiment. The maximum period (time) required from when the first to fourth data input / output means 1 to 4 issue a memory access request until receiving the memory access permission will be described with reference to FIG. As described above, the memory access priority for the memory means 10 is as follows: first data input / output means 1> second data input / output means 2> third data input / output means 3> fourth data input / output means 4 The issuance intervals of access requests to the shared memory means 10 of the first to fourth data input / output means 1 to 4 are 2 cycles, 4 cycles, 8 cycles, and 8 cycles, respectively.
[0037]
In the figure, each cycle from cycle A to cycle H represents a unit memory access cycle.
[0038]
First, in the cycle A, the arbitration unit 30 is the first data input / output unit having the highest priority since the first to fourth data input / output units 1 to 4 each issue a memory access request. 1 issues memory access permission.
[0039]
In cycle B, the second to fourth data input / output means 2 to 4 that could not perform memory access in cycle A continue to issue memory access requests, and the arbitration means 30 receives the data input that received the access request. A memory access permission is issued to the second data input / output means 2 having the highest memory access priority among the output means 2 to 4.
[0040]
In cycle C, the first data input / output unit 1 issues a memory access request once every two cycles, so the arbitration unit 30 issues a memory access permission to the first data input / output unit 1.
[0041]
In cycle D, the third and fourth data input / output means 3 and 4 that were not able to access the memory in cycle C continue to issue memory access requests, and the arbitration means 30 receives the access request data A memory access permission is issued to the third data input / output means 3 having the highest memory access priority among the input / output means 3 and 4.
[0042]
In cycle E, in cycle C, the first data input / output means 1, the second data input / output means 2, and the fourth data input / output means 4 issue a memory access request, and the arbitration means 30 The memory access permission is issued to the first data input / output means 1 having the highest memory access priority among the data input / output means 1, 2, 4 received.
[0043]
Arbitration means 30 performs memory access arbitration in the same manner, and gives data access permission to fourth data input / output means 4 in cycle H.
[0044]
Therefore, the first data input / output unit 1 can receive the data access permission after one cycle including the cycle in which the data access request is issued. Similarly, the second data input / output means 2, the third data input / output means 3, and the fourth data input / output means 4 each include a cycle in which a data access request is issued, and after two cycles and four cycles later. The data access permission can be received after 8 cycles. Each data input / output means 1 to 4 inputs or outputs data corresponding to the data storage capacity of the built-in data storage means 50 to 80 with the shared memory means 10 in a cycle in which access permission is received.
[0045]
As can be seen from the above description, the access request intervals of the first to fourth data input / output means 1 to 4 are 2, 4, 8, and 8 cycles, respectively. Are actually 1, 2, 4, and 8 cycles, and it is guaranteed that all the input / output means are accessed within the access request interval.
[0046]
Next, the data storage capacity of the data storage means 50-80 built in each data input / output means 1-4 will be described. In the fourth data input / output means 4, the access request interval is 8 cycles, and the period from when the access request is issued until this request is granted is 7 cycles as can be seen from FIG. Accordingly, the data input / output units 1 to 3 having higher priority than the data input / output unit 4 of the self do not issue the access request this time, and considering the worst case of issuing the next time, the fourth data input / output unit is considered. The capacity of the input data storage means 80 of the means 4 is the total period (15 cycles) of the access request interval (8 cycles) and the period until the request is granted after the access request is issued (7 cycles). Meanwhile, the amount of data received from the input means 82 is set to at least a capacity that can be stored.
[0047]
Similarly, the capacity of the input data storage means 70 of the third data input / output means 3 is the access request interval (8 cycles) and the period after the access request is issued until this request is granted (3 cycles). During the total period (11 cycles), the amount of data received from the input means 72 is set to at least a storable capacity.
[0048]
Further, the capacity of the output data storage means 60 of the second data input / output means 2 includes an access request interval (4 cycles), a period from when an access request is issued until this request is permitted (1 cycle). During the total period (5 cycles), the amount of data to be output to the output means 62 is set to at least a storable capacity.
[0049]
Further, the capacity of the output data storage means 50 of the first data input / output means 1 includes an access request interval (2 cycles), a period from when an access request is issued until this request is permitted (0 cycle). During the total period (2 cycles), the amount of data to be output to the output means 52 is set to at least a storable capacity.
[0050]
Conventionally, a memory access interval (a period from an access request to an actual access) is not defined for each of the data input / output units 1 to 4. Accordingly, the data input / output means (for example, the fourth data input / output means 4) having a low memory access priority cannot assume the waiting time as one predetermined time for memory access, and the input data The capacity of the storage unit 80 cannot be specified. As a result, it becomes difficult to transfer data in real time.
[0051]
On the other hand, according to the present embodiment, a plurality of data input / output means 1 to 4 use a common memory means 10, and each data input / output means 1 to 4 is connected to the shared memory means 10. An access priority and a memory access request issuance interval are allocated, and the arbitration unit 30 arbitrates the memory access request based on the access priority for each unit access cycle of the memory unit 10, whereby each data input / output unit 1-1. Since the capacity of the four output data storage means 50, 60 and the input data storage means 70, 80 can be specified as the predetermined capacity, data transfer in real time is possible.
[0052]
In the present embodiment, each of the first to fourth data input / output means 1 to 4 continuously outputs the memory access request signals 20 to 23 when the memory access request is not permitted. However, the present invention is not limited to this. For example, each of the data input / output units 1 to 4 outputs the memory access request signals 20 to 23 only at a predetermined time interval, and the arbitration unit 30 simultaneously outputs two or more data inputs / outputs. When a memory access request signal is received from each of the means, access is permitted to the data output means having the highest memory access priority, and in the next cycle, to the data input / output means having the next highest access priority. You may employ | adopt the structure which repeats permitting access for every cycle.
[0053]
Further, when the access request is arbitrated every unit access cycle as in the present embodiment, the capacity of the output data storage means 50, 60 and the input data storage means 70, 80 is set to the minimum necessary capacity. There is an effect that can be reduced.
[0054]
Further, in the present embodiment, the number of data input / output means for accessing data to the memory means 10 is "4". However, the operation and effect of this embodiment are basically the same even if the number is larger. Will not change.
[0055]
In addition, in the present embodiment, the first data input / output means 1, the second data input / output means 2, the third data input / output means 3, and the fourth data input / output means 4 are connected to output video, audio. Output processing, MPEG video decoding processing, and audio decoding processing are performed. However, as long as data is input / output to / from the memory means 10, the processing contents and data contents are not limited at all.
[0056]
【The invention's effect】
As described above, according to the data transfer apparatus of the first to fourth aspects of the present invention, when the memory means is shared by a plurality of data input / output means, each data input / output means accesses the shared memory means. Since the request time interval is set to a predetermined interval, it can be ensured that the access to the shared memory means of each data input / output means is reliably performed within a desired time. The capacity of the buffer memory can be clearly grasped in advance, and these capacities can be reduced as compared with the prior art.
[0057]
Particularly, since the arbitration of the access request from each data input / output means is performed for each unit access cycle of the memory means, the capacity of the second buffer memory provided in each data input / output means can be reduced to the minimum necessary capacity.
[0058]
According to the third and fourth aspects of the present invention, the data storage capacity of each data input / output means is set between the access request interval for the memory means and the period from the issuance of access requests to permission. The amount of data to be input / output can be clearly determined as at least the storage capacity.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a data transfer apparatus according to an embodiment of the present invention.
FIG. 2 is a block diagram showing first data input / output means according to the same embodiment;
FIG. 3 is a block diagram showing second data input / output means according to the embodiment;
FIG. 4 is a block diagram showing third data input / output means according to the embodiment;
FIG. 5 is a block diagram showing fourth data input / output means according to the embodiment;
FIG. 6 is a block diagram showing access information storage means according to the embodiment;
FIG. 7 is a timing diagram of memory access according to the embodiment;
FIG. 8 is a timing diagram of memory arbitration according to the embodiment;
[Explanation of symbols]
1-4 Data input / output means
10 Memory means
11 Output bus
12 Input bus
20-23 Memory access request signal
30 Mediation means
31 Access information storage means
32 Memory control means

Claims (4)

A plurality of data input / output means for inputting or outputting data;
Memory means that is shared by the plurality of data input / output means and inputs / outputs data to / from the plurality of data input / output means;
Arbitrating means for arbitrating access requests to the memory means from the plurality of data input / output means;
Each of the data input / output means is pre-assigned a priority of access to the memory means, and can issue an access request to the memory means at a predetermined time interval.
The arbitration unit receives access requests from the plurality of data input / output units, arbitrates access requests from the plurality of data input / output units for each unit access cycle of the memory unit, and receives the access requests. In addition, for the plurality of data input / output means, memory access is permitted in descending order of the access priority ,
Each of the plurality of data input / output means can access the memory means only for a time equal to a unit access cycle time of the memory means when memory access is permitted by the arbitration means. A data transfer device. The arbitration means permits access to the data input / output means having the highest access priority among the data input / output means that have received the access request,
2. The data transfer apparatus according to claim 1, wherein each data input / output unit issues an access request again regardless of the predetermined time interval when the access request is not permitted by the arbitration unit. Each of the data input / output means is
An input means for inputting data;
Input of a capacity for storing at least the amount of data input to the input means during a total period between an access request interval for the memory means and a period from when the access request is issued until the access request is granted Data storage means;
The data transfer apparatus according to claim 1, further comprising: Each of the data input / output means is
An output means for outputting data;
Output of a capacity for storing at least the amount of data output from the output means during the total period of the access request interval to the memory means and the period from the issuance of the access request to the time when the access request is granted Data storage means;
The data transfer apparatus according to claim 1, further comprising:

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