JP3151416B2 - Data transfer control device and magnetic disk device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer control technique and a magnetic disk drive, and more particularly to a technique which enables high-speed data transfer via a buffer memory such as an inexpensive and large-capacity DRAM.

[0002]

2. Description of the Related Art For example, in a magnetic disk device which is one of external storage devices in a computer system or the like, a high-level device having a large data transfer capability and a magnetic disk drive having a relatively low data transfer speed due to a rotation wait or the like. For the purpose of matching data transfer with the device and improving the data transfer efficiency between the two devices, a part of the magnetic disk control device interposed between the magnetic disk drive device and the host device, etc.
A buffer memory made of a semiconductor memory such as M is provided.
It is known to perform data transfer via this buffer memory.

[0003] By the way, the DR that constitutes the buffer memory is used.
Conventionally, regarding the arbitration of the priority of the access to the AM, for example, the time of the read / write cycle of the DRAM is shortened by using the page mode,
By switching the priority at the time of write conflict in the refresh cycle, read and write are smoothed,
It is known to improve data transfer efficiency.

[0004] In addition, refresh requests to DRAMs are generally given the highest priority in order to ensure data reliability.

[0005]

In the above conventional method,
Even when the data transfer speed of one of the upper device or the lower device accessing the DRAM is several times faster than the other, the processing efficiency is not sufficient to give the same priority and the buffer access is performed every refresh cycle. It is necessary to give up the right, and there is a problem that the data transfer efficiency is surely reduced by the refresh.

Accordingly, it is an object of the present invention to improve the data transfer efficiency via a buffer memory interposed between both devices without being affected by the difference in data transfer speed between the upper device and the lower device. It is to provide a possible data transfer control technique.

Another object of the present invention is to provide a data transfer control technique capable of achieving both a reduction in the cost of a buffer memory and an increase in capacity and data transfer efficiency.

Still another object of the present invention is to improve the data transfer efficiency via a buffer memory interposed between a host device and a magnetic disk drive device without being affected by a data transfer speed gap between them. It is an object of the present invention to provide a magnetic disk drive capable of causing the magnetic disk drive to operate.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0010]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

According to the present invention, there is provided a data transfer control device for exchanging data between an upper-level device and a lower-level storage device via a main buffer memory for temporarily storing data. One and
It intervenes between the main buffer memory and temporarily holds data. In accessing the main buffer memory, an access request signal giving priority to the higher-order device and the lower-order storage device or the upper-order device and the lower-order storage device is used. A pre-buffer that outputs a non-priority access request signal, a processor that outputs a buffer access request signal that requests access to the main buffer memory, and an access request signal having a different priority output from the pre-buffer;
And arbitrating the buffer access request signal in accordance with the amount of data held in the preceding buffer, thereby giving priority to the execution of accesses to the main buffer memory of each of the upper device or the lower storage device and the processor via the preceding buffer. And an arbitration logic for dynamically changing

The present invention also relates to a magnetic disk drive for transmitting and receiving data between a host device and a magnetic disk drive via a main buffer memory for temporarily storing the data. An access request signal that is interposed between at least one of the drive units and the main buffer memory to temporarily hold data, and gives priority to the host device and the magnetic disk drive unit in accessing the main buffer memory; or A pre-buffer for outputting an access request signal not giving priority to the host device and the magnetic disk drive, a processor for outputting a buffer access request signal for requesting access to the main buffer memory, and a priority output from the pre-buffer. Different access request signals and buffer access requirements By arbitrating signals according to the amount of data held in the preceding buffer, the priority order of execution of access to the main buffer memory of each of the host device or the magnetic disk drive and the processor via the preceding buffer is dynamically determined. And an arbitration logic that changes to

When the main buffer memory is constituted by a DRAM, a refresh counter for outputting a refresh request signal to the main buffer memory at a predetermined interval is provided, and the arbitration logic has different priorities output from the preceding buffer. By arbitrating the access request signal, the buffer access request signal, and the refresh request signal, the upper device or the lower storage device (magnetic disk drive) via the preceding buffer, the refresh counter, and the main buffer of each of the processors An operation of dynamically changing the priority of execution of access to the memory is performed.

In this case, for example, the read / write processing of a lower-order storage device such as a magnetic disk drive is to execute at least one sector (generally 512 bytes) at a constant speed accompanying the steady rotation of the magnetic disk. By paying attention and considering the access address to the main buffer memory, the setting is made so that the DRAM can be refreshed by using the actual transfer data between the upper device and the lower storage device when reading and writing between them. .
In other words, if necessary, the access request to the main buffer memory is determined so that the priority of the access request from the higher-level device or the lower-order storage device is higher than that of the refresh request signal. Make the action delegate possible.

According to the data transfer control device and the magnetic disk device of the present invention described above, for example, the transfer speed of the host device such as a host computer is several times faster than that of the lower storage device such as a magnetic disk drive. In the read processing, the upper buffer (upper FIFO memory) on the upper side and the lower buffer (lower F
IFO memory) operate in an empty state.

At the time of write processing, both the upper and lower precedent buffers operate in a full state.

Conversely, when the data transfer rate of the lower storage device is several times faster than that of the upper device, the device operates full when reading and empty when writing.

At this time, the priority of reading the main buffer memory is as follows: (1) lower FIFO memory has room, (2) upper FIFO memory has room, (3) lower FIFO memory is empty,
(4) Upper FIFO memory is full.

The priority of the main buffer memory at the time of writing is determined as follows: (1) lower FIFO memory has room, (2) upper FIFO
O memory available, (3) lower FIFO memory full, (4)
Upper FIFO memory empty.

By doing so, it is possible to dynamically switch the access right to the main buffer memory in the order of the processing having the higher priority from the entire data flow. As a result, it is possible to improve the efficiency of data transfer between the host device and the lower storage device such as a magnetic disk drive via the main buffer memory without being affected by the difference in data transfer speed between the host device and the lower storage device. it can.

In general, in a magnetic disk drive, when accessing a magnetic disk as a medium, a minimum of 1
Since the sectors are processed continuously, the data transfer speed during that time is a constant burst speed corresponding to the rotation speed of the magnetic disk.

Taking the magnetic disk drive manufactured by the applicant as an example, 9-bit addresses are accessed in 170 μs to transfer 512 bytes per sector at 3 Mbytes / sec.

However, since the read-ahead cache function actually operates, the same function operates even when the above access is performed for only one sector with one instruction and a time interval is provided between the next instruction and the next instruction. In the case of a disk drive, 48 Kbytes ≧ 15 bits) are accessed.

Actually, the overhead of several milliseconds of the magnetic disk controller or the host computer is generated for each command. Therefore, in the magnetic disk drive which does not support the prefetch cache function, the access of the minimum data length is performed at the minimum interval. Even if you repeat,
During the above overhead, the DRAM constituting the main buffer memory can be refreshed using actual transfer data.

[0025]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A data transfer control device and a magnetic disk drive according to one embodiment of the present invention will be described with reference to FIGS.

FIG. 1 is a block diagram showing an example of a configuration in a case where the present invention is applied to a magnetic disk control device in a magnetic disk device as an example of a data transfer control device and a magnetic disk device of the present embodiment.

The magnetic disk controller of the present embodiment includes a microprocessor (MPU) 1 for controlling the entire system, a host interface control circuit 2 for exchanging information with a host computer (HOST) (not shown), A disk interface control circuit 3 for transmitting and receiving information to and from a magnetic disk drive (not shown) (not shown), and data transmitted and received between the disk interface control circuit 3 and the host interface control circuit 2 And a buffer memory 11 (DRAM) that is temporarily stored.

The access of the host interface control circuit 2 and the disk interface control circuit 3 to the buffer memory 11 is controlled by the buffer access arbitration circuit 8, and the access is made to the address of the buffer memory 11 specified through the address selection circuit 10. Executed for

The data amounts transferred between the host interface control circuit 2 and the buffer memory 11 and between the disk interface control circuit 3 and the buffer memory 11 are counted by the transfer counter 6 and the transfer counter 7, respectively. Is done.

In the case of this embodiment, the buffer memory 11
The refresh access is performed based on the value of a refresh counter 9. The presence or absence and timing of the execution are managed by the buffer access arbitration circuit 8.

In this case, between the host interface control circuit 2 and the buffer memory 11, and between the disk interface control circuit 3 and the buffer memory 11, a FIFO memory 4 (previous buffer) having a smaller capacity than the buffer memory 11 is provided. And a FIFO memory 5 (pre-stage buffer).

FIFO memory 4 and FIFO memory 5
Of the FIFO counter 33 (H
FCNT) and FIFO counter 34 (SFCNT)
For example, as shown in FIG. 2 described later, this is grasped by the buffer access arbitration circuit 8.

Data exchange with a host computer (not shown) is performed by the host interface control circuit 2, and when data transfer is possible, a transfer request signal HSREQ35 is output to a host controller (not shown).
When the host controller permits the transfer, a transfer permission signal HSACK37 is returned, and the HSACK37 or the HSACK37 is transmitted.
Transfer of data in synchronization with REQ35 is performed in FIFO memory 4
Done through.

At this time, the transfer byte address HOSTA
DR 31 is counted by the transfer counter 6.

At this time, the number of bytes of the FIFO memory 4 is F
This is reported by the IFO counter 33.

On the other hand, data exchange with an interface controller (not shown) of a lower drive (not shown) is performed by the disk interface control circuit 3, and when data transfer is possible, a transfer request signal DKREQ 36 is output to the disk controller. . When a disk controller (not shown) permits the transfer, a transfer permission signal DKACK 38 is returned, and the DKACK 38 or DKACK 38 is returned.
Transfer of data in synchronization with REQ36
Done through.

At this time, the number of bytes of the FIFO memory 5 is F
This is reported by the IFO counter 34.

Byte address HDCADR32 for this transfer
Are counted by the transfer counter 7.

Buffer access request HREQ 22 for transfer to the host computer, buffer access request DREQ for transfer to a drive (not shown)
26, a buffer access request MREQ24 (buffer access request signal) of the microprocessor 1 for controlling the disk controller, and a buffer access request R by the refresh counter 9 for refreshing the buffer memory (DRAM) 11 constituting the buffer memory.
The access arbitration of the EFREQ 29 (refresh request signal) is performed by the buffer access arbitration circuit 8, and the permission signals HACK23 and DACK are respectively provided for the selected requests.
27, MACK25, and REFACK28 are returned.

Byte address HOST at the time of access request
ADR31, HDCADR32, MPUDR21, and REFADR30 are used by the address selection circuit 10 to select signals SELECT from the buffer access arbitration circuit 8.
Selected at T8a.

The selection addresses of the address selection circuit 10 are a row address RAWADR39 and a column address COLU.
MNADR39a.

The refresh counter 9 is reset by a permission signal DACK 27 for a transfer request from the drive.

FIG. 2 shows an embodiment of the configuration of the buffer access arbitration circuit 8.

The buffer access arbitration circuit 8 of this embodiment
Are OR circuits 40 and 41 and OR circuits 42 and 43 interposed between the arbitration logic 45 and the FIFO memories 4 and 5, OR circuits 64 and 65, AND circuits 62 and AND Circuit 63, and an OR circuit 47 and an OR circuit 47 provided on the output side of the arbitration logic 45.
And a circuit 48.

FI on the host interface control circuit 2 side
From the FO memory 4 to the arbitration logic 45, the logic signal 4
a, a logic signal 4b, a logic signal 4c, and a logic signal 4d are output. The logical signal 4a and the logical signal 4b are ORed.
The signal becomes an HHREQ 22 a (access request signal) described later via the circuit 40, and is input to the arbitration logic 45 via the OR circuit 64.

The logical signal 4c and the logical signal 4d are ORed.
An HLREQ 22b (access request signal), which will be described later, passes through the circuit 41, and a part of the HLREQ 22b is AND
The logical AND with the HLAST 60 described later is obtained via the circuit 62, and the result is input to the OR circuit 64 together with the HHREQ 22a.

Similarly, from the FIFO memory 5 on the side of the disk interface control circuit 3 to the arbitration logic 45, the logical signals 5a, 5b and 5c,
The logic signal 5d is output. The logic signal 5a and the logic signal 5b are passed through an OR circuit 42 to a DHREQ 26a to be described later.
(Access request signal), which is input to the arbitration logic 45 via the OR circuit 65.

The logical signal 5c and the logical signal 5d are ORed.
A DLREQ 26b (access request signal), which will be described later, passes through the circuit 43, and a part of the DLREQ 26b is AND
The logical product with a later-described DLAST 61 is obtained via the circuit 63, and the result is input to the OR circuit 65 together with the DHREQ 26a.

FI on the host interface control circuit 2 side
When reading the disk, the FO memory 4 counts down by a transfer permission signal HSACK 37 from the host computer, and outputs a permission signal HACK 23 from the arbitration logic 45.
Count up by

At the time of disc writing, the above-described count-up and count-down are reversed.

When the disk is read, the FIFO memory 5 on the drive side transfers a transfer permission signal DKACK from the lower drive.
The count is incremented by 38, and the count is decreased by the permission signal DACK27 from the arbitration logic 45.

At the time of disk writing, the above-described count up and count down are reversed.

Depending on the situation where the data in the FIFO memories 4 and 5 is stored, the buffer access request signals H having different priorities on the HOST side and the drive side respectively.
HREQ22a (HOST side high priority), HLREQ2
2b (HOST-side low priority), DHREQ 26a (drive-side high priority), and DLREQ 26b (drive-side low priority) are selected by the arbitration logic 45.

The arbitration logic 45 additionally outputs a buffer access request MREQ 24 by the microprocessor 1.
A buffer access request REFREQ 29 for refreshing by the refresh counter is also arbitrated.

In the arbitration, the arbitration permission timing signal ARBI
This is performed at a timing set by the TEN 46.

In FIG. 2, MREQ 24, DHREQ 26
a, REFREQ29, HHREQ22a, DLREQ
An example in which priorities are assigned in the order of 26b and HLREQ 22b is shown.

FIG. 3 shows the relationship between the state of the FIFO memories 4 and 5 and the buffer access priority at the time of disk reading and at the time of disk writing, respectively.

As an example, the case where the HOST interface circuit accesses in the page mode of m pages is as follows.
When the FIFO memory 4 is empty to (full-m) at the time of reading (when the logical signal 4a is on), m
It can be determined that there is a free area of bytes or more and that data of one or more pages can be transferred from the buffer.

When the FIFO memory 4 is m to full at the time of writing (when the logical signal 4b is on), the FIFO memory 4
Is transferred from the HOST, and it can be determined that the data can be written to the buffer memory 11.

In the above two cases, the priority of the transfer request on the host side is determined to be higher, and the HHREQ 22
A buffer access request is made as a.

When the FIFO memory 4 is full to (full-m) at the time of reading (when the logical signal 4c is ON),
Since there is no m-byte free area in the O memory 4, it can be determined that data of one page cannot be transferred from the buffer memory 11.

When the FIFO memory 4 is empty to m at the time of writing (when the logical signal 4d is on), m bytes of data have not been transferred from the HOST to the FIFO memory 4;
It can be determined that writing to the buffer memory 11 is not possible.

In the above two cases, the priority of the HOST transfer request is assumed to be low, and the OR
LREQ22b.

For example, when the drive is accessed from the disk interface control circuit 3 in the page mode of n pages, when the FIFO memory 5 is full from n (when the logic signal 5a is ON) at the time of reading, the FIFO is used. It can be determined that data of n bytes or more has been transferred from the drive to the memory 5 and can be written to the buffer memory 11.

When the FIFO memory 5 is empty to (full-n) at the time of writing (when the logical signal 5b is on), the FIFO memory
It can be determined that there is a free area of n bytes or more in the memory 5 and the data can be transferred from the buffer memory 11.

In the above two cases, the priority of the transfer request on the drive side is determined to be higher, and the DHRE
A buffer access request is made as Q26a.

When the FIFO memory 5 is empty to n at the time of reading (when the logical signal 5c is on), n bytes of data have not been transferred from the drive to the FIFO memory 5;
It can be determined that writing to the buffer memory 11 is not possible.

At the time of writing, the FIFO memory 5 becomes (full-
n) to FI (when the logic signal 5d is ON)
It can be determined that there is no n-byte free area in the FO memory 5 and transfer from the buffer is impossible.

The above two cases are calculated by the OR circuit 43.
Drive transfer request DL with low priority of drive transfer request
REQ26b.

FIG. 5 shows one embodiment of the arbitration timing of the access to the buffer memory 11.

The timing of each signal is based on the basic clock CLK.
Based on 50.

This example shows a case where the buffer memory 11 is accessed in the page mode of four pages.

When the transfer speed of the drive is higher than the transfer speed of the host computer, the data is transferred with the buffer memory 11 being full at the time of reading and the buffer memory 11 being almost empty at the time of writing.

At this time, the DHREQ 26a (the FIFO memory 5 has accumulated 4 bytes or more = at least one page can be transferred), and the HLREQ 22b (the FIFO memory 4 has accumulated (full-4) or more = one page is not empty. ) Turns ON.

Since the priority of the DHREQ 26a is higher, the DHACK 27a is returned and the access right of the buffer memory 11 is given to the drive.

Buffer access for transfer with the drive is performed while DHACK 27a is ON.

In this example, since the access is performed in the page mode of four pages, one row address 39 (ROW A) is used.
DR) for four consecutive column addresses 39a
(COLUMN ADR) (COL # 0 to # 3).

Data is written at the timing of BUFWR 53, and data is read at the timing of BUFRD 54. The FIFO memory 5 counts up and down at the timing of FIFOCNT 55.

After selecting the last column address (COL # 3), the next buffer access right is selected at the timing of ARBITN 46. In this example, since the DHREQ 26a loses the priority at the timing of CLK = 1, the HLREQ 22b that has given up the access right and has been waiting for the selection has the C level.
LK = 13 access right arbitration selected, HLACK
23b is returned.

During this time, the transfer from the HOST to the FIFO memory 4 on the HOST side may progress, and the request on the HOST side may be changed to the HHREQ 22a having a higher priority than the HLREQ 22b.

In this case, HH for HHREQ 22a
Since ACK 23a is returned, there is no problem in transfer (FIG. 6).
reference).

When the reference unit of the data transfer amount is not a multiple of the number of bytes for one page in the page mode but is a fraction at the end of the transfer, the DHREQ 26a and the HHREQ 22a
DLREQ 26b and HLREQ 22b are issued.

In this case, in order to increase the priority, a signal HLAST60, a signal DLAST61 indicating the end of the transfer,
The HLREQ 22b and the DLREQ 26b obtained by the AND operation by the AND circuit 62 and the AND circuit 63 are converted into HH signals, respectively.
REQ22a, DHREQ26a and OR circuits 64, 65
And is ORed.

DLRE for transferring last one byte
FIG. 7 shows an example of the timing of buffer access right arbitration for Q26b.

The DLRE 26b itself has a lower priority than the HHREQ 22a, but the DLAST 61 is ON.
It is regarded as having the same priority as DHREQ 26a,
K27a is returned to obtain the buffer access right.

At the end of the transfer of the first column address, the buffer access is terminated, DLACK 27b is turned off, and ARBITEN4 for the next buffer access right is set.
6 turns on.

In the above embodiment, the buffer access is set to the page mode of 4 pages on both the upper and lower sides. However, a table is created as shown in FIG.
Switching of 6 pages, buffer memory 11 (DRAM)
A method of selecting switching between 256 Kbytes / Mbytes is also conceivable.

The upper side m and the lower side n based on the data amount of the FIFO memory 4 (5) for determining the priority of the buffer access are not the page access amount of the buffer memory 11, but the capacity of the FIFO memory 4 or 5. It is also conceivable to set the value in 1 / integer or the absolute number of bytes.

In the structure of this embodiment, the FIFO memory 4 and the FIFO memory 5 can be constituted by a buffer having a plurality of planes.
It is also conceivable to use an AM.

As described above, according to the data transfer control device and the magnetic disk device of the present embodiment, for example, when accessing a standard drive, (1). At the time of access, by raising the priority when one page of data is accumulated in the FIFO memories 4 and 5 or when there is a space for one page, the upper and lower layers always operate in a time-divided page mode efficiently. Therefore, it is possible to configure the buffer memory 11 of the magnetic disk control device that requires high-speed access with a low-cost large-capacity DRAM.

(2) At present, generally, it is possible to substitute the refresh necessary for the DRAM used for constructing the buffer memory 11 by the buffer access from the drive side, and the data transfer for the refresh is performed. The frequency of interruption is reduced, and the efficiency of data transfer via the buffer memory 11 is improved.

[0092]

Advantageous effects obtained by typical ones of the inventions disclosed in the present application will be briefly described.
It is as follows.

That is, according to the data transfer control device of the present invention, the data transfer efficiency via the buffer memory interposed between the upper device and the lower device is not affected by the difference in data transfer speed between the upper device and the lower device. Can be improved.

According to the data transfer control device of the present invention,
An effect is obtained that it is possible to achieve both a reduction in the cost of the buffer memory and an increase in the capacity and the data transfer efficiency.

According to the magnetic disk drive of the present invention, it is possible to improve the data transfer efficiency via the buffer memory interposed between the host and the drive without being affected by the data transfer speed gap between the host and the drive. Is obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an example of a configuration of a data transfer control device and a magnetic disk device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing one embodiment of a configuration of an access arbitration circuit in the data transfer control device according to one embodiment of the present invention.

FIG. 3 is an explanatory diagram showing an example of a relationship between a state of a FIFO memory and a buffer access priority at the time of a disk read in a data transfer control device according to an embodiment of the present invention.

FIG. 4 is an explanatory diagram showing an example of a relationship between a state of a FIFO memory and a buffer access priority at the time of a disk write in a data transfer control device according to an embodiment of the present invention.

FIG. 5 is a timing chart showing an example of the operation of the data transfer control device according to one embodiment of the present invention.

FIG. 6 is a timing chart showing an example of the operation of the data transfer control device according to one embodiment of the present invention.

FIG. 7 is a timing chart showing an example of the operation of the data transfer control device according to one embodiment of the present invention.

FIG. 8 is an explanatory diagram showing a configuration example of a buffer memory in the data transfer control device according to one embodiment of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Microprocessor (MPU), 2 ... Host interface control circuit, 3 ... Disk interface control circuit, 4 ... FIFO memory (previous buffer), 4a ... Logic signal, 4b ... Logic signal, 4c ... Logic signal, 4d ... Logic signal 5, FIFO memory (previous buffer), 5a logical signal, 5b logical signal, 5c logical signal, 5d logical signal, 6 transfer counter, 7 transfer counter, 8 buffer access arbitration circuit, 9 refresh Counter, 10
... Address selection circuit, 11 ... Buffer memory (DRA)
M), 33 ... FIFO counter, 34 ... FIFO counter, 40 ... OR circuit, 41 ... OR circuit, 42 ... OR circuit, 43 ... OR circuit, 45 ... Arbitration logic, 47 ... OR circuit, 48 ... OR circuit, 62 ... AND circuit, 63 ... AND
Circuit, 64 ... OR circuit, 65 ... OR circuit.

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Mitsuru Kubo 2880 Kozu, Kokuzu, Odawara-shi, Kanagawa Prefecture Inside the Odawara Plant, Hitachi, Ltd. 56) References JP-A-63-192151 (JP, A) JP-A-63-192150 (JP, A) JP-A-62-93728 (JP, A) (58) Fields studied (Int. Cl. ⁷ , (DB name) G06F 13/12 G06F 3/06

Claims (6)

(57) [Claims] 1. A data transfer control device for exchanging data between an upper-level device and a lower-level storage device via a main buffer memory that temporarily holds the data, wherein the upper-level device and the lower-level storage device An access request signal interposed between at least one of the devices and the main buffer memory for temporarily holding the data and giving priority to the upper device and the lower storage device in accessing the main buffer memory; A pre-buffer that outputs an access request signal that does not give priority to the upper device and the lower storage device; a processor that outputs a buffer access request signal that requests access to the main buffer memory; and a processor that is output from the pre-buffer. The access request signals having different priorities and the buffer access request Execution of access to the main buffer memory of each of the higher-order device or the lower-order storage device and the processor via the previous-stage buffer by arbitrating a signal in accordance with the amount of the data held in the previous-stage buffer; Arbitration logic for dynamically changing the priority order of the data transfer control device. 2. The data transfer control device according to claim 1, wherein said main buffer memory is a DRAM, and said data transfer control device outputs a refresh request signal to said main buffer memory at a predetermined interval. A counter, wherein the arbitration logic arbitrates the access request signals having different priorities output from the preceding buffer, the buffer access request signal, and the refresh request signal, so as to pass through the preceding buffer. A data transfer control device for dynamically changing the priority order of execution of access to the main buffer memory of each of the upper device or the lower storage device, the refresh counter, and the processor. 3. The data transfer control device according to claim 1, wherein said first-stage buffer is a first-in first-out memory (FIF).
O) The data transfer control device according to (1). 4. A magnetic disk drive for transmitting and receiving data between a host device and a magnetic disk drive via a main buffer memory for temporarily storing the data, wherein the host device and the magnetic disk drive An access that is interposed between at least one of the drive units and the main buffer memory to temporarily hold the data, and gives priority to the host device and the magnetic disk drive unit in accessing the main buffer memory. A pre-buffer that outputs a request signal or an access request signal that does not give priority to the host device and the magnetic disk drive, a processor that outputs a buffer access request signal that requests access to the main buffer memory, and the pre-buffer Access request signals with different priorities output from And by arbitrating the buffer access request signal in accordance with the amount of data held in the preceding buffer, the upper device or the magnetic disk drive via the preceding buffer, and the processor Arbitration logic for dynamically changing the priority of execution of accesses to the main buffer memory;
A magnetic disk drive comprising: 5. The magnetic disk device according to claim 4, wherein said main buffer memory is a DRAM, and said magnetic disk device includes a refresh counter for outputting a refresh request signal to said main buffer memory at a predetermined interval. The arbitration logic comprises: arbitrating the access request signals having different priorities output from the pre-buffer, the buffer access request signal, and the refresh request signal, so that the arbitration logic passes through the pre-buffer. A magnetic disk device characterized by dynamically changing the priority of execution of access to the main buffer memory of each of a host device or the magnetic disk drive, the refresh counter, and the processor. 6. The magnetic disk drive according to claim 4, wherein said first-stage buffer is a first-in first-out memory (FIF).
O) A magnetic disk drive characterized in that: