JPS5995611A - Monitoring and controlling equipment for programmable controller - Google Patents

Abstract

PURPOSE:To constitute a monitoring equipment and a programmable controller PC in one body and to perform transmission and reception of their data fast at signal bus levels of both a CPU for the PC and a monitor CPU. CONSTITUTION:The monitor CPU2 sends a temporary stop request signal (e) to the CPU11 for the PC when a request to read the operation state of the PC or write a sequence program, etc., in the PC is made by operating a keyboard 6, and when the CPU11 for the PC stops temporarily, a temporary stop completion signal (f) is supplied from the CPU11 for the PC to a bus switch 9. Consequently, a signal bus D1 for the monitor CPU is connected to a signal bus D2b and the monitor CPU2 performs reading from writing to a control program memory 12, data memory 13, sequence program memory 14, process output interface 15, and process input interface 16.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is based on the invention,
Before explaining the present invention, the general configuration of the conventional device will be explained. will be explained with reference to Fig. 1. 《1》 in Fig. 1 is an example of a supervisory monitoring device with a CRT. (2) is a CPU, (3) is a program memory for u control, (4) is a temporary storage memory, ( 5) is keyboard 1 controller, (6) is keyboard, (7) is C
JtT controller, (8) is CILT, (9》 is PC)
The external interface for exchanging signals with σO is the CPU (2), control block memory (3), temporary memory (4), etc. A signal bus for address, data, etc. for exchanging signals with the board controller (5), cit'r controller (7), and interface (9).

On the other hand, (Ql) +, tOPU, (x2 is a control programmable memory, 03 is a data memory, 04) is a sequence program memory, aQ is a process output interface, (IQu process input interface, θ
η is an external interface for transmitting and receiving signals with the monitoring device (1) with Oil 0 ILT, 1 is the process input, b is the process output, and D is the OP U (I
ll, control program memory O2, data memory α3
．． This is a signal bus for sending and receiving signals such as addresses and data between the sequence block memory Q4), the process output interface 0υ, and the process input interface αQ.

As mentioned above, this type of monitoring device (1) is connected to the PC (10) and the J1 connecting cable α, which is separately provided.
Not only is υ required and expensive, but also CPU (2
) or αυ signal bus, mutual data exchange can be performed at high speed.

The present invention is designed to eliminate the drawbacks of the conventional devices as described above, and to integrate the monitoring device and the PC.
The purpose of the present invention is to provide a device that can exchange data between the two at high speed at the signal bus level of E I'U. The details will be explained below.

Fig. 2 47) (2) 11 OF U for motor, (
+n);r P to 1Hcn+dema). ri3)~(8
), (lri～(1(S and 11.b are the same as those in Figure 1, and their explanations are omitted. FC, Shinq Has]
Switch to the opposite side with J2a] and PCJTIOP
LIα1) and control program memory (12, data memory ([J, sequence program memory (141)
, process output interface 0υ, and process input interface θq are connected. Now, °, monitor c 1) u (2+
Since the t-a keyboard (6) is operated, it is necessary to read the operating status of the PC and write the 0\sequence block → m, etc. At this time, Monitor OP U (2) I) For PC (
': P U (1) Temporary suspension request redemption number 6 ノ)'+
First, let me know] PCCOOP U QIJ
When is paused, the pause completion @f becomes 1' JI
From OP U (II), 7chi (given to 19,
+ is connected to signal bus J,) 211] monitor C',
P u (2) Yosu1tll Department block memo I+
(121, Data Memo II (11° Sequence Program Memory θ4), Process Output'/Tarface O
ri+, process human interface (1(9-\
Lead Orney 1j-Fitop + Stl Noh 2 rr
, 1 reads the process input (-) through the process input interface Of9 I7.0 (,T
Controller (7); +jH-r (s l+,'r
(s++z Table 77 < Surukoto II) Monitoring the operation of the PC (7) or conversely operating the key 11 <- to write the block data to the sequence program memory 040 to write the block rope? The above explanation is that the PC signal bus and monitor (1℃
Since the signal path is directly connected to the bus switch and Tsuchiko, there is no need for an external interface like with conventional devices.If you only want 4C, it is inexpensive and can send and receive signals at daytime speeds.
fllJ) HA 7 'y / 1ノ,, ') トI thousand IiJ] ding し) z1#, it is,

[Brief explanation of the drawing]

FIG. 1 shows an example of the configuration of a conventional device, and FIG. 2 shows an embodiment of the present invention, and in FIG.
t (3Ri'i' monitoring device l!(,,(2)i,t
CPU, (11) 12 programmable controller OP[], Q"intelligence switch, 1) 2R,, I)
2b is a signal bus for the programmer full controller, f is a pause completion signal, and in FIG. 1-11, the same reference numerals are the same or 1. The part corresponding to r is shown.

Claims (2)

[Claims] (1) A bus switch that is equipped with a programmable controller CPU and a monitor CPU that monitors the operation of the programmable controller, and connects any of the CPUs to the signal bus of the programmer full controller.
A temporary stop request signal is issued to the monitor CPU, and when the temporary stop is completed, the bus switch is sent from the signal bus for the programmer full controller to the monitor CPU (3PU
This supervisory control device for the programmer full controller is configured to switch to the bus and connect to the signal bus for the programmer full controller. (2) All input/output devices such as the sequence block memory and data memory of the programmer full controller can be read/written by the monitoring CPU. supervisory control equipment,