JPS5982648A - Controlling device for video tape recorder - Google Patents

Abstract

PURPOSE:To control plural VTRs simultaneously by a complex controlling means by driving an information signal processing circuit in a remote controlling device by a clock signal having a frequency higher than that of a clock signal to be used for the transmission/reception of a command signal and an information signal between a communication circuit and an I/O circuit. CONSTITUTION:When a status signal or a time code signal is transmitted from a VTR1 or 2, a series I/O circuit 6 reads data successively by a clock signal S1 from a clock oscillator 10. At that time, a microprocessor MP7 applies a preset signal S6 to a timer controller 8, which counts up clock signals S5 from a clock oscillator 11 and, every reach of a preset value, generates a reference synchronizing signal S4 and sends the signal S4 to the MP7 as an interruption signal advancing the processing step. Every arrival of the information signal of one frame from the VTRs 1, 2, the MP7 returns a command signal S3 obtained in accordance with the prescribed editing process to the VTRs 1, 2.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a control device for a video tape recorder, and is particularly suitable for application when controlling a plurality of video tape recorders in a related manner.

[Background technology and its problems]

Conventionally, in an automatic editing system configured using multiple video tape recorders (VTRs) as this type of control device, when attempting to automatically edit the image information of multiple VTRs in a predetermined order, A common remote control device is provided for the control system, and each VT
The information signals (consisting of status signals and time code signals) transmitted from R via the communication equivalent cable are monitored by a remote control device, and each VTR is
A device is used that sends back a command signal instructing a response action. Here, the status signal represents the current operating mode of the VTR, and the time code signal represents the tape position of the video head (for example, an address assigned to each field).

By the way, due to the characteristics of communication lines used in such control systems, there is a limit to the baud rate, which is usually 2-52.
-5C] Each VTR is controlled using a signal with a frequency of about -5C], and standards have been established to ensure compatibility among VTRs.

In practice, a remote control device has an information signal processing circuit consisting of, for example, a microprocessor, and when forming various command signals for controlling each VTR, a master clock processor is clocked at a frequency corresponding to the standard standard of the communication line. The VTR 5 is operated at a high frequency to process information signals arriving from the VTR 5 and return command signals.

However, in this case, if the number of VTRs increases or the amount of information to be processed increases, such as when trying to perform complex control, there is a risk that the amount of information to be processed will not be able to be processed.

[Purpose of the invention]

The present invention was made to solve this inconvenience.
The present invention attempts to propose a control device that can sufficiently increase the amount of information signal processing within the remote control device as required while satisfying the frequency limitations of signals in communication lines.

SUMMARY OF THE INVENTION To achieve the above object, the present invention transmits signals between a remote control device and a VTR using a clock signal having a first frequency, and also performs signal processing inside the remote control device using a clock signal having a first frequency. A clock signal having a second frequency higher than the first frequency.

〔Example〕

An embodiment of the present invention will be described in detail below with reference to the drawings.

In Figure 1, (1) is the first VTR that operates as a player (or mask), (2) is the second VTR that operates as a recorder (or slave), and (3) is the first and second VTR. A remote control device commonly provided for VTRs (1) and (2), and the remote control device (3) is a time-series signal transmitted through cables (4) and (5) as communication lines. Series input/output circuit (6) that inputs and outputs transmission signals of
and an information signal processing circuit (9) comprising a microprocessor (7) and a timer controller (8) connected to the serial input/output circuit (6).

The serial input/output circuit (6) is the first clock oscillator (10)
receives an information signal S2 consisting of a status signal and a time code signal as a transmission signal driven by a clock signal S1 of the VTR (1) and (2) via cables (4) and (5); cable(
A command signal S3 is sent as a transmission signal to be sent back to the VTRs (1) and (2) via signals 4) and (5).

Here, the oscillation frequency of the clock oscillator (10) is selected to be the standard frequency of the communication line (for example, 2.5 (:Mn2)), and thereby the remote control device (3) can be operated while satisfying the frequency limit for the communication line. VTR (
Transmission signals can be sent and received between 1) and 2).

On the other hand, the microprocessor (7) is driven by the second clock oscillator (11) and the serial input/output circuit (
VTR (1) and (6) compare the information signal S2 consisting of a status signal and a time code signal received serially over time with a predetermined processing procedure, and
2) sends out a command signal S3 for controlling. The microprocessor (7) is interrupted each time a status signal or a time code signal arrives and executes processing for each signal.

The operation of this microprocessor (7) is executed based on the timing of the reference synchronization signal S4 of the timer controller (8). The timer controller (8) is composed of a counter that performs a counting operation using the clock signal S5 of the clock oscillator (11) according to the instructions of the microprocessor (7) every time a status signal or time code signal arrives. A reference synchronization signal S4 is generated each time the built-in preset data S6 is read and the count reaches this preset data value, and thus the count ratio of the timer controller (8) is determined by the preset data value. .

Here, the value of the preset data S6 preset from the microprocessor (7) to the timer controller (8) is, for example, 16.6 (msec) (when processing a video signal of the NTSC system, the field frequency is 6 (1 (
f(z) representing a period of 01),
As a result, the timer controller (8) generates the reference synchronization signal S4 (FIG. 2A) every 16.6 m5ec, which corresponds to one field. When the microprocessor (7) receives this reference synchronization signal S4, as shown in FIG. It is designed to process signals.

Incidentally, in the first field interval FLI, the microprocessor (7) exchanges the status signal with the VTRs (1) and (2) at the first time T1, and then exchanges the received status signal at the second time T2. After that, at a third time T3, a command signal is sent to VTR (1) or (2) in accordance with the processing result. Thus, status processing is executed at the first and second times T1 and T2. Also, in the second field section FL2, the micro 7'' processor (
7) exchanges the time code signal with the VTRs (1) and (2) at the fourth time T4, and then at the fifth time.

The time code signal received at T5 is processed, and then at the sixth time T6, the VTR is processed according to the processing result.
Send a command signal to (1) or (2). Thus, time code processing is executed at the fourth and fifth times T4 and T5.

The contents of the command No. 4W sent at the third and sixth times T3 and T6 include editing commands, channel selection commands, phase adjustment output, audio/video selection commands, etc.
Contains commands and data necessary to control TR(1) and (2>.In addition, during time To provided prior to time T1 and T4, VTR(1) and (2) confirm the transmission signal. This is the time required for

The microprocessor (7) controls the first and second VTRs (1
) and (2) in a predetermined procedure as shown in FIG. That is, the time code 811 assigned to each field in the tape track pattern from the first and second VTRs (1) and (2) is received by the time code register (15), and the clock oscillator (11) The time code generator (16) receives the clock signal S5 of the clock signal S5, and the time codes generated by the time code generator (16) are compared in the first comparator (17), and if there is a difference, the difference output 812 The controller (18) is operated according to the phase modulation output S13 to the first
and the second VT, R(1) and (2). At this time, the first and second VTRs (1) and (2) perform a phase adjustment operation to match the time code generated by the time code 1 generator (16).

On the other hand, the stored contents of the time code register (15) are compared with the time codes sequentially read out from the system RAM (3)) in the second comparator (19), and when they match, the mode switching signal S14 is sent from the controller (18). is transmitted to the first and second VTRs (1) and (2), respectively, and the operating modes of the first and second VTIs (1) and (2) are transmitted to the first and second VTRs (1) and (2), respectively, as editing procedure information written in the system RAM (20). It is arranged to switch sequentially according to the situation.

In the above configuration, when the status signal or time code signal is transmitted from the VTR (11 or (2)), the serial input/output circuit (6) sequentially reads it from the clock oscillator (10) using the clock signal S1. A preset signal S6 is given from the microprocessor (7) to the timer controller (8), and the timer controller (8) counts the clock signal S5 of the clock oscillator (11) and generates a reference synchronization signal S4 every time the preset value is reached. and sends this to the microprocessor (7) as an interfraft signal to proceed with the processing step.Therefore, the microprocessor (7) performs the process as shown in FIG. 2 every time the reference synchronization signal S4 arrives from the timer controller (8). The processing operations described above are executed, thus VTR (1) and (
Every time an information signal for one frame (that is, two fields) arrives from 2), a command signal S3 according to a predetermined editing procedure is sent back to the VTRs (1) and (2).

Therefore, the transmission of information signals and command signals between the serial input/output circuit (6) and the communication circuit is performed using a clock oscillator (10) having the same frequency as the standard frequency (2.5 [MHz]). In contrast, the processing of information signals and the generation of command signals by the microprocessor (7) and timer controller (8) are performed using a clock signal S1 at a frequency higher than the frequency of the clock signal S1 (4(
It is executed at high speed by the clock signal S5 of the clock oscillator (11) with MHz)). Therefore, according to the configuration shown in FIG. 1, compared to the case where all the information is processed using the clock signal of the standard frequency of the communication line, the amount of information processed by the 71 microprocessor (71
), it can be executed on multiple VTRs (1
) and (2) can be controlled simultaneously even with a fairly complicated control procedure.

The remote control device (3) having the above configuration can be realized by the specific configuration shown in FIG. In Fig. 4, the remote control device (3) and the first and second VT
The signal between R (11 and (2)) is sent to the terminal (33A
), (33B) and (34A), (34B
) and is sent and received by the series input/output circuit (6).

The serial input/output circuit (6) transfers data signals among transmission signals to and from the microprocessor (7) through a data bus (36) and a buffer circuit (37), as well as various control signals. is further transferred to and from the microprocessor (7) through a control signal line (38) and a buffer circuit (39). Incidentally, the control signals include a request signal (IOREQ), a read signal (RD), an interft signal (INT), and a reset signal (RESE).
T), etc.

In this way, the series input/output circuit (6) connects the first and second VT.
A clock oscillator (10) is prepared to send and receive transmission signals between R(1) and (2), and the clock signal S1 causes the serial input/output circuit (6) to connect to the terminal (33A).
), (33B) and (34A), (34
B) The transmission signal is sent to or received from the receiver. The oscillation frequency of this clock oscillator (10) is determined by the transmission line (31) between the VTRs (1) and (2).
and (32) usage frequency (e.g. 2.5 CMHz)
) are selected to match.

On the other hand, the timer controller (8) connects the data bus (36)
It receives preset value data through the buffer circuit (37), and receives a control signal through the control signal line (38) and further through the buffer circuit (39). The timer controller (8) is a microprocessor (
7) clock oscillator (11) (e.g. 4 (M, H
It performs a counting operation according to a clock signal Sl of a pulse oscillator (consisting of a pulse oscillator), and sends an interrupt signal to the microprocessor (7) when it reaches a preset value sent from the microprocessor (7) to the data bus (36). As a result, the data processing or time code processing program (FIG. 2B) of the microprocessor (7) is started for each field section.

The processing operations in the microprocessor (7) are thus carried out at surface speed by the clock signal S5 of the clock oscillator (11), and the data to be processed are fed into the microprocessor (7) and the processed data are
- A clock signal S1 of a clock oscillator (10) is applied to the serial input/output circuit (6) in order to send the signal to the microprocessor (7). Thus, the series input/output circuit (6
) is activated by the clock signal S1 of the clock oscillator (10) at the frequency (2', 5 [MHz:) ) of the VTR.
(1) and (2), and transmits data to and from the microprocessor (7) at its frequency (4 (: MHz)) using the clock signal S5 of the clock oscillator (11). and transmits and receives signals and performs arithmetic processing thereof.

Therefore, the signal processing speed inside the remote control device (3) can be adjusted between the remote control device (3) and the VT.
Since the signal processing speed between R(1) and R(2) can be executed at a higher speed, it is possible to easily control a plurality of VTRs (1) and (2) at the same time.

In the above description, an embodiment in which the present invention is applied to an NTSC system VTR has been described; however, the present invention is not limited to this, and in the case where it is possible to switch to other systems such as PS system, the microprocessor (7) What is necessary is to change the preset value to the timer controller (8).

〔Effect of the invention〕

As described above, according to the present invention, the information signal processing circuit (9) of the remote control device (3) is used for passing information signals and command signals between the communication line and the input/output circuit (6). By driving with the clock signal S5 having a higher frequency than the frequency of the clock signal S1, it is possible to easily control a plurality of VTRs simultaneously and with a complicated control procedure.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a tape recorder control device according to the present invention, FIG. 2 is a 'Rr diagram for explaining its signal processing operation, and FIG. 3 is a detailed diagram of the microprocessor shown in FIG. 1. FIG. 4 is a block diagram showing the specific configuration of the control device. (1), (2)-VTR1 (3)...Remote control device, (6)...Series input/output circuit,
(7)...Microprocessor, (8)...Timer controller, (9)...Information@signal processing circuit, (io
), (ii)...Clock oscillator, (37),
(39)...Buffer circuit. Figure 3

Claims (1)

[Claims] a remote control device comprising an information signal processing circuit for forming a command signal for controlling the video tape recorder based on information signals such as at least a status signal and a time code signal transmitted from the video tape recorder; , a video tape recorder characterized in that the information signal and the command signal are transmitted at a first frequency, and the information signal processing circuit is driven by a second clock signal having a higher frequency than the first frequency. control device.