JPS5979481A - Memory interleave control system - Google Patents

Abstract

PURPOSE:To simplify the constitution of an address selecting circuit by switching an interleave number only with a partial shift of a system bus address. CONSTITUTION:In a 2-way state an S30 is positioned at the least significant digit of a memory bus addresses, i.e., at the least significant digit of the address within a board in a conventional address. In this example, however, the S30 is positioned at the bit 4 of the memory bus addresses, i.e., at the most significant digit of the address within the board. In such a way, just a difference exists between ''S0, S1, S2, S3 and S30'' and ''0, S1, S2, S3 and S4'' with 5 bits 0-4, i.e., 5 bits higher than the most significant digit within the board for memory address in 2-way and 4-way states respectively. Therefore the constitution is extremely simplified for the address selecting circuit 302.

Description

[Detailed description of the invention] [Technical field of invention] The present invention relates to a memory interleave control method.

In particular, it relates to an interleaving number switching method.

[Technical background of the invention]

Generally, in an information processing system using a memory interleave control method, an address (system address) output from a CPIJ or a device for memory access is transferred to a memory controller via a system bus. The lower bits of the system address are used as bank select information, and the upper bits are used as an intra-bank address. The number of F-order bits of the system path address that is relevant for bank selection is 1, and for example, in 4-way interleaving, it is 2 bits.

In 2-way interleaving, it is 1 bit. This means that there is a 1-bit difference in the address within the puncture between 4-way and 2-way. When switching the number of interleaves in this way, a difference occurs in the bit length of the address within the bank.

For this reason, conventionally, as shown in FIG.
By providing an address selection circuit 11'j91 and changing the address once a month, a memory path for accessing the memory (forming an anchor) (AM array) connected to the memory path is created. Address 12i (i=1:
2-way 1l-XI, 2; 4-way) was generated.

0 (M S 13)
) to bit 31 (L S Ll ) is a 32-bit system path address whose contents are SQ(M
Sll), 81, 82, 83. -828°S 29,
S 30, S 31 (L 813) ” There is.

Here, Sl , (+ ”” Ot 1 g...31
) is the logic ``l++'' or ``0''. The address selection circuit 1 is a selector that selects ``0'' or SQ.

It is composed of a selector for selecting SQ or Sl, a selector for selecting 81 or S2, a selector for selecting S28 or 829, and a selector for selecting S29 or 830.

14 is a 2-way/4-way changeover switch (see below).

By switching 5W14, the output of each selector forming the address selection circuit 1 is switched.

In the example shown in FIG. 1, switching to 2-way interleaving is performed by switching 8W14 to contact a (1111).In other words, when 5W14 is switched to contact a, each selector constituting the address selection circuit 11 80, 81°S2...S29, S, respectively
30 is selected and output. These 8O-830 (31 bits) are the memory path address 12. is output to the memory path as . At this time, 1-bit punk select information 15. As, system path address 13
31 (=831) is used.

In addition, by switching 8W14 to contact b (lIll), switching to 4-way interleaving is performed. In this case, the address selection circuit 11 outputs 0" and 80-
The connection information with 829 is selectively output. In other words, SO~
829 is shifted 1 bit (right) to memory address 1.
2. is output to the memory path as . At this time, 2-pit bank select information 15. As system path address y s (D Gila) 30, 31 (=830.831
) is used.

[Problems with background technology]

As described above, in the conventional system, in order to switch the number of interleaves, a thick bit with a bit length equal to the system path address is required.

This has the disadvantage that the amount of hardware constituting the address selection circuit as an address selection circuit increases.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and its purpose is to:
The number of interleaves can be changed by simply shifting part of the system path address.

An object of the present invention is to provide a memory interleaving control method that can significantly simplify the address selection circuit configuration.

[Summary of the invention]

The present invention provides n-way to n/2-way switching; second, the most significant bit of the internal address on the board when n/2-way is selected; In addition, the memory path address is generated by shifting only the bit position of the system path address that is higher than the bit position that is the most significant bit of the address on the board in the n-way mode. Embodiment of the Invention] An embodiment of the present invention will be described below with reference to the drawings. Note that this embodiment is a system in which 4-way/2-way switching is performed similarly to the conventional example, and the system path address is 32 pits.

This is the case when the system is implemented in which the memory bus address is 31 bits. Also, the top 4 memory path artless
Similarly to the conventional example, the bit is used for board selection, and the F-order 27 bits are used as an address within the board. FIG. z shows the configuration of a memory system to which the present invention is applied. In the text, 20 is the system bus.

30 is a memory controller, 40 is a memory path address information line, and 50, 50, . . . , 50 are memory boards. The number of memory boards 50 in this embodiment is 2+
1 (=32). In a 4-way system, 8 memory boards 50 constitute one memory bank, and in a 2-way system, 16 memory boards 50 constitute one memory bank.

When there is a memory access request from a C P TJ (not shown) etc. connected to the system bus 20, the system path address (So, 81, 82) on the system bus 20 is
．．・ 829, 830゜831'') is the system path address register (J, bottom,
8 AR) 301. 8AR3
SQ to s3 of the held contents of 01 (that is, the upper 4 bits above the bit position that is the most significant bit of the address on the board during 4-way operation as is clear from FIG. 1) and 530 (that is, 5JJ1 As is clear from the figure, 4
830 used as punk selection information when purchasing
, 831) is guided to an address selection circuit 302 having a chic function. 1-bit data of logic nOn is also led to this address selection circuit 302. Address selection circuit 302 is logic “0”
Or with a selector to select SO.

A selector for selecting SO or Sl, and a selector for selecting SO or Sl, and
, a selector that selects S2 or S3, and a selector that selects S3 or 830.
'' selects the former (1 side input), and logic ``0'' selects the latter (0 side input).
It is determined by switching 8W ('2-way 74-way switching unit) 304, which is similar to 5W14 in the figure. In this embodiment, the select signal line 303 is 8W
Logic “1” while 304 is switched to contact C side
During the period when the contact d41111 is switched, the logic becomes "O"'. The address selection circuit 302 selects the first input, that is, 0", 80, 81, 82.83 when the select signal line 303 is at logic "1". Similarly, the address selection circuit 302 selects Q (ll11 input, that is, S
Select o, 81, 82, 83, 830.

When used as a 2-way interleaved memory system, 5W 304 is switched to contact d 4pl.

In this case, since the select signal line 303 becomes logic "O", the address selection circuit 302 outputs 80.81, 82.
, 83, 830 are selectively output. Address selection circuit 3
The selected outputs (80, 81, 82, 83, 830) of 02 are led to an output driver (hereinafter referred to as D) 305.

D305 contains 84-5 of the contents held in 8AR301.
29 (26 bits from bit 4 to bit 29) are also led. D305 is 80, 81, 82, 83, 830 and 8
The connection information with 4 to 829 is sent onto the address information line 40 as a memory path address (at the time of 2-way operation).

Figure 3 shows the structure of the memory bus address during this 2-way operation, with the upper 4 pits (80, 81, 82
, 83) is used for board selection, and the lower 27 bits (830°s4.s5...827,828,829
) is used as the on-board address.

830 (bit 3) of the contents held in S A R301
0) is led to the address selection circuit 302 as described above, and is also led to the 10,000 input terminal of an AND gate (hereinafter referred to as A) 306. The other input terminal of A306 is connected to select signal line 3θ3. Now, the select signal line 303 is at logic 00'' as described above, so the output of A306 is 0''. The output of this 306 is led to each memory board 50, 50, . Also,
831 (bit 31) of the contents held in 8AR301
teeth.

Just go through the punk select line 402.

It is guided to each memory board 50, 5θ, . . . 5o as the lower bit of the puncture select information. In this embodiment when the 2-way operation is performed, the bank select information stored in the memory boards 50, 50, .
will be selected.

Ail sent on address information line 40:11
The memory address is for each memory board 5θ.

50, . . . 50, specifically, the upper 4 bits (So-83) of the memory bus address are sent to the comparator 501 (in the memory board 5o) as board select information via the board select line 403. Guided, lower 27
The pit (830 degrees S4-529) is led to l<AM array 502 (in memory board 50) as an intra-board address via intra-board address line 404.

Furthermore, a 4-bit board address unique to the corresponding memory board 50 is led to the comparator 501 from a board address selection specifying section (hereinafter referred to as BD) 503, such as a switch.

The comparator 501 compares the board select information (So-83) on the board select line 403 with the board address obtained from T3D503, and outputs a match detection signal S of logic "1" when a match is detected. On the other hand, bank select information (0'' on the punk select lines 401 and 402).

531) is routed to a comparator 504 within each memory board 50. This comparator 504 includes a puncture address selection specifying unit (hereinafter referred to as I3K) 50 such as a switch.
A 2-bit puncture address unique to the corresponding memory puncture from 5 is written. The upper 1 bit of this bank address is.

During the 2-way operation, both memory boards 50 are set to 0''. The comparator 504 receives the punk selection information i(
"O", 831) is compared with the bank address given from the BK505, and when a match is detected, a match detection number 41 of logic "1" is output.Each output of the comparators 501 and 504 is an A (AND gate). 506.

A306 outputs a select signal of 1 function "J" when both comparators 501 and 504 detect a match. The memory board 50 starts operating by this select signal.

Note that the memory boards 5θ, 50. . . 50 have the same basic configuration, in FIG. 2 only the components of a specific memory board are illustrated, and the remaining memory boards are omitted.

On the other hand, when used as a 4-way interleaved memory system, the 8W304 is switched to the contact C1111''. In this case, the select signal line 303 becomes logic "1". ”, so, si.

s2 and s3 are selectively output. Therefore, D305
The memory path address at the time of 4 steps sent out on the address information line 40 is 0'' as shown in FIG.
, 80 , 81 , S'2゜S3 and S4~5-29
This is the linked information. In this case, the upper 4 bits as the board select information are °0", sO, sl, s2, and the lower 27 bits as the board address are 83 to S.
It is 29.

As is clear from the above explanation, the memory address for the 4-way operation according to the present embodiment (see Figure 4) is different from the memory address for the 4-way operation in the conventional example (reference numeral 122 in Figure 1).
) It is the same 414-built building. On the other hand, in this embodiment (see Figure 3), the memory address at the time of 2-way operation (see Figure 3) is the same as the memory address at the time of 2-way operation in the conventional example for the upper 4 bits used as board selection information. Although it has the same structure as (121 of the first part), the lower 27 pits used as addresses on the board have a different structure from that of the conventional example.In other words, when two-way, the address on the board is , S4゜s5...828,829,830 in the conventional example, whereas in this embodiment, it is 830,84,85...S2
The total number is 8,829. In other words, during the 2-way operation, S30 is located at the lowest memory path address (address within the puncture) in the conventional example, that is, at the lowest address within the board, whereas in the non-implemented example, S30 is located at the lowest memory path address (address within the puncture). It is located at bit 4 of the intra-bank address, that is, at the most significant position of the intra-board address. In this way, in the non-embodiment, the memory address for each 2-way and 4-way is 5 bits from bit 0 to bit 4, that is, the 5 bits from the top of the address on the board to "80".
,81゜82.83,830j, r"0'", Sl, S
2°83, only different from S4J. Therefore, according to this embodiment, the configuration of the address selection circuit 302 can be significantly simplified (compared to the address selection circuit 11 in FIG. In switching.

Since the bit address 830 that is no longer used as bank select information is used as an intra-board address, it is easy to understand for maintenance purposes.

By the way, in the 4-way mode, the select signal line 303 is at the logic "'1" as described above.
, 306 are in the open state, and 830 is directly connected to the puncture select line 401 (two outputs).Therefore, the bank select information led to the comparator 504 of the memory board 50 is 830 degrees 831 (two is " 0”, S
3], ). The basic operation of the memory board 50 (-) is the same as in the 2-way process, although there are differences in the structure of link select information and memory path addresses. (In case of NIO6, the most significant bit of the board address specified by BD503 must be set to “0”. Also, the most significant bit of the board address specified by BK5 (75) must be
Bit is not necessarily O" unlike 2W and 1%.

It goes without saying that the pit length of the system path address, the bit length of the board select information, etc. are not limited to d8 implementation seconds. Further, in the above embodiment, 4-way #2-way switching has been described, but the present invention can generally be applied to a system requiring n-way #n/2-way switching. In this case, as an address selection circuit, the connection information between one pit data with logical value "0" and the 6B internal address of the board in the n-way in the system path address, the upper f pit at or above the bit position that becomes the upper bit, or Top system path address above! bit and lower m
Any one of the bits (nl is an integer satisfying n=2) and the concatenation information with the upper one bit may be selected. Then, the connection information between the selected output of the address interpretation circuit and the remaining bits of the system path address excluding the above-mentioned upper h pits and lower m bits may be used as a memory path address (address within a puncture).

〔Effect of the invention〕

As described in detail above, according to the present invention, the number of interleaves can be switched by simply shifting a part of the system path address, so that the configuration of the thick address selection circuit can be significantly simplified.

[Brief explanation of the drawing]

The first factor is the conventional interleaving number of 1. Diagram showing the functional configuration for memory path address generation in IJ replacement, Part 2
The figure is a block diagram showing an embodiment of the memory system to which the present invention is applied, FIG. 3 is a diagram showing the structure of the memory path address at the time of 2-way processing in the above embodiment, and FIG. 4 is a diagram showing the structure of the memory path address in the above embodiment. FIG. 4 is a diagram showing the structure of a memory path address in 4-way operation. 30...Memory controller, 50.50...Memory board, 301...System path address register (8AR), 302...Address selection circuit. 304...2-way/4-way changeover switch (3w,
interleaving number switching specification section). 305...Output driver (I)), Applicant's agent Patent attorney Suzue Takehiko no ＼゛shi2pfu? L'sis Figure 2

Claims (1)

[Claims] The logic (
Concatenation information between the 1-bit data of il "i"U" and the j bit with "1" above the bit position that is the most significant bit of the address on the board in n-way in the system path address, or the above system path address (m is an integer that satisfies , = 2m) of the above upper b bits and lower m bits of (m is an integer that satisfies , = 2m); A memory ink league characterized in that the connection information between the selected output of the address selection circuit and the remaining bits excluding the upper bits and the lower m bits of the system bus address is a bus address (1). control method.