JPS62217498A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To reduce the storage capacity of a memory cell for redundancy by allowing >=2 of plural memory cell blocks to share a specific number of columns for redundancy. CONSTITUTION:Columns B1-Bn for redundancy are so provided that they can be connected to at least two of plural memory blocks A1-Am. The columns B1-Bn for redundancy consist of plural memory cells and a memory C is stored with information I1 on an address corresponding to a defective column and information I2 on the memory cell block where the defective column is present. In this method, the storage capacity as redundancy decreases as compared with when one array of columns for redundancy are provided for each memory cell block and, for example, when up to two columns are retrieved by two memory cell blocks, the former is 16K bits and the latter is 32K bits.

Description

[Detailed Description of the Invention] [Summary] A semiconductor memory device in which at least two of a plurality of memory cell blocks (A+ to Ai) share a predetermined number of redundant columns CBt to Bfi). By configuring to do so, it is possible to reduce the memory capacity of the redundant memory cell, thereby reducing the chip area and manufacturing cost.

[Industrial application field]

The present invention relates to a semiconductor memory device, and more particularly, the present invention relates to a semiconductor memory device that has a memory cell block and a redundancy column, and when the memory cell block includes a defective column, when address information corresponding to the defective column is input, The present invention relates to a semiconductor memory device in which a redundant column is activated in place of a defective column.

The device according to the present invention can be used, for example, in the section 1a of information equipment such as a computer that requires high reliability.

[Conventional technology]

FIG. 5 shows the correspondence between memory cell blocks and redundant columns or redundant memory cell blocks in the conventional semiconductor memory device with redundancy described above.

FIG. 5(a) shows a case where the storage capacity 1256 has a 1-bit configuration, where one chip consists of four memory cell blocks a, ~a14, and each memory cell block has 512 bits.
Consists of 128 bit columns, corresponding to each memory cell block, and redundant column bII+b+□+
One row of b+3+b+4 is provided. In this case, the redundancy value is 2 bits. If each memory cell block all to a14 includes a defective column, when the address corresponding to the defective column is specified, the defective column is switched to the redundant column bll to b14 as shown by the broken line. .

FIG. 5(b) shows a case where the storage capacity 256 has an 8-bit configuration, in which one chip consists of four memory cell blocks all to a24, and each memory cell block consists of eight memory cell blocks a211. 〜a2,8, each memory cell block a211''a
218 is composed of 5]2 pins x 16 columns, with redundant column b2 corresponding to each memory cell block.
1. bZ□,..., b2. are provided in each column. In this case, the storage capacity for redundancy is 16 bits. When each memory cell block a211 to a2+11 includes a defective column, the redundant column 1, bit to b28 is
can be switched to

FIG. 5(C) shows the case of an 8-bit component with a capacity of 256 bits in 1a, where the l chip consists of four memory cell blocks 231 to a34, and each memory cell block corresponds to eight Ilo. It consists of eight memory cell blocks a3.1 to 8318 and one redundant memory cell block b31, and each memory cell block has five
It consists of 12 bits x 16 columns. in this case,
The storage capacity for redundancy is 32 bits. If each of the memory cell blocks 831 to a34 includes a memory cell block (a3□) including a defective column, the defective memory cell block aff11 is previously set to redundant memory as shown by the thick arrow. cell block b3
1 and used as an 8-bit component.

[Problem that the invention seeks to solve]

In the above-mentioned conventional technology, in addition to the original storage capacity of 256 bit memory cells, in order to rescue 1 bit, a redundant portion is used for 1 bit per 2 in the case of (a), and 16 bits in the case of (b). In the case of <c>, 32 bits worth of memory cells are required, which increases the chip area and raises the manufacturing cost. This problem becomes even more pronounced when the number of bits to be rescued increases, since the storage capacity of the redundant memory cells also increases accordingly.

SUMMARY OF THE INVENTION In view of the problems in the prior art described above, an object of the present invention is to provide a semiconductor memory device that can reduce the memory capacity of redundant memory cells, reduce the chip area, and reduce manufacturing costs. It is in.

[Means for solving problems]

FIG. 1 shows a principle block diagram of a semiconductor memory device according to the present invention.

In FIG. 1, A1 to Al11 are a plurality of memory cell blocks, and each of the memory cell blocks is constituted by columns each consisting of a plurality of memory cells arranged in an array. 81 to B7 are a predetermined number of redundant columns, and the redundant columns B1 to B0 are provided so as to be connectable to at least two meheri cell blocks A1 to 80, and each redundant column is Consists of multiple memory cells.

C is a memory, and the memory C contains first information @rl representing the address corresponding to the defective column in which the defective memory cell exists, and information on which of the memory cell blocks A1 to AII the defective column is located. The second information r2 indicating whether the information is included is predetermined by α. D is a determination circuit which inputs address information ADD that simultaneously specifies the corresponding columns of each of the memory cell blocks A, ~A1, and this address information
T.

It has a function to determine whether it matches or not. E
is a control circuit that detects a memory cell block containing a defective column based on second information 2 in memory C when address information ADD matches first information 11;
It has a function of making the memory cell block inactive and making any of the redundant columns B and B7 active.

Therefore, the apparatus of the present invention as a whole is configured such that at least two of the plurality of mesh cell blocks A1-80 share a predetermined number of redundant columns B1-B.

[For production]

In the semiconductor memory device according to the present invention, the input address information ADD is the address information (
A determination circuit determines whether the information matches the first information r+), and when these pieces of information match, the control circuit E identifies the defective column based on the second information I2 in the memory C. The memory cell block containing the memory cell block is made inactive, and at the same time redundant columns B1 to B, l are installed in place of the defective column.
Make one of them active.

The above-described switching from a defective column to a redundant column is performed between at least two memory cell blocks and a predetermined number of redundant columns shared by the memory cell blocks.

This allows the device of the present invention to
By reducing the a capacitance, it is possible to reduce the chip area and manufacturing cost.

〔Example〕

FIG. 2 shows a semiconductor diagram 1 as an embodiment of the present invention. A device is shown in block form, and FIG. 3 shows the correspondence between memory cell blocks and redundant columns in the device of FIG. 2.

As shown in FIG. 3, the memory storage capacity of the device of this embodiment is 256 bits, and one chip has four memory cell blocks A1° and Az. ,A. .

Each memory cell block is composed of eight memory cell blocks A1 to A8. Each memory cell block A, -A is composed of 512 bits x 16 columns. Furthermore, two redundant columns B and B2 are provided corresponding to memory cell blocks A and A2.
Similarly, two redundant columns are provided corresponding to two memory cell blocks. In this case, the redundant storage capacity is 16
It is K bits (512 bits x 8 x 4).

To simplify the explanation, only two memory cell blocks A1 and A2 and two redundant columns B and B2 are shown in the 21st column 1. In Figure 2, C is address FROM (programmable read-only memo January 01 and ■10 (input/output)
This memory consists of PROMCz. PR for address
In OMC+, each memory cell block A, , A2
Address information (1) indicating in which column of the 16 columns a defective memory cell is present is stored in advance. Therefore, in this case, address information 1. is O~1
The unit is 4-bit information representing one of the 5 addresses,
It is sent as 8-bit information for two column addresses.

In addition, in the T10 PROM C2, information indicating which memory cell block At, Az includes a defective column containing a defective memory cell, in other words, it indicates which 110 channel it corresponds to. I10 information ■2 is stored in advance.

A determination circuit and a control circuit E are connected to the memory C. The determination circuit includes memory cell block A1. Address information ADD that simultaneously specifies each corresponding column of A2
is input, and when the determination circuit enters, this address information ADD is the 7 address information 1. from memory C. II+determination is performed to determine whether or not they match. On the other hand, fliII control circuit E
When the address information ADD matches the address information 1 based on the judgment result according to the judgment Ii'i'l path, the memory indicating the defective address block receives either the defective address match signal B13 or B2S. Based on the T10 information 12 from C, appropriate high level control signals E1 to B4 are output. As a result, the memory cell block A1 or A2 including the defective column becomes inactive, and at the same time, the redundant column B or B2 becomes active.

The 4-bit address information ADD is sent to column decoders CDI, CD, and corresponding to each memory cell block AI and A2.
is also entered. Column decoder Cr), CD2
are each composed of 16 field-effect transistors T. -T
I5, and the source terminals of the transistors are connected to the respective gate terminals of memory cell blocks A1. In A2, the train end f" is 110 buffers I OB+ , I OB
Connected to 2. That is, column decoder CD,
, when the address NADD is decoded in CD2,
The transistor corresponding to the decoded address is turned on, and the memory cells of the column connected to the transistor are connected to I10, IOB, IOB, and IOB.

Column decoders CDI and CD are each
Connected to the output terminals of N0RI and N0Rz.

The controller I is connected to one input terminal of the NOR gate NOR+.
A control signal E from SE is input, a control signal E3 is input to the other input terminal, and NOKATE N0R2
The control signal E2 is inputted to one input terminal of the , and the control signal E4 is inputted to the other input terminal. Noah game) NOR,,N.

When a high-level signal is input to at least one input terminal of R2, the output of NOAKATE becomes low-level, thereby causing the column decoder CD.

CD2 stops functioning and becomes memory cell block AH.

A2 becomes inactive.

Control signals E +, E Z, E 3 from control circuit E
．． E4 are field effect transistors t1~
It is designed to be input to each gate terminal of t4. The source terminals of transistors t1 and t2 are connected to redundancy column B1, the source terminal of transistor "3+"4 is connected to redundancy column B2, and transistor tI
The drain terminal of +t3 is T10 buffer I OB +
, the drain terminal of transistor “Zr”4 is I10
It is connected to the buffer IOB. Therefore, for example, when control signal E is output, transistor t is turned on, and redundancy column B and I10 buffer IOB+ are connected. At this time, since the output of NORI is at a low level, the memory cell block A1 becomes inactive.

FIG. 4 is a schematic diagram illustrating switching to a redundant column when up to two columns are to be rescued using the apparatus shown in FIG. 2.

(1) Case of FIG. 4(a) In this case, defective memory cells exist in the 3rd column and the 10th column G of the memory cell block AI. Therefore, the determination circuit determines that the address information ADD matches the address information ■1 only when the address information ADD includes information representing address 3 or 10, and in each case, Redundant column B +,
Match signal B13.8 indicating that it should be replaced with B2
Sends 2S.

In response to this determination, the control circuit E determines the memory cell block A1 containing the defective column based on the I10 information @Ig, and sends control signals E, ,E, for replacing the defective column with a redundant column.
Output. As a result, the output of the NOR gate NORI becomes low level, the memory cell block A becomes inactive, and at the same time, the transistors tI+t3 turn on, so the columns B and B2 become the I10 buffer IO.
Connected to B+ and becomes active.

(2) Case of FIG. 4(b) In this case, the defective memory cell exists in the 8th column of each of the memory self-locks A, A2.

Therefore, the determination circuit determines that the address information IIAD
It is determined that D matches address information 11, and match signals B15°B2s are sent out at the same time. The control circuit E uses this determination and the T10 from the I10 PROM C2.
Control signals El, E4 (or E2, E3) for determining memory cell blocks containing defective columns as A and A2 based on information 2 and replacing them with redundant columns.
Output. With this, Noah game) NOR+.

The outputs of N0R2 both become low level, memory cell blocks A+ and Az both become inactive, and at the same time transistors tI+t4 (or tZ+t3) are turned on, so redundant columns B+ and Bt are connected to r10 buffers IOB+ and l0Bz, respectively. becomes active.

Note that in the case where there are defects in columns with different addresses in memory cell blocks A, A2, the sending of the match signal BIS+B23 is the same as in case (1), and the transmission of the match signal BIS+B23 is the same as in case (1). Selection (activation) of redundant columns B, Bffi by driving is (2)
Since this is similar to the case of , detailed explanation will be omitted.

As explained above, according to the apparatus shown in FIG.
Since two redundant columns (storage capacity 16 bits) are associated with each memory cell block, and up to two columns can be repaired, the conventional type (Fig. 5) is used to repair the same two columns. In case b), the storage capacity of the redundant memory cell can be reduced compared to (the redundancy divided by the storage capacity divided by 32 bits). This makes it possible to reduce the chip area and reduce the manufacturing cost, and when the area of the chip to be manufactured is constant, there is ample space, making manufacturing easier.

〔Effect of the invention〕

As explained above, according to the present invention, redundant memory cell description 1. By reducing the a capacitance, the chip area and manufacturing cost can be reduced.

[Brief explanation of drawings]

FIG. 1 is a principle block diagram of a semiconductor memory device according to the present invention, FIG. 2 is a block diagram showing an embodiment of the present invention, and FIG. 3 is a diagram showing a memory cell block and a redundant column in the device shown in FIG. Figure 4 is a schematic diagram illustrating switching to the redundant column when saving up to 2 bits using the device shown in Figure 2. Figure 5 is a diagram showing the conventional memory FIG. 3 is a diagram showing the correspondence between cell blocks and redundant memory cells. A1 to AII...memory cell block, B, -B, l
... Redundancy column, C... Memory, D... Judgment circuit, E... Control circuit, II... First information (
address information), 12...second information (I10 information)
, ADD...address information.

Claims (1)

[Scope of Claims] A plurality of memory cell blocks (A_1 to A_m), each of which has a plurality of columns each consisting of a plurality of memory cells arranged in an array; and at least two columns. The memory cell block (A_1 to A_
A predetermined number of redundant columns (B
_1 to B_n), each of which has a plurality of memory cells, and first information (I_1) representing an address corresponding to a defective column in which a defective memory cell exists. A memory (C) in which second information (I_2) indicating which of the memory cell blocks (A_1 to A_m) the defective column is included in is stored in advance; ) a circuit (D) that inputs address information (ADD) that simultaneously specifies each corresponding column of the column and determines whether or not the address information matches the first information (I_1) in the memory; , When the address information (ADD) matches the first information (I_1), the memory cell block including the defective column is made inactive based on the second information (I_2) in the memory, and the redundant column is A semiconductor memory device comprising: a control circuit (E) that activates any one of columns (B_1 to B_n).