JPS596556B2 - Channel memory control method in time division switching equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a communication path memory control system in a time division switching system that allows reading and writing of data from an external control device, such as a processor, without using the communication path.

The configuration of a conventional channel memory device is shown in FIG.

In Figure 1, SPM is a communication path memory, HM is a communication path specification memory, IHW is an incoming highway, OHW is an outgoing highway, 5EL0-2 are selection circuits, LAT0-2 are latch circuits, COUNT is a counter circuit, and DEC is a decoder. circuit, TIM is a timing generation circuit, ADD is an addition circuit, DI is an input data line, DO is an output data line, ADA,
ADB is an address line, and CONT is a read/write control circuit. FIG. 2 is a time allocation diagram for explaining the operation of FIG. 1, where TSPM indicates the time allocation for the communication path memory SPM, W is the write allocation time from the incoming highway IHW, and R is the data allocation to the outgoing highway 0HW. The allotted time for reading information, T, indicates the allotted time for reading and writing data information from an external control device, such as a processor, not shown in FIG. Note that FIG. 2 does not show detailed timing but a rough time allocation. To simplify the explanation, for convenience, the data information on the entry/exit highway is 8KH.
It is assumed that an 8-bit PCM signal sample-encoded every two periods, that is, every 125 μs, is multiplexed into 64 channels and transmitted in parallel in synchronization with the clock of the channel memory device.

Therefore, it is assumed that the communication path memory SPM has a 64-word, 8-bit configuration, and the communication path designation memory HM has a 64-word, 6-bit configuration. In addition, in Fig. 2, T1 to T192 are 125μ
This is a convenient name assigned to each time by dividing S into 192 times. First, considering the case where data information of channel o on the incoming highway IHW is written to the speech path memory SPM, at time T2 in FIG. 2, the 8-bit data information of channel o from the incoming highway IHW is selected by the selection circuit SELO. , is input to the communication path memory SPM as write information. Similarly, at the time of T2, the selection circuit SELI
As a result, the output data of the counter circuit COUNT is selected and input as address information to the speech path memory SPM. Also, at the time of T2, the read/write control circuit CO
A memory write signal is issued from NT to speech path memory SPM, so that as a result, 8-bit data information of channel o is written to the address represented by the output data of counter circuit COUNT. Similarly, data information of channel 1 is written at time T5 to the address represented by the output data of the counter circuit COUNT at that time. Thereafter, data information up to channel 63 is similarly written to the 64-word speech path memory SMP within a period of 125 μs.

Next, considering the case where data information is sent to channel 0 on outbound highway 0HW, the output data of latch circuit LAT2 is selected by selection circuit SELl at time Tl92, inputted to speech path memory SPM as address information, and read out at the same time. A memory read signal is output from the write control circuit CONT to the speech path memory SPM, and 8-bit data information is read out.

The read data information is latched by the latch circuit LATO, and the data information is output to the channel O of the outgoing highway 0HW. The output data of the latch circuit LAT2, which is the read address of the speech path memory SPM, is Tl9.
This is 6-bit data information read from the channel designation memory HM at a predetermined time point before 2 and written from the external control device. For example, when sending data on channel 4 of the incoming highway IHW to channel O of the outgoing highway 0HW, 6-bit data representing the address channel 4 of channel O in the communication route designation memory HM, for example 000100, is written. . This 6-bit data is read from the channel designation memory HM in the first half of channel 63, but at this point, the 6-bit output data of the counter circuit COUNT corresponds to channel 63, so the adder circuit ADD reads out the channel designation memory HM. It is converted into 6-bit data corresponding to O. Note that the selection circuit SEL2 receives the address line ADA from the external control device.
At a predetermined timing, either the address information for writing in the communication path designation memory HM sent via the address information for writing in the communication path designation memory HM or the output data of the counter circuit COUNT converted by the adder circuit ADD is selected at a predetermined timing, and is written as the address information of the communication path designation memory HM. It has an input function.

Further, write data to be written from the external control device to the communication path designation memory HM is input from the input data line DI. Next, considering the case where data is written to or read from the communication path memory SPM from the external control device, the address information of the communication path memory SPM is sent from the external control device via the address line ADA, and the selection circuit SEL1 selects the address information of the communication path memory SPM. In FIG. 2, it is selected at the time Tl, T4, . At the same time, during writing, write data is sent from the external control device via the input data line D, and the selection circuit SELO causes Tl in FIG.
, T4, T7, . . . , at the time of Tl9O, and inputted to the speech path memory SPM as write data information. On the other hand, reading is also performed at the same time as above,
The read data is sent to the output data line D by the external control device.
latch circuit LAT for sufficient time to read through O
It is latched with l.

Note that the address line ADA and the input data line DI are also used when writing to the communication path designation memory HM, so another address line ADB is used to write or read the communication path memory SPM or write to the communication path designation memory HM. There is a decoding circuit DEC that identifies the Here, the communication path memory SPM when there is no data information writing or reading from the external control device to the communication path memory SPM
Figure 3 shows the time allocation. That is, in FIG. 3, W is the path from the incoming highway IHW to the communication path memory SPM.
R is the read allocation time for sending data from the communication path memory SPM to the outbound highway 0HW, and compared to FIG. 2, the allocation time is 1.5 times longer. That is, in the conventional method, the time allocation given to reading and writing to the channel memory SPM is 2/3 of that when there is no reading and writing from the external control device, and the demands on the memory access time and cycle time are correspondingly stricter. There is a drawback that channel multiplicity must be lowered in order to use faster, ie, more expensive, memory, or to increase time allocation to memory.

The present invention has been made in view of the above-mentioned drawbacks found in the conventional devices.The present invention divides the communication path memory into two and shifts the time allocation for writing and reading to each communication path memory. By reading and writing from the external control device to the other communication path memory at the time of writing from the input highway to the communication path memory or the time of reading from the output highway, the above-mentioned drawbacks can be eliminated and the external control device The purpose is to construct a communication path memory device with the same multiplicity using a memory of the same speed and capacity as in the case where there is no function of reading and writing to the communication path memory.

The invention will now be explained in detail with reference to the drawings. FIG. 4 shows an embodiment of the present invention, in which SPMO, SP
Ml is call path memory, HM is call path designation memory, IHW
is the incoming highway, 0HW is the outgoing highway, SELO~
6 is a selection circuit, LATO~2 is a latch circuit, COUNT
is a counter circuit, DEC is a decoder circuit, TIM is a timing generation circuit, ADD is an adder circuit, DI is an input data line, DO is an output data line, ADA and ADB are address lines, and CONT is a read/write control circuit.

FIG. 5 is a time allocation diagram for explaining the operation of FIG.
It is assumed that an 8-bit PCM signal sampled and encoded every 25 μs is multiplexed into 64 channels and transmitted in parallel on the ingress/egress highway in synchronization with the clock of the channel memory device. It is not limited to the conditions of

In FIG. 5, T1 to Tl28 are convenient names assigned to each time by dividing one period of 125 μs into 128,
TSPMO indicates the time allocation for the communication path memory SPMO, TSPMl indicates the time allocation for the communication path memory SPML, W is the allocation time for writing from the inbound highway IHW, R is the allocation time for reading data information from the outbound highway 0HW, and T is the allocation time for the readout of data information from the outbound highway 0HW. 4 shows the allocated time for reading and writing data information from an external control device (not shown), such as a processor. In addition, the fifth
The figure does not show detailed timing, but a rough time allocation. In FIG. 4, the channel memories SPMO and SPMl each have a 32-word, 8-bit configuration, and the channel designation memory HM has a 64-word, 6-bit structure.
It has a bit configuration.

First, when writing data information on the incoming highway IHW to the speech path memories SPMO and SPMl, considering channel O, at the time T1 in FIG.
8-bit data information of channel 0 is selected from the incoming highway IHW by O, and is input as write data to the speech path memory SPMO. Similarly, at time T1, the output data of the counter circuit COUNT is selected by the selection circuit SEL1, and the upper 5 bits of the 6 bits are inputted to the speech path memory SPMO as address information. Also, at the time of T1, the read/write control circuit CONT
A memory write signal is issued from the channel memory SPMO to the channel memory SPMO, and the 8-bit data information of channel 0 is written to the address represented by the upper 5 bits of the 6 bits of output data of the counter circuit COUNT. Next, in the case of channel 1, the selection circuit SEL is activated at time T3 in FIG.
2, the 8-bit data information of channel 1 is selected from the incoming highway IHW and inputted as write data to the speech path memory SPML. Also at T3,
The output data of the counter circuit COUNT is selected by the selection circuit SEL3, and the upper 5 bits of the 6 bits are inputted to the speech path memory SPMI as address information. Also, at time T3, a memory write signal is issued from the read/write control circuit CONT to the channel memory SPM1, and the 8-bit data information of channel 1 is written to the address represented by the upper 5 bits of the 6 bits of output data of the counter circuit COUNT. written to. Similarly, the even channels, ie channel 2, channel 4
, channels 62 are T5, T9, etc., respectively.
At time Tl25, the 32-word memory of the channel memory SPMO is written, and the odd channels, namely channel 3, channel 5, . . . , channel 63, are written at time T7, Tll, . ,
It is written to the 32 word memory of the channel memory SPM1.

The switching of the write channel memories SPMO and SPM1 corresponding to even channels and odd channels is controlled by the read/write control circuit CONT identifying the least significant bit of the counter circuit COUNT. Next, when data information is read from the speech path memories SPMO and SPMl in order to send it out on the highway 0HW, taking as an example the case where data information of channel n is first sent to channel O, the channel of the communication path designation memory HM is 6-bit information representing channel n at the address corresponding to 0;
For example, if n is 4, 000100 is written in advance by the external control device. This communication route designation memory HM
The 6-bit information representing channel n written in
It is read out from the communication path designation memory HM at a time before Tl28 of the channel 63 and latched in the latch circuit LAT2. If channel n is an even channel, at time Tl28, the selection circuit SELl selects
The output data of the latch circuit LAT2 is selected, and the upper 5 bits out of 6 bits are inputted to the speech path memory SPMO as address information. If channel n is an odd channel, the output data of the latch circuit LAT2 is selected by the selection circuit SEL3 at time Tl28, and the output data of the latch circuit LAT2 is selected.
Among the bits, the upper 5 bits are stored in the communication path memory SPML.
is input as address data. In addition, at Tl28, the read/write control circuit CONT sends the channel n
If is an even channel, to the communication path memory SPMO,
If the channel n is an odd channel, a read signal is given to the speech path memory SPMI, and as a result, 8-bit data information is read from the corresponding address of the speech path memory SPMO or SPMl, and the selection circuit SEL5 selects the speech path. Either of the outputs of memories SPMO and SPMl, that is, if it is an even channel, the communication path memory SPM
O, if the channel is an odd numbered channel, the output of the speech path memory SPM1 is selected and outputted to the outgoing highway 0HW at the time of channel O by the latch circuit LATO. The case of channel O has been explained above, but for other channels, data information is similarly read from the speech path memory SPMO or SPMI from the time of the previous channel.
The data output is selected by the selection circuit SEL5, latched by the latch circuit LATO, and sent to the outgoing highway 0HW at the time of the corresponding channel. This channel memory SP
Reading data information from MO or SPM1 is performed in the fifth step.
In the figure, time point R, that is, T2, T4...T
However, since the actual read data is output across the corresponding channels due to the delay due to the access time, it can be latched by the latch circuit LATO.
Note that the selection circuit SEL5 is controlled by the read/write control circuit CONT. In addition, in FIG. 4, the adder circuit ADD is a circuit for converting the channel number indicated by the output data of the counter circuit COUNT into address information to be read from the communication path designation memory HM, as explained in the conventional method. For example, counter circuit COU
When the output data of NT is channel 63, the address of channel O must be read from the communication path designation memory HM, so 1 is added by the adder circuit ADD.

Further, in FIG. 4, the selection circuit SEL4 is connected to the communication path designation memory H sent from the external control device via the address line ADA.
It has a function of selecting either the write address information of M or the output data of the counter circuit COUNT converted by the adder circuit ADD at a predetermined timing and inputting it as an address signal of the communication path designation memory HM.

Note that write data to be written from the external control device to the communication path designation memory HM is input from the input data line DI.

Next, from the external control device, the communication path memory SPMO or SP
Considering the case of writing to the Ml header or reading data, first, 6 bits of address information are sent from the external control device via the address line ADA, and the selection circuit SEL1 or SEL3 selects T in FIG.
, i.e., the channel memory SP
It is selected at the time of T3, T7...Tl27 in MO, and Tl, T5,...Tl25 in the speech path memory SPML, and the 6-bit data is sent to the speech path memory SPMO or SPMl as address information. Of these, the upper 5 bits are input.

In addition, in the case of writing, write data is sent from the external control device via the input data line DI, and is selected by the selection circuit SELO or SEL2 at the time point also assigned as T in FIG. road memory SP
It is input as write data to MO or SPM1.
It is all up to the read/write control circuit C to input the address information and data information mentioned above into the communication path memory SPMO or SPMl and output the read signal write signal.
Controlled by the ONT, the communication path memories SPMO and SPMI are selected depending on whether the 6-bit information sent from the external control device via the address line ADA specifies an even channel or an odd channel. On the other hand, the data information read from the speech path memory SPMO or SPMl is selected by the selection circuit SEL6 under the control of the read/write control circuit CONT, latched by the latch circuit LATl, and sent back to the external control device by the output data line DO. be done. Note that the decoder circuit DEC determines whether the address information and data information sent from the external control device via the address line ADA and the input data line DI are for reading or writing into the speech path memories SPMO and SPMl, or whether the address information and data information sent from the external control device via the address line ADA and input data line DI are for reading or writing, This is used to distinguish whether the address line ADB is used for writing to the address line ADB, and serves to expand the information on the address line ADB and pass control to the read/write control circuit CONT.

Comparing Figure 4 and Figure 1, the amount of channel memory is the same, and comparing Figure 5 and Figure 3, the time allocated to reading and writing the channel memory is the same. It turns out that. Although a detailed explanation will be omitted since it is not directly related to the present invention, when data information is read from or written to the communication path memory from an external control device, it is necessary to write data information from the incoming highway to the communication path memory. It is desirable to be able to prohibit each channel; for example, one
One method is to add a bit to control the writing of data information from the inbound highway to the channel memory. As explained above, in this embodiment, the communication path memory is divided into two parts, data information from the incoming highway is written into the two divided communication path memories alternately, and data information entering from the highway is written into one of the communication path memories. By allocating time to read and write data information from the external control device to the other communication path memory during the time when the other communication path memory is being used, the operating speed required for the communication path memory is not made too strict. To enable reading and writing of a communication path memory from an external control device without increasing the total amount of communication path memory and without reducing channel multiplicity.

In this embodiment, in order to compare with the conventional method, data information from the incoming highway is written to a fixed address in the communication path memory under the control of a counter circuit, and when reading data information to the outgoing highway, the data information from the incoming highway is written to a fixed address in the communication path designation memory. Although a so-called cyclic write and random read system communication path memory device has been described in which data information is read from an arbitrary address in the communication path memory, the present invention is not limited thereto, and is applicable to random write and cyclic read methods. In the case of the read method, during the time when reading from one channel memory to the outbound highway is being carried out,
By allocating time to read and write data information from an external control device to the other communication path memory, the same effect as this embodiment can be achieved, and a random write, cyclic read type communication path memory can be obtained. It is also applicable to devices. As explained above, according to the present invention, the call route memo J is divided into two parts, the time allocation for reading and writing to each call route memory is shifted, and the writing of data information from the incoming highway to one of the call route memories is delayed. Since the configuration is configured such that data information is read from or written from the external control device to the other communication path memory at the same time as the data information is read from the outgoing highway, the operating speed required of the communication path memory can be controlled. There is an advantage that reading and writing of the communication path memory from an external control device can be performed without making the communication path memory difficult, without increasing the overall amount of the communication path memory, and without reducing the channel multiplicity.

[BRIEF DESCRIPTION OF THE DRAWINGS] The drawings are provided to explain the present invention. FIG. 1 is a block diagram of a communication path memory device in a conventional time division switch, and FIG. 2 shows the time allocation of the device shown in FIG. 1. FIG. 3 is a diagram showing time allocation when there is no writing or reading of data from an external control device to the communication path memory, and FIG. 4 is a communication path memory in a time division switch showing an embodiment of the present invention. FIG. 5 is a diagram showing the configuration of the equipment, and is a diagram showing time allocation of the apparatus shown in FIG. 4. SPM, SPMO, SPMl...Call path memory, HM...Call path designation memory, IHW...
...Inbound highway, 0HW...Outbound highway, DI...Input data line, DO...Output data line, ADA, ADB...Address line,
SELO~SEL6...Selection circuit, LATO~
LAT2...Latch circuit, COUNT...
...Counter circuit, ADD... Addition circuit, DE
C: decoder circuit, TIM: timing generation circuit, CONT: read/write control circuit.

Claims (1)

[Claims] 1. In a call path memory device in a time division exchange that allows data information to be read and written by an external control device such as a processor without going through the call path, the call path memory is divided into two, and reading from each call path memory is performed. The writing time allocation is shifted so that at the time when data information is written from the incoming highway to one channel memory or when the data information is read from the outgoing highway, data is written to the other channel memory from the external control device. 1. A communication channel memory control system in a time division switch, characterized in that data information is read or written.