JPS596411B2 - Channel data transfer control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for controlling data transfer from a data buffer to a main memory in a channel having a data buffer.

In general, a channel having a data buffer for temporarily storing and buffering data transferred between a main memory and an input/output device is already well known. The time required to transfer the write data to the device, and the time required for the main memory to be activated for access from the channel side, and a series of steps including checking for address errors and data errors, etc. When comparing the time required to complete a memory operation (hereinafter referred to as an MS operation cycle), that is, the MS operation cycle time, the latter is usually considerably longer than the former.

By the way, there is a basic processing unit (hereinafter abbreviated as BPU) that shares a main memory with the channel, and there is a system in which the channel shares a control microprogram with the BPU. In such cases, BPU
When the BPU executes a microprogram and performs a processing operation, the channel steals the program and performs data transfer to the main memory (during this time, the processing operation remains suspended and does not proceed in the BPU), After that, the program is returned to the original stolen BPU, and the BPU
Then, the processing operation will be restarted. of this channel,
In a data transfer operation to the main memory by a program stolen from the BPU side, the MS operation cycle of the main memory, which is activated and starts operating at the same time as the start of this transfer operation, is completed and data errors etc. occur. A method (hereinafter referred to as
In the case of a control system (sometimes referred to as a control system), BP
If a data error or the like is detected in the MS operation cycle after the processing operation is restarted on the U side, the processing operation on the BPU side shifts to channel transfer operation control by stealing again (this is called stealing level recovery). ), collect fault information, and perform other abnormal handling operations. This conventional method has the disadvantage that when a data error or the like is detected during an MS operation cycle, control for abnormality processing such as recovery of the steal level and collection of fault information becomes too complex. On the other hand, in order to simplify the control for handling abnormalities, the data transfer operation to the main memory of the channel started by stealing is terminated until the MS operation cycle is completed and it is confirmed that there are no data errors. If a method is adopted in which data transfer is not performed, data transfer will take more time than necessary, resulting in a reduction in throughput between the channel and the main storage device.
This invention has been made to overcome the drawbacks of the prior art as described above, and therefore, the object of this invention is to
When a data error or the like is detected in the S operation cycle, there is no need for complicated abnormality handling control that would be required if a stand-by control method is adopted, and moreover, the throughput from the channel to the main storage device is reduced. An object of the present invention is to provide a channel data transfer control method that can improve the channel data transfer.

The main points of the structure of this invention are as follows.

Data transfer using a channel having a data buffer for temporarily storing and buffering data transferred between a host storage device and an input/output device is generally performed as follows. For example, assume that 100 bytes of data are to be transferred from the input/output device to the main storage device. At this time, transfer from the input/output device to the data buffer in the channel is performed in units of 1 byte. On the other hand, data transfer from the data buffer to the main memory is performed in units of 8 bytes (actually, since the bus has a capacity of only 4 bytes, the data is transferred in two batches of 4 bytes each). By the way, when the memory contents in the main storage device are rewritten in 8-byte units using data sent from the data buffer in 8-byte units, this is called a full write. On the other hand, instead of rewriting all 8 bytes of data in the main memory, some of the bytes may be data that has already been stored in the main memory, and only the remaining data is the data transferred from the data buffer. In some cases, the calligrapher can write the calligrapher's work, and this is called partial writing. When performing a partial write, the storage device first reads the 8 bytes of data from the memory into a register, performs an error check, and then rewrites only the required bytes with the data transferred from the channel. , and then writes it again from the register to memory in the form of 8 bytes. By the way, we assumed that 100 bytes of data were transferred from the input/output device to the main memory, but in this series of data transfer operations, only the first and last accesses from the channel (data buffer) to the main memory are performed. However, there is a strong possibility that the above-mentioned partial write operation will be performed, and the intermediate access will be a full write operation. The reason for this is that in the first access, depending on the starting address specified from the channel to the main memory, if the starting address specifies the middle of an 8-byte memory partition on the main storage side, a partial This is because it is a write operation. Also, in the final access, depending on the amount of transferred data (100 bytes in the current example) and the specified location of the start address in the first access, the final data may not be exactly 8 bytes; This is because it is often less than In intermediate accesses, 8-byte buffering is performed in the data buffer of the channel, so all data is necessarily written. Now, in the case of a partial write, as mentioned above, the main memory side reads 8 bytes of data into a register and checks for data errors, but in the case of a full write, all 8 bytes are Since the data is rewritten, there is no need to read it to a register and check for errors as in the case of partial writing.

This invention focuses on this point, and when data transfer from a channel to main memory leads to a partial write of data to the main memory (in most cases, the first and last access), the partial write At this time, a data error check is performed, so in the sense of waiting for the check result to be determined, the data transfer control operation in the channel is not terminated until the end of the MS operation cycle, and on the other hand, if it leads to all write operations. Since no data check is performed during all writes, there is no need to wait for the end of the MS operation cycle, and the data transfer control operation in the channel ends immediately after the data transfer from the channel to the main memory device is completed. , the key point of the present invention is that the process is shifted to restarting the processing operation of the BPU. Next, one embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

Please refer to FIG. Channel 2 and BPU 3 share main memory 4. The channel 2 includes a data buffer 8, a data transfer control logic circuit 7, a partial write operation detection logic circuit 6', and a microprogram/decode logic circuit 5.
The BPU 3 includes a t1 AND circuit A, an interface control logic circuit 9 with the main memory 4, a sequence control logic circuit 10, a sequence inhibition logic circuit 11,
It comprises a control memory 12 and a microprogram decode logic circuit 13. Note that the microprogram stored in the control storage device 12 is shared by the BPU 3 and the channel 2, and while the BPU 3 is reading out the microprogram and executing the control operation, the channel 2 can steal the program as necessary. A method is adopted in which the BPU executes the control operation (during which the BPU stops the control operation) and resumes the control operation upon completion of the control operation. Data is transferred from the input/output device 1 to the main memory 4 via the data buffer 8 in the channel 2 and through the interface control logic circuit 9 in the BPU 3. Next, the operation in the above configuration will be explained.

When data is transferred from input/output device 1 to main storage device 4 via channel 2, the data is sent from input/output device 1 to channel 2 in 1-byte units, and the sent data is transferred to channel 2 under data transfer control. The data is buffered into a data buffer 8 under the control of the logic circuit 7.
When 8 bytes of data accumulates in the buffer 8, the data transfer control logic circuit 7 sends a steal request signal to the sequence control logic circuit 10 in the BPU 3, and when it is accepted, the latter sends a steal acceptance signal to the former, and the channel 2 steals the control program from the BPU 3 and starts the control operation.

That is, the sequence control logic circuit 1 in the BPU 3
0, a control storage device 12 that stores a microprogram;
By the operation of the micro program/decode logic circuit 13, the micro program/decode logic circuit 5 in channel 2, etc., channel 2 is configured as shown in FIG.
The flow of operation under the control of the microprogram is executed, and data in units of 8 bytes is transferred from data buffer 8 to the BPU.
The data is transferred to the main memory device 4 via the interface control logic circuit 9 for the main memory device 4 of No. 3 (actually, the 8-byte data is transferred in two batches of 4 bytes each due to the capacity of the bus. ). FIG. 2 shows that when data is transferred from channel 2 to main storage device 4, channel 2
It is a flowchart of operations executed under the control of a microprogram stolen from the BPU3 side.

The flow of channel operation will be explained with reference to FIG.

In FIG. 2, the operations in one box in the flow are executed in one machine cycle in principle. flow 1
, the channel (hereinafter sometimes abbreviated as CH) 2 activates the main memory (hereinafter sometimes abbreviated as MS) 4, and transfers the address where the data transferred from the channel should be stored. . In flows 2 and 3, 4 bytes of data are each transferred from the channel CH to the main memory MS.

Now that the 8-byte data transfer has finished, flow 4
At , the byte counter is updated and the address in the main memory to be transferred next is specified and the amount of data to be transferred is specified.

This completes the main operation of data transfer. flow 5
The microprogram in is for testing whether an error has occurred in the MS operation cycle performed in the main storage device 4. In this flow 5, in the present invention, from the channel CH to the main memory device MS
When the data transfer to leads to a partial write, the main memory MS, which was activated from the channel CH in flow 1, checks the data read from the memory to the register during the partial write operation. The channel CH executes the program of flow 5 over a plurality of machine cycles and waits until the MS operation cycle including determination of the result is completed. Therefore, if it is detected that an error has occurred in the MS operation cycle at this time, the control operation by steal has not been completed in the channel, so by executing the microprograms 7 and 8, necessary failure information can be obtained. It becomes possible to easily evacuate to an appropriate location. On the other hand, when the data transfer from the channel CH to the main storage device MS leads to full writing,
Unlike the partial write case, no data read check is performed during the MS operation cycle, so the channel can continuously execute flows 1 to 6 without waiting for the end of the MS operation cycle. . FIG. 3 shows the temporal relationship of the above flow. See Figure 3.

A) is a time chart to show the time scale of the machine cycle, and shows how the machine cycle progresses over time. When the data transfer from the channel CH to the main memory MS leads to a full write operation, the flow of operations in the channel ends sequentially from 1 to 5 in FIG. It is shown that. No. 9 is a case where the data transfer from the channel CH to the main memory MS leads to a partial write operation, and in flow 5 in FIG. 2, the MS operation shown in d) is performed after waiting for 3 machine cycles. This indicates that the flow will wait for the end of the cycle and move on to the next flow. Therefore, it can be seen from FIG. 3 that the data transfer leading to a partial write operation takes nine machine cycles, while the data transfer leading to a full write operation completes in six machine cycles. In other words, compared to the method of uniformly waiting for the end of the MS operation cycle without determining whether the data transfer will lead to a partial write operation or a full write operation, It will be appreciated that since most accesses result in full write operations, there is a considerable machine cycle savings. In FIG. 3, error signal 1 indicates that if there is an error when checking read data during partial writing, error signal 1 will be output around 6.5 machine cycles in the MS operation cycle. The error signal 2 indicates that if there is an error as a result of a check such as address in the MS operation cycle, the error signal 2 is output around the third machine cycle in the MS operation cycle. In other words, the results of error checks on read data are finalized around 6.5 machine cycles in the MS operation cycle, which is very slow, whereas the results of error checks on addresses, etc. are finalized only after the MS operation cycle. It is determined at a relatively early time, around the third machine cycle of the operation cycle.
The MS-END signal represents the signal output by the end of the MS operation cycle. Next, returning to FIG. 1, the hardware for the channel to execute the operation flow as shown in FIG. 2 will be described.

Now, the data transfer from channel 2 to main storage device 4 is as follows.
When the data is partially written to the main storage device MS, it takes time to determine the result of checking the read data in the MS operation cycle (see error signal 1 in FIG. 3), so the sequence control logic circuit 10 of the BPU 3
Now, the signal (TEST=MS-ERROR) resulting from the decoding of the microprogram (Did an error occur in MS?) read from the control storage device 12 by the microprogram/decode logic circuit 5 of the channel and the partial write operation detection logic circuit. Partial write signal PW (PartialWr
(abbreviation of it) by AND circuit A, and BP
In the presence of a similar signal (TEST:=MS-ERROR) from the microprogram decode logic circuit 13 of U, the signal MS-END( (see FIG. 3) is received by the sequence suppression logic circuit 11.
The control storage device 12 is controlled to inhibit the channel from executing the microprogram 5 (see FIGS. 2 and 3). In other words, the inhibition logic circuit 11
Until a signal is received, the same microprogram is repeatedly read from the control storage device 12 of the BPU, inhibiting the progression of the sequence. When the MS-END signal arrives, the sequence control logic circuit 10 stops inhibiting the inhibition logic circuit 11 and allows the channel to execute the microprograms 5, 6 (see FIGS. 2 and 3);
One data transfer from the channel to the main memory is completed. On the other hand, data transfer from the channel to the main memory is
When the operation leads to a full write operation to the main memory, unlike the case of partial write, the check of read data whose check result is slow to be determined (Error signal 1 in Figure 3)
is not performed in the MS operation cycle, and checks for address errors, etc. are performed, but the check results are determined quickly (error signal 2 in Figure 3), and are determined between 1 and 4 in the microprogram flowchart in Figure 2. Because I end up doing it,
In the channel transfer control, there is no need to wait for the arrival of the MS-END signal, and flows 1 to 6 may be executed continuously. Therefore, the sequence control logic circuit 10 of the BPU also
No inhibition control is performed by the inhibition logic circuit 11.
As the partial write operation detection logic circuit 6 in channel 2, it is set when instructing the start of data transfer from the channel to the input/output device 1, and is set when the first data transfer from the channel to the main storage device is performed. a flip-flop that remembers that this is the first data transfer (the first access to the main memory), and a data transfer controller that controls data transfer when the last data is sent from the input/output device 1 to the data buffer 8. A flip-flop which is set by the function of the logic circuit 7 and reset at the time of the next data transfer from the data buffer 8 to the main memory device 4, and which remembers that it is the last data transfer (last access). It is obvious that the above-mentioned partial write signal PW can be generated by using a logic circuit constituted by When data is transferred from an input/output device to the main memory via a channel that performs While using this method, it has the advantage that the data transfer ability from the channel to the main storage device can be almost the same as that of the above-mentioned left-handed control.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention, FIG. 2 is a flowchart of a transfer operation executed by the channel under the control of a microprogram stolen from the BPU side during data transfer, and FIG. This is a time chart of the flow of operations in the figure.

Claims (1)

[Claims] 1. In a data transfer control method for a channel that has a data buffer for buffering transfer data and transfers data between an input/output device and a main storage device via the buffer, the main storage device is The control program for the basic processing unit (hereinafter abbreviated as BPU) shared with the channel is
By stealing the channel from the PU side, the data transfer operation between the data buffer and the main storage device is started and controlled, and moreover, the data transfer operation between the data buffer and the main storage device is performed every certain unit data amount. If the amount of transferred data written to the main memory is less than the unit data amount, the main memory side is activated by the start of the channel transfer operation and starts the operation. The above-mentioned BP
When the processing operation on the U side is resumed and the amount of transferred data written to the main storage device is equal to the unit data amount, the data transfer is ended without waiting for the end of the MS operation cycle and the processing operation on the BPU side is resumed. A channel data transfer control method characterized by restarting a processing operation.