JPH0248733A - Information processor - Google Patents

Abstract

PURPOSE:To eliminate OSC (Operand Store Conflict) detection logic circuit and OSC dealing control logic circuit and to reduce a hardware quantity by controlling the processing stage of an instruction executing memory storage so as the OSC is not generated. CONSTITUTION:A storage operation into a buffer memory 10 among the storage operation into the memory 14 of a store instruction 2 is executed without waiting for the completion of the instruction processing of an instruction prior to the store instruction 2. For the stage, an operand data read stage L being the idle stage of the store instruction 2 can be used. Consequently, the storage operation into the buffer memory 10 can be executed prior to the operand reading of the subsequent instruction and the generation of OSC itself is avoided. Thus, the detection circuit of OSC and the dealing control circuit of OSC are eliminated and the hardware quantity can considerably be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an information processing apparatus, and particularly to an information processing apparatus employing a pipeline control method.

[Prior Art] In general, a pipeline control method is a method in which the processing of one instruction is divided into multiple stages, multiple instructions are input with a predetermined cycle shift, and each stage operates in parallel on multiple instructions. This method reduces the average execution time per instruction and improves the performance of information processing devices.

An example of such a pipeline control method is shown in FIG. In this example, the processing of one instruction is D, M, A, L,
It is divided into six stages: E and W. Here, D is the instruction decoding stage, M is the addition stage to find the logical address of the operand, A is the address translation stage to convert the calculated logical address of the operand to a real address, and L is the stage for converting the operand data from the buffer memory. A read stage reads data, E is a calculation stage that performs calculations using the obtained operand data, and W is a storage stage that writes the calculation results to a register or memory.
These stages are executed at one cycle pitch.

Now, in FIG. 6, instruction 2 is a store instruction that stores operand data at an arbitrary address in memory, for example, real address a, and instruction 3 is a store instruction at the same address a.
Consider the case where the instruction reads the contents of an address as an operand address. In this case, since instruction 3 is issued after instruction 2, the operand data read by instruction 3 should be the operand data stored in instruction 2. However, in the pipeline control shown in Figure 6,
Since the operand data read stage L of instruction 3 is processed before the operand data storage stage W of instruction 2, there may be an inconvenience that in instruction 3, the data before being stored (updated) by instruction 2 is read out as operand data. . In this way, prefetching the operands of a subsequent instruction before storing them in memory of the preceding instruction is generally known in OS C (Operand 5tore).
Conflict). In order to cope with this oSC, an information processing device that employs a pipeline control method has a means for detecting the oSC, and a means for detecting the oSC.
It is essential to have a processing function to deal with this when it occurs.

In the conventional device, as shown in FIG. 2, when instruction 2 is an instruction for storing memory, the store address obtained in stage A is registered in a store address register for match detection, and instruction 2 is At stage A of subsequent instructions 3, 4, and 5, the operand address is compared with the contents of the store address register, and if a match is detected, the operand data read stage L is transferred to instruction 2.
A process was performed to make the operator wait until the completion of the operand data storage stage W. In this method, when oSC occurs,
As described above, since the operand reading of the subsequent instruction is delayed, the pipeline is disturbed and the performance of the information processing device is degraded.

In order to eliminate this drawback, various bypass methods have been proposed in the past. For example, techniques such as those described in Japanese Patent Publication Nos. 61-8453 are known. This means that when processing an instruction that stores in memory, not only the operand address is registered in the store address register, but also the operand data is registered in the store buffer register, and the operand read address of the subsequent instruction is set to the store address. If both addresses match after comparison.

This method eliminates the need to wait for operand readout and prevents performance degradation by controlling operand data to be read from the store buffer register rather than from the buffer memory.

Problem to be Solved by the Invention J In the above conventional technology, in order to prevent performance degradation due to O20, bypass control logic such as a store buffer register is required, and since it is also necessary to detect O20, the store address register, address Comparison circuits etc. are also required,
There was a problem that the amount of hardware increased.

An object of the present invention is to reduce the processing stage of an instruction for memory storage in an information processing apparatus using a pipeline control method.
By controlling so as not to generate 20, the O8C detection logic and O5C handling control logic are unnecessary, and the amount of hardware can be drastically reduced.

[Means for Solving the Problems] An information processing device according to the present invention is an information processing device of a pipeline control type that has a main memory and a buffer memory that holds a copy of a part of the main memory. When processing an update command to update memory information,
The present invention is characterized in that a control means is provided for controlling the information updating operation of the buffer memory to be performed in the instruction processing of the update instruction before the processing of the instruction preceding the update instruction is completed.

According to another aspect, the information processing apparatus according to the present invention is an information processing apparatus of a pipeline control type having a main memory and a buffer memory holding a copy of a part of the main memory. A control means is provided for controlling an operation of updating information in a buffer memory in the instruction processing of an update instruction before an operand read operation of an instruction following the update instruction when processing an update instruction for updating information. That is.

According to still another aspect, the information processing apparatus of the present invention is an information processing apparatus of a pipeline control type having a main memory and a buffer memory holding a copy of a part of the main memory. During the instruction processing of an update instruction that updates the information of the update instruction, before the processing of the instruction preceding the update instruction is completed, and before the operand read operation of the instruction following the update instruction, the information in the buffer memory is updated during the instruction processing of the update instruction. The present invention is characterized in that a control means for controlling the update operation is provided.

Preferably, the control means controls the information update operation of the main memory by the update command to be performed after the processing of the preceding command is completed.

According to another aspect, the information processing apparatus of the present invention is an information processing apparatus of a pipeline control type having a main memory and a buffer memory holding a copy of a part of the main memory. The present invention is characterized in that a control means is provided for controlling a data storage operation to be performed in a buffer memory at an operand read stage among a plurality of stages of pipeline control during instruction processing of a store instruction for storing data. be.

In this case, preferably, the control means controls the data storage operation in the main memory to be performed at the final stage.

The information processing device further includes a detection means for detecting an interruption when the instruction is interrupted after the update operation of the buffer memory by an update instruction or a store instruction;
It is desirable to provide means for invalidating updated information in the buffer memory.

[Operation] In an information processing device that has a buffer memory that holds a copy of a part of the main memory and employs a pipeline control method, an information update instruction (hereinafter, typically referred to as a store instruction) is In consideration of the occurrence of interrupts, etc., data is stored in the buffer memory after the preceding instruction has been processed, and the same data is stored in the main memory at the same time or after that. This is the principle.

However, the inventors of the present invention focused on the fact that operand data is neither read nor operated in a store instruction, and therefore, among the memory storage operations of a store instruction, the storage operation in a buffer memory is , we have come up with the idea of executing the store instruction without waiting for the completion of instruction processing of the instruction preceding it. The operand data read stage, which is an empty stage in a store instruction, can be used as a stage for storing data in the buffer memory. As a result, in normal pipeline control, the storage operation in the buffer memory in the store instruction can be performed before the operand reading of the subsequent instruction, so that the occurrence of O20 itself can be avoided. Therefore, an O20 detection circuit and an O20 countermeasure control circuit as in the prior art are not required, and the amount of hardware can be significantly reduced.

Note that the disadvantage of updating the information in the buffer memory before the processing of the preceding instruction is completed is that if an interrupt occurs during the execution of the preceding instruction and the store instruction is not executed, the contents of the buffer memory may not match the instruction operation. A situation of contradiction arises. What are the disadvantages of this?

If the pipeline of a store instruction is interrupted between the buffer memory storage in the store instruction and the completion of the store instruction, this interruption is detected and the information stored by the store instruction among the information in the buffer memory is invalidated. This can be corrected by doing so.

Detection of store instruction pipeline interruption can be performed by existing means of detecting interrupts, and invalidation of information stored in the buffer memory can be performed using existing means such as resetting the valid bit of the information stored in the buffer memory. It can be dealt with by means. Therefore, the amount of hardware does not increase due to these processes.

In addition, if the storage operation to the store main memory is controlled to be processed in the last stage of the store instruction pipeline, where the instructions before the store instruction have completed, as before, when the store instruction pipeline is interrupted, the above will occur. No adverse effects will occur.

[Example J Hereinafter, one embodiment of the present invention will be described in detail.

FIG. 3 shows a block diagram of an embodiment of an information processing apparatus according to the present invention. The present embodiment will be described using an example of an apparatus that employs a pipeline control system consisting of six stages D, M, A, L, E, and W, as described above.

In FIG. 3, each block is shown corresponding to the flow of each stage of the pipeline. The information processing device shown in FIG.
An instruction register 1 that stores instruction codes, a decoder storage 2 that decodes instructions, a decoder data register 3 that holds the instruction decoding results, a control unit 4 that controls the entire device according to the contents of this register 3, a general-purpose register 5, and logic. An address arithmetic circuit 6 that calculates an address, a logical address register 7 that holds the calculated logical address, and a T L B (T
ranslation Lookaside Buff
er) 8, a real address register 9 that holds real addresses, a main memory 14. A buffer memory (cache memory) 10 that holds a copy of a portion of this main memory 14 and is specified by the real address register 9, a work register 11 that temporarily holds the output of this buffer memory IO.
An arithmetic unit 12 that calculates the re-output of the work register 11 and the general-purpose register 5; an output register 1 that temporarily holds the output of the arithmetic unit 12 and stores it in the main memory 14;
31. It consists of a store address register 15 that holds a store address of a store instruction according to the present invention, and a stage interruption detection means 16 that detects a stage interruption of a store instruction.

Hereinafter, the vibe line conceptual procedure of the store command in the information processing apparatus shown in FIG. 3 will be explained.

First, a store instruction to be executed is read into the instruction register 1, and in the D stage, the type of instruction, etc. is decoded by referring to the decoder storage 2. The decoded result is stored in the decoder data register 3, and the control section 4 controls subsequent stages according to this content.

In the next M stage, the address arithmetic circuit 6 finds a logical address in the logical address register 7.

Furthermore, in the next A stage, the real address is found in the real address register 9 by referring to the TLB8. T.L.
If the logical address to be translated is not registered in B8, a corresponding real address is determined by a well-known address translation means (not shown).

Now, in the next stage, if it is a normal instruction, the real address register 9 accesses the buffer memory 10 and reads out the operand data, but in the case of a store instruction, the real address is read out under the control of the control unit 4. Store data from the general-purpose register 5 is stored at the address location of the buffer memory 10 specified by the register 9. At the same time, processing when a store instruction is interrupted by an interrupt, etc. (described later)
In preparation for this, the real address of the real address register 9 is stored in the store address register 15.

The following E stage is a stage in which the arithmetic unit 12 executes operations on the contents of both the work register 11 and the general-purpose register 5, which store the operand data read from the buffer memory 10, and outputs the results to the output register 13, depending on the type of instruction. However, in the case of a store instruction, the work register 11 is not used, and the value of the general-purpose register 5 is passed through the arithmetic unit 12 and stored in the output register 13.

The final W stage is a storage stage for calculation results,
The contents of the output register 13 are stored in the main memory 14.

The processing stage of the store command in the information processing apparatus shown in FIG. 3 has been described above, and the timing chart of this processing stage is shown in FIG. 4.

As can be seen from this figure, in this embodiment, the store instruction is in an empty stage, and the storage operation to the buffer memory IO is performed in the stage. Main memory memory 1
The storing operation to 4 is performed on the W stage as before.

Further, a store address is held in the store address register 15 during the E stage and the W stage.

FIG. 1 shows the state of pipeline processing when the present invention is adopted. As in the case of FIG. 6 and FIG.
is a store instruction, and instruction 3 is an instruction to read the store data of instruction 2 as operand data. As described above, in instruction 2, which is a store instruction, data is stored in the buffer memory 10 at stage L (W'). Instruction 3 operand data read stage L
Since stage L is temporally later than stage L of instruction 2, instruction 3 can read the data updated by instruction 2 from the buffer memory 10 as operand data. Therefore, since there is no need to delay the readout of operands of subsequent instructions, the pipeline processing is not disturbed as shown in FIG.

Next, referring to the timing chart of FIG. 5, the buffer memory storage stage W of the store instruction processing stage will be explained.
A case will be described in which the store instruction processing stage is interrupted after ' (that is, the original stage L) due to an interrupt caused by the processing result of the instruction preceding this store instruction.

As described above, in such a case, a situation arises in which the buffer memory is updated even though the memory update by the store instruction should not be executed. Therefore, in this embodiment, the following measures are taken.

There are two possible cases in which a store instruction is interrupted after the W' stage: after the W' stage ends and after the E stage ends, but here we assume that the interrupt occurs due to an interrupt occurring after the W' stage ends. Then, the stage interruption detection means 16 detects that the stage is interrupted,
Under the control of the control unit 4, the valid bit of the data in the buffer memory IO is set to O in accordance with the address previously stored in the store address register 15, thereby invalidating the data. As a result, the data stored in the buffer memory IO by the store instruction is invalidated. In addition, E
If the game is interrupted after the stage ends, it will be handled in the same way.

Although preferred embodiments of the present invention have been described above, the present invention is not limited thereto, and various modifications and changes can be made without departing from the gist of the present invention.For example, The type and number of stages in the pipeline are not limited to those mentioned above. Also, although the L stage is used to store data in the buffer memory in a store instruction, it may be executed before the operand data is read in the subsequent instruction. If possible, stages other than the L stage may be used.

[Effects of the Invention] As explained above, according to the present invention, in an information processing apparatus using a pipeline control method, O
Since the occurrence of O20 can be prevented, a circuit for detecting O20 and a circuit for dealing with the occurrence of O8C are not required, and the amount of hardware can be significantly reduced. Inconsistency in the contents of the buffer memory due to interruption of the processing stage of an information update command can be resolved by invalidating the updated contents of the buffer memory.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of pipeline processing according to the present invention, and FIG.
3 is a block diagram showing an embodiment of the information processing device according to the present invention; FIG. 4 is a timing chart showing the operation of the device shown in FIG. 3; FIG. 5 is a timing chart showing the operation of the device in FIG. 3 when a stage interruption occurs;
FIG. 6 is an explanatory diagram of general pipeline processing. 1...Instruction register, 2...Decoder storage,
3... Decoder data register, 4... Control unit, 5
... General-purpose register, 6... Address calculation circuit, 7.
・Logical address register, 8・-TLB, 9...
・Real address register, 10...Buffer memory, 1
1...Work register, 12...Arithmetic unit, 13-...
- Output register, 14--Main memory, 15...
Store address register', 16... Stage interruption detection means

Claims (1)

[Scope of Claims] 1. In a pipeline control type information processing device having a main memory and a buffer memory that holds a copy of a part of the main memory, an update for updating information in the main memory. Information processing characterized in that a control means is provided for controlling the information updating operation of the buffer memory in the instruction processing of the update instruction before the processing of the instruction preceding the update instruction is completed in the instruction processing of the instruction. Device. 2. In a pipeline control type information processing device having a main memory and a buffer memory that holds a copy of a part of the main memory, when processing an update instruction to update information in the main memory, An information processing apparatus comprising: a control means for performing control to perform an information update operation of the buffer memory in the instruction processing of the update instruction before an operand read operation of an instruction following the update instruction. 3. In a pipeline control type information processing device having a main memory and a buffer memory that holds a copy of a part of the main memory, when processing an update instruction to update information in the main memory, Control to perform the information update operation of the buffer memory in the instruction processing of the update instruction before the processing of the instruction preceding the update instruction is completed and before the operand read operation of the instruction following the update instruction. An information processing device characterized by being provided with means. 4. Claim 1 or 3, wherein the control means controls the information update operation of the main memory by the update command to be performed after the processing of the preceding command is completed.
The information processing device described. 5. In a pipeline control type information processing device having a main memory and a buffer memory that holds a copy of a part of the main memory, when processing a store instruction to store data in the main memory, An information processing apparatus comprising: a control means for controlling a data storage operation to be performed in the buffer memory at an operand data read stage among a plurality of stages of pipeline control. 6. The information processing apparatus according to claim 5, wherein the control means controls the storage operation of data in the main memory to be performed at a final stage. 7. The information processing apparatus according to claim 1, 2, 3 or 5, further comprising: detecting the interruption if the update instruction or the store instruction is interrupted after the update operation of the buffer memory; An information processing apparatus comprising: a detecting means; and a means for invalidating the updated information in the buffer memory.