JPS596314U - Muting pulse generation circuit - Google Patents
Muting pulse generation circuitInfo
- Publication number
- JPS596314U JPS596314U JP10020682U JP10020682U JPS596314U JP S596314 U JPS596314 U JP S596314U JP 10020682 U JP10020682 U JP 10020682U JP 10020682 U JP10020682 U JP 10020682U JP S596314 U JPS596314 U JP S596314U
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- power supply
- generation circuit
- operation level
- pulse generation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Amplifiers (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来のミューティングパルス発生回路を示す回
路図、第２図はミューティングパルス発生回路の動作説
明図、第３図、第４図はそれぞれこの考案の実施例を示
す回路図である。
１１、 １４． １６． １９・・・抵抗、１２・・・
ツェナーダイオード、１３．１８・・・トランジスタ、
１５゜１７・・・ダイオード、１０・・・コンデンサ。FIG. 1 is a circuit diagram showing a conventional muting pulse generation circuit, FIG. 2 is an explanatory diagram of the operation of the muting pulse generation circuit, and FIGS. 3 and 4 are circuit diagrams each showing an embodiment of this invention. . 11, 14. 16. 19...Resistance, 12...
Zener diode, 13.18...transistor,
15°17...Diode, 10...Capacitor.
Claims (1)
電源電圧に対して、第１の動作レベルでオンし、この第
１の動作レベルよりも低い電源電圧でオフするように設
定された第１のトランジスタと、前記第１の動作レベル
よりも低い第２の動作レベルでオンし、この第２の動作
レベルよりも低い電源電圧でオフするように設定され、
前記第１のトランジスタがオンしたときは強制的にオフ
される第２のトランジスタとを具備し、前記第２のトラ
ンジスタの出力をミューティングパルスとするミューテ
ィングパルス発生回路において、前記第１のトランジス
タの第１の動作レベルを設定するために、この第１のト
ランジスタのベースと電源ライン間に接続されるツェナ
ーダイオードを含む回路内に、前記電源電圧の低下を前
記第１のトランジスタベースに高速伝達するコンデンサ
を設けたことを特徴とするミューティングパルス発生回
路。A first transistor configured to turn on at a first operation level and turn off at a power supply voltage lower than the first operation level in response to a power supply voltage that changes transiently when a power switch is turned on or off. and is set to turn on at a second operation level lower than the first operation level and turn off at a power supply voltage lower than the second operation level,
and a second transistor that is forcibly turned off when the first transistor is turned on, and the muting pulse generation circuit uses an output of the second transistor as a muting pulse, wherein the first transistor In order to set a first operating level of the first transistor, a drop in the power supply voltage is quickly transmitted to the base of the first transistor in a circuit including a Zener diode connected between the base of the first transistor and the power supply line. A muting pulse generation circuit characterized by being provided with a capacitor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10020682U JPS596314U (en) | 1982-07-02 | 1982-07-02 | Muting pulse generation circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10020682U JPS596314U (en) | 1982-07-02 | 1982-07-02 | Muting pulse generation circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS596314U true JPS596314U (en) | 1984-01-17 |
Family
ID=30237153
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10020682U Pending JPS596314U (en) | 1982-07-02 | 1982-07-02 | Muting pulse generation circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS596314U (en) |
-
1982
- 1982-07-02 JP JP10020682U patent/JPS596314U/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS596314U (en) | Muting pulse generation circuit | |
| JPS6066126U (en) | reset circuit | |
| JPS6129549U (en) | Muting circuit | |
| JPS5994441U (en) | Power-on reset circuit | |
| JPS60172434U (en) | Malfunction prevention circuit at startup | |
| JPS5917862U (en) | Voltage drop detection circuit | |
| JPS6071923U (en) | Simple feedback constant voltage circuit | |
| JPS5850529U (en) | Pulse generation circuit | |
| JPS5923760U (en) | Light emitting diode switching circuit | |
| JPS5963715U (en) | Constant voltage power supply circuit | |
| JPS5939527U (en) | Amplifier muting circuit | |
| JPS6064633U (en) | switch input circuit | |
| JPS59113810U (en) | power supply | |
| JPS60192022U (en) | Auto clear circuit | |
| JPS59187239U (en) | switch circuit | |
| JPS5972890U (en) | Motor control circuit | |
| JPS58138409U (en) | Muting circuit | |
| JPS6113310U (en) | Recording bias switching circuit | |
| JPS5975349U (en) | reset circuit | |
| JPS58147019U (en) | power protection circuit | |
| JPS5826236U (en) | timer circuit | |
| JPS59174738U (en) | Transistor base drive circuit | |
| JPS59169618U (en) | Stabilized power supply circuit | |
| JPS59127340U (en) | drive device | |
| JPS60193717U (en) | switching circuit |