JPS5962959A - Storage device - Google Patents

Abstract

PURPOSE:To read and write data extending oven two addresses with one memory access by selecting and giving two addresses to each memory chip. CONSTITUTION:A storage device 6 generates one or two addresses, which are accessed when designation of a position of data read/write is inputted, of N- number of sets of memory chip groups 4-1-4-N which constitute N-bit word length to store data. An address generating circuit 7 selects and supplies these addresses to memory chip groups 4-1-4-N. A data form converting circuit 15 converts normalized data to a form, where data is stored in the memory of memory chip groups, or converts data, which is read out from the memory of memory chip groups, to a normalized form easy to operate. Thus, data is stored in or read out from two addresses with one memory access.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a method for storing or reading data having a length of 1 to N bits across two addresses in memory accesses 1. ii HIi? i.

Conventionally, this processing is performed using electronic nl'3Q Iso's performance 39
This was performed in software by the processing unit and the main memory 6'. FIG. 1 is a block diagram showing the essential points. In the figure, 1 indicates the main memory 1, (y indicates the overall configuration of the device, and 2 indicates the arithmetic processing unit. The main memory t"i
To explain the internal structure of 1-1, 3 is a 7-res ranboo to hold the address to be read/written, 4-J to 4-N! 'jJIvia)QlInnoRt)j, ;l f row 5 memory chip, 5 is front rI
IX! This is a data lug that holds the outputs of the memory chips 4-1 to 4-N in units of words. Main memory [Addresses in 1 are published for each middle word (N pit) + Tjtl
The focus/71゛I/S (0~N-]) is the bit/
Address 0 is memory chip 4-1, Pinto 7 “Res.
is memory boot block 4-2, . . . bit address N-1 is assigned to memory chip 4-N.

Next, the operation of the data read stand XlIb will be explained. The data to be read is N-pils long, and the first N-
When 2 bits are stored in the bit address N-3 from the i-th location, and the remaining 2 bits are stored in the focus addresses 0 and 1 of the i-1-1rrf location, the arithmetic processing unit h2 is stored in the main memory. A read request and read address i are sent to device 1. On the main memory device n''1 side, this read address i is held in the 7-dress latch 3 and supplied to each memory chip 4-1 to 4-N.
A read request is made for -1 to 4-H, and the contents of address i are taken out to data latch 5. The contents launched into the data latch 5 are read out by the arithmetic processing unit 2 and held in its internal register. Next, the above-mentioned read operation to the main memory device 1 is repeated for address i+1, and the contents of address 1+1 are held in the internal register of the processing device 2. In the arithmetic processing unit 2, the content of address i and the content of address i+] are combined and normalized by mask processing and shift operation, and the desired data can be obtained by 14I.

The arithmetic processing unit 2 of the conventional electronic punching machine and the above 1. As mentioned above, in the process using V1 device 1, data stored at one address is stripped to 1(f!'-'F), but data stored at two addresses; When reading out data that the user wants to use, two accesses are required, and the read data must be synthesized and IE-standardized in the processor 2 (processor 3'1). Furthermore, when data is stored across two addresses, processing in the arithmetic processing unit 2 and two memory accesses are required, as in the case of reading data.

This invention has been made in view of the above points;
The objective is to provide a storage device that can read and write data across two addresses in one memory access by assigning two locations to each memory chip in a selective manner. .This invention will be explained below based on the drawings.

FIG. 2 shows a storage device 40il in one embodiment of the present invention.
It is a block diagram showing II configuration. In the same figure, 2°4
-1 to 4-N and 5 are an arithmetic processing unit, a memory chip, and a data launch, respectively, as in FIG. 6 is the overall configuration of a storage device 1q which is an embodiment of the present invention, and T
shows the overall configuration of a address generating circuit that supplies addresses to each of the memory chips 4-1 to 4-N. 8 is the position of the first bit of the data to be read (word address 8a and bit 7)
9 is a data length latch that holds the data length of the data to be read; 10 is a bit address latch that holds the address 8b); 10 is a data length latch that adds the outputs of the bit address latch 8 and data length latch 9, and adds 1 from there; The decrementing n operator, 11 is All bit 7 dress latch 8
A first bit address register 12 inputs the word address 11a supplied to each memory chip 4-1 to 4-NK and a pinned address 11b in gffff indicating the position of the first hit of the read data. A final bit address register takes the output as input and outputs a word address 12g to be fed to the memory chips 4-1 to 4-NK and a bit 7 address 12b indicating the last bit position of the read data. 13 is a control register. In the circuit
This control circuit 13 includes a leading bit address register 1.
1 and the bit addresses 11b and 12b in the last hit address register 120 are input, and the controller 111
From IIl tract 13, each manotochiplexa 14-1 to 14
-N for the first bit address register 11 and the last bit address register 120 word addresses 11a and 12a
It outputs a selection signal for selecting one of the outputs and a control signal for the shift width and the like to the data format conversion circuit 15.

The multiplexers 14-] to 14-N input the word addresses 11n and 123 of the first focus address register 11 and the last hint address register 12', and operate the control circuit 1.
Each memory chip 4-1 to 4-
The suspension J (14) that supplies fil to N; selects pe. The data format switching h'315 converts the output of the data latch 5 into ilE J'11. 61゛-processing equipment R
2. The m location in the storage device 6 is the word (N
The bit address (0 to N-, +) of candy 1 is written in units of bits, and bit address 0 is assigned to memory chip 4-1, and bit address] is assigned to memory chip 4-2.
. . . Bit 7 address N-1 is assigned to memory chip 4-NK.

When the arithmetic processing bag [2 specifies the position of a certain bit in the storage device 6, it is specified by ((word address) x 2n + (internal bit address) IK (however, 2'=N,
n is a positive integer).

Next, the operation of the storage device 6 shown in FIG. 2 will be explained. The data to be read is N bits long, and N-2 bits are first stored in N-IK starting from the hit address i,
The remaining 2 bits are i i-1 address σ) bit address O
When the IK is stored, the arithmetic processing unit 2 sends a read request to the storage device 6, the first bit position 1N of the data to be read, (iXN+2), and the data length N. On the storage device 6 side, the first bit position [^)(i
XN+2) is loaded into the bit address launch 8K, and the data length N is loaded into the data length latch 9. It is then binned to output l (i+1 )XN+] ). Next, the output of the bit address latch 8 is taken into the first bit 7 address register 11, the output of the arithmetic unit 10 is taken into the last bit address register 12, and i is taken as the candy address output of the first bit address register 110. 2 is output as the output, i + 1 is output as the final bit address register 120 word address output, and 1 is output as the internal bit address output. Next, the first bit address register 11, the last bit address register 120, and the internal bit address output 2 are controlled by the circuit 1.
A control signal that is taken in to multiplexers 14-3 to 14-N and selects the output of the first bit address register 11 is sent to multiplexers 14'-1 and 14-N.
, 2, the output of the final bit address register 12 is circularly shifted by 2 hits to the left for the data format conversion circuit 15, and the N-bit mask is removed. Outputs a control signal. Then, the locations selected by the multiplexers 14-1 to 14-N are supplied to the memory chips 4-1 to 4-N (memory chips 4-1 to 4-N).
Reboot tab 4-1.4-2 has i + 1 city, May [
Richsono 4-: U~4-NK is supplied with address i).

The data is then read out and the output is data launch 5.
defeated within. Next, the output of the data latch 5 is input to the data format conversion circuit 15, and under the control of the converter 1 circuit 13, it is shifted by 2 bits to the left by 4'', an N bit mask is removed, and the normalized output is output. The arithmetic processing unit 2 then reads this output to obtain the desired data.

In the above embodiment, the position of the data to be read is specified using the first bit 7 address and the data length, but it may be specified using the first and last bit addresses. In addition, when the data length is constant (14), a register for holding the data length and the first bit address and logic for increasing the first bit address by the data length are provided in the storage device 66 so that it is not specified every time. It is also possible to make it possible to do so.

Further, in the above embodiment, one memory chip constitutes one bit, but one bit may be formed into a groove using a plurality of memory chips to enlarge the address space.

Furthermore, although the above embodiment describes the case of reading data, data is stored across two addresses.
In this case, the storage location 1a is input to the similar data format conversion circuit γ, and the data format conversion circuit 15 converts the stored data into a bit array to be stored and supplies it to each memory chip. For a memory chip in which data is not read, the same effect as in the case of reading data can be obtained by sending a write signal I).

As explained above, the storage device according to the present invention has N, ir, n memory chips Wff, !, which have a word length of N bits and store data. :, data C') K)'t h
4'F # Input 1'1' location specification in Sarel, generate two addresses that are accessed by 1, and write them as ■
A circuit that selectively supplies the normalized data to the memory chip/ff memory chip and stores the normalized data in the memory of the memory chip group M or +ii the memory chip group J. Since it is constructed with a data format conversion circuit that converts the data retrieved from the memory of t into a normalized form that is easy to do,
Storing and reading data across two addresses, which was previously performed by memory access and processing in processing unit H, can now be performed with memory access in 11[jl], improving processing efficiency and reducing the load on processing unit 19. φI! It has excellent effects when reduced. Also, on the 11″ piece,
[Storage device according to the present invention] By using Lv as a data buffer for a variable-length router, a data buffer with high storage efficiency can be realized without placing a load on the arithmetic processing unit. 5 Excellent effects There is.

[Brief explanation of the drawing]

Figure 1 shows the reading of data in a conventional electronic word machine.
FIG. 2 is a block diagram showing the structure of the processor groove, and FIG. 2 is a block diagram showing the structure of the data reading mechanism of the JLE storage device as an embodiment of the present invention. In the figure, 4-1 to 4-N are memory chips, 5 is a data latch, 6 is a storage device, T is an address generation circuit, and 8 is bit 7
Address latch, 9 is data length latch, 10 is arithmetic unit, 11 is first bit 7 address register, 12 is last hit address register, 13 is control circuit deh, 1
4-1 to 14-N are multiplexers, and 15 is a data format conversion circuit. F:l:O, 1 indicates the same or equivalent part in the same reference numeral in the diagram 1゜Representative: Shin Kuzuno - (1 other person)

Claims (1)

[Claims] By inputting N sets of memory chip groups each having a word length of N bits and storing data, and specifying the position where the data is to be read, one or two addresses to be accessed are generated and these are stored in the memory chip group. An address generation circuit that selects and supplies data to each memory chip;
It consists of a data format conversion circuit that converts the data stored in the memory of the 1r memory depth llt or the data read out from the memory of the memory chip group into a normalized form that is easy to play poetry, and the memory of the llgl. Access 1
A storage device 6-0 characterized in that N-bit length data can be stored or read across two addresses K of the memory chip group.