JPH10143661A - Data processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data processor capable of accelerating a processing speed for calculating the similarity of binary input data for a binary reference value data pattern. SOLUTION: This data processor for operating pattern matching between an (m) bit binary input data pattern and binary reference data pattern constituted of (m) bits is provided with a data retrieving means 2A which retrieves the bit position of a bit in which the data value of the (m) bit binary input data pattern is one of binaries, data pattern retrieving means 3A which outputs the number of the binary data pattern in which the data value at the same bit position as the output of the data retrieving means 2A is one of the binaries among the binary data patterns to which the first - fifth numbers are assigned based on the output of the data retrieving means 2A, and count means 10 which counts the number of times how many the same number is outputted based on the output of the data pattern retrieving means 3A. The counting of the coincident bits of the data values can be simplified.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing apparatus for calculating the similarity of binary input data to a binary reference data pattern in digital data processing.

[0002]

2. Description of the Related Art FIG. 12 shows a configuration diagram of a conventional pattern matching circuit. In FIG. 12, first, m
Shift register 1 stores data for one row of memory (K rows × J columns) 1 in which a binary input data pattern of bits is stored
03 is stored in a memory (K rows.times.x) where an m-bit binary reference data pattern serving as a matching reference with the m-bit binary input data pattern corresponding to the memory 1 is stored.
J column) The data for one row of 102 is shifted by the shift register 104
To enter. When data is input to each of the shift registers 103 and 104, the shift registers 103 and 104 start a shift operation. The contents of the least significant bit (hereinafter referred to as MSB) of the shift register 103 and the shift register 10
When the contents of the MSBs of the two shift registers 103 and 104 are both "1", the AND circuit 105 which inputs the contents of the MSB of "4" outputs "1", and counts the value of the counter 106 at the next stage. Proceed.

The contents of the MSBs of the shift registers 103 and 104 are stored in the most significant bits (LS) of the memories 1 and 102, respectively.
When the data of B) is obtained, the shift registers 103, 1
04 receives the following data from the memories 1 and 102, respectively. When the logical product is obtained between all the corresponding data in the memory 1 and the memory 102, the counter 106 stores the m-bit binary input data pattern stored in the memory 1 and the m-bit binary input data pattern stored in the memory 102. This means that the result of pattern matching with a value of 1 between the binary data pattern is counted.

[0004]

As described above, a binary input data pattern having a data size of m bits (K bits.times.J bits) and a binary data pattern having a data size of m bits (K bits.times.J bits) are described. When the matching score of is calculated, one shift operation of the shift register is required for one data read from the memory.
× J processing cycles are required.

Further, when there are L binary reference data patterns for pattern matching, there is a problem that an L-times processing cycle is required and the amount of calculation is large, so that the calculation processing time becomes long.

The present invention has been proposed in view of the above-mentioned conventional circumstances, and has as its object to provide a data processing device with an improved processing speed.

[0007]

In order to achieve the above object, the present invention employs the following means. That is, the present invention provides an m-bit binary input data pattern and m-bit binary input data patterns.
It is assumed that the data processing device performs pattern matching with a binary reference data pattern composed of bits.

In the above data processing device, first, as shown in FIG. 1, for example, data for retrieving a bit position of a bit in which the data value of the m-bit binary input data pattern is any one of binary values A search unit 2A is provided, whereby the bit position of any one of the binary data to be searched can be obtained.

Next, the present invention relates to the data search means 2.
A of the binary data patterns assigned the first to n-th numbers based on the output of
A data pattern search means 3A for outputting the number of a binary data pattern in which the data value at the same bit position as the output of A is any one of the above-mentioned binary values is provided. As a result, the pattern number of the pattern in which the target bit position is the target data value is obtained.

Further, a counting means 10 is provided to count the same number among the pattern numbers obtained as described above. As a result, a data pattern having a high similarity in the target data value can be obtained.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described.
Description will be given based on the drawings. (Embodiment 1) FIG. 1 shows a configuration diagram of a data processing apparatus according to a first embodiment of the present invention.

First, in a state where an m-bit binary input data pattern is stored in the memory 1 (first memory), the data retrieving means 2A reads the m-bit binary input data stored in the memory 1. It searches and outputs the bit number of the bit whose data value is 1 from the first bit in the pattern. The data pattern search means 3A includes, among binary reference data patterns assigned numbers from 1 to n,
The pattern number k (k: k: k) of the data pattern whose value at the same bit position as the value output from the data search means 2A is 1
(An integer from 1 to n). The configuration of the data pattern search means 3A will be described later in detail.

The output of the data pattern searching means 3A is input to the counting means 10, where the same pattern number k is counted. In other words, the count enable decoder 4 receives the output of the data pattern searching unit 3A, among 9n from the next stage of the counter 9 _1, the same number k and the output of the data pattern searching unit 3A counter 9
_An enable signal is output to _k (k is treated as a suffix), whereby the selected counter 9 _k is incremented. By repeating the above operation, counters 9 ₁ to 9 n
Stores the total number of matches of bits whose data value is "1" between the binary input data pattern and the binary reference data pattern assigned a number from 1 to n.

FIG. 2 shows a configuration diagram in the case where there are five types of binary reference data patterns with 8 bits, that is, m = 8. FIG. 3 shows a specific example of a binary input data pattern.
FIG. 4 shows specific examples of five types of binary reference data patterns.

Hereinafter, the operation when the binary input data pattern shown in FIG. 3 and the binary data pattern shown in FIG. 4 are used in FIG. 2 will be described. The data search means 2A outputs a bit number having a data value 1 counted from the first bit, that is, 0, 4, and 7.

Next, the data pattern search means 3A outputs the pattern number k of the binary reference data pattern in which the same bit as the output (0, 4, 7) of the data search means 2A is "1".
Is output. That is, as shown in Table 1 at the end, the data pattern in which the 0th bit is 1 is k = 1,
The data pattern in which the third, fourth and fourth bits are 1 is k =
The data pattern in which the third, fourth and seventh bits are 1 is k =
Since it is 2,4, 1,3,4,3,4,2,4 are sequentially output from the data pattern search means 3A.

The count enable decoder 4 has a counter 9 _{k of the} same number k as the output of the data pattern search means 3A.
Output an enable signal. Therefore, once the counter 9 _1, the counter 9 ₂ once in, the counter 9 ₃ 2
Times, three times in the counter 9 _4, since the counter 9 ₅ 0 times the enable signal is input, the final value of the counter the counter 9 ₁ 1, the counter 9 ₂ 1, counter 9 ₃ 2, counter 9 ₄ 3, the counter 9 ₅ 0. Therefore, as long as this method is followed, it can be understood that there are many portions where the reference pattern of No. 3 matches the input pattern.

As described above, the amount of calculation can be reduced by using the known information indicating which bit of the binary reference data pattern has the data value 1. (Embodiment 2) FIG. 5 shows a configuration diagram of a data processing apparatus according to a second embodiment.

In this embodiment, the counting means 10 has the following configuration. Since the configuration up to the counting means 10 is the same as that of FIG. 1 (FIG. 2), the description will be simplified. As in the first embodiment, the memory 1 stores the stored m-bit binary input data pattern, and the data search means 2A outputs the m-bit binary input data pattern stored in the memory 1. The bit having the data value of 1 is searched and output at the bit number counted from the first bit.
The data pattern search means 3A outputs a pattern number k of a data pattern whose value at the same bit position as the value output from the data search means 2A is 1 among binary reference data patterns to which numbers from 1 to n are assigned. I do.

The memory 5 (second memory) constituting the counting means 10 has an m-bit binary input data pattern and
The number of coincidences of the bit whose data value is 1 is stored between the binary data pattern to which the number from n is assigned and the initial value is 0. Here, if the output of the data pattern search means 3A is input as an address value of the memory 5, the address value matches the pattern number k of the binary reference data pattern.

When the address of the memory 5 is designated by the output of the data pattern search means 3A, the contents of the address are incremented by the increment means 110, and the incremented value is written again to the same address. That is, the value read from the specific address of the memory 5 is input to the second register 6 and is incremented by the incrementer 8.
Is incremented and input to the first register 7, and the contents of the first register 7 are written to the address of the memory 5 specified as described above. As a result, the number of bit matches when the data value is "1" between the binary input data pattern and the specific binary reference data pattern is updated.

FIG. 6 is a block diagram showing the contents of FIG. 5 in more detail. As in the first embodiment, there are five types of binary reference data patterns, the binary input data patterns are those shown in FIG. 3, and the five binary reference data patterns are those shown in FIG. And the same as

The output of the data pattern search means 3A is k =
The points of 1, 3, 4, 3, 4, 2, and 4 are the same as those in the first embodiment, and the description is omitted. Upon receiving the output of the data pattern search means 3A, the memory 5 first receives an address value 1 as a read address via the read means 120. Here, the initial value of the memory 5 is assumed to be 0 for all addresses, and when the address value 1 is input to the memory 5 as described above, the contents 0 of the address 1
Is read out to the second register 6 constituting the incrementing means 110, and the value is incremented by the incrementer 8 and input to the register 7. Further, this value is written to the address 1 of the memory 5 via the writing means 130.

In this manner, the address values 3, 4, 3, 4, 2, and 4 are sequentially input to the memory 5, and the content of the designated address value is incremented by 1 by the incrementer 8, and Store to original address. As a result, the final value stored in each address is 1 for address value 1, 1 for address value 2, 2 for address value 3, 3 for address value 4, and 0 for address value 5. The number of matching bits whose data value is 1 between the data pattern and the five reference 8-bit binary data patterns can be obtained.

(Embodiment 3) In the first and second embodiments, the bit whose data value is "1" is targeted in the binary input data pattern, but the data value is "1". A similar result can be obtained for a bit that is "0".

The case where the data value is "0" will be described below with reference to FIG. Data search means 2
B retrieves and outputs the bit number of the bit whose data value is “0” from the first bit in the m-bit binary input data pattern stored in the memory 1. The data pattern search means 3B has a value "0" at the same bit position as the value output from the data search means 2B among the binary reference data patterns assigned numbers from 1 to n.

The count enable decoder 4 constituting the counting means 10 outputs an enable signal to the counter 9 _k of the same number k and the output of the data pattern searching unit 3B of (from 9 ₁ 9 _n) counter 9 _k, thereby The selected counter is incremented. By repeating such a procedure, the counters 9 ₁ to 9 _n have bits whose data value is “0” between the binary input data pattern and the binary reference data pattern assigned the numbers 1 to n. The total number of matches is stored.

FIG. 2 shows an example in which there are five types of binary data patterns, the binary input data pattern is the pattern shown in FIG. 3, and the five types of binary reference data patterns are the patterns shown in FIG. This will be further described based on

At this time, the binary input data pattern is 100
01001, the output of the data search means 2B outputs the bit number whose data value is “0”, that is, 1;
2, 3, 5, and 6.

Next, the data pattern search means 3B searches for and outputs the pattern number k of the binary data pattern in which the same bit as the output of the data search means 2A is "0". That is, according to Table 2 at the end, the data pattern numbers whose first bit is “0” are 3, 4, 5, and 5, and the data pattern numbers whose second bit is “0” are 2, 3, 4, 5, 3
The data pattern number whose bit is “0” is 4, 5,
The data pattern number whose fifth bit is “0” is 3,
Since the data pattern numbers in which the fourth, fifth and sixth bits are "0" are 2, 3, 4, and 5, the data pattern search means 2B eventually outputs 3, 4, 5, 2, 3, 4, 5, 4 , 5
3, 4, 5, 2, 3, 4, and 5 are sequentially output.

The count enable decoder 4 has a data path.
The rice in the counter of the same number as the output of the turn search means 3B
Output the cable signal. Therefore, the counter 9₁0
Times, counter 9_TwoTwice, counter 9_ThreeFour times
Unta 9_Four5 times, counter 9_FiveHas five enablements
Signal is input to each counter 9_kThe final value of is a counter
9 is 0, counter 9_TwoIs 2, counter 9_ThreeIs 4, Coun
TA9_FourIs 5, counter 9 ₁Becomes 5. by this,
When “0” is used as a criterion in binary data, the data
The fourth or fifth of the turn has similarity with the input data
Will be expensive.

As described above, the amount of calculation can be reduced by using the known information indicating which bit of the binary reference data pattern has the data value "0". This example is shown in FIGS.
Of course, it is also possible to apply to the second embodiment shown in FIG.

(Embodiment 4) Further, the first, second, and third embodiments
In the embodiment, the calculation may be performed using both the case where “1” is the target of the determination criterion and the case where “0” is the target of the determination criterion.

Hereinafter, the data value "1" will be described with reference to FIG.
A case will be described where both "0" and "0" are to be determined. The data search means 2C searches and outputs the bit number of each data value ("1" or "0") of the m-bit binary input data pattern stored in the memory 1 counted from the first bit.

The function of the data pattern search means 3C is exactly the same as that of the first to third embodiments, and among the binary reference data patterns assigned numbers 1 to n, the data output from the data search means 2C. The pattern number k of the data pattern having the same bit position value as the calculated value is output.

The count enable decoder 4 counter 9 _k data pattern searching unit 3 of (9 ₁ from 9 _n)
An enable signal is output to the counter 9 _k having the same number as that of the output of C, whereby the selected counter 9 _k is incremented. By repeating this procedure, the counter 9 _k has a binary input data pattern and a binary The total number of data values at the same bit position that match the reference data pattern is stored. FIG. 7 shows a more detailed block diagram of the data search means 2C and the data pattern search means 3C in this embodiment. A clock signal synchronized with the reading of the binary input data from the memory 1 is counted by a counter 201 constituting the data search means 2C, and the output of the counter 201 is input to an AND gate 202 and an AND gate 203. The binary input data read from the memory 1 is further input to the AND gate 202.
03 is input with inverted binary input data read from the memory 1. Thereby, the AND gate 20
The bit position when the data value is "1" is
The bit position when the data value is "0" is output from the AND gate 203.

The data pattern search means 3C has a "1" search unit 301 for searching for a pattern number based on the bit position corresponding to the data value "1" and a pattern number based on the bit position corresponding to the data value "0". Search for “0”
A search unit 302 is provided, and the output of the AND gate 202 is input to the “1” search unit 301 and the output of the AND gate 203 is input to the “0” search unit 302. As a result, each of the search units 301 and 302 sequentially outputs the corresponding pattern number k and inputs it to the counting unit 10. At this time,
It goes without saying that the outputs from the search units 301 and 302 are processed so as not to overlap in time.

Here, as in the first embodiment, it is assumed that the binary data patterns are the five types shown in FIG. 4 and the binary input data patterns are the patterns shown in FIG. At this time, the data search means 2C determines that the binary input data pattern is 100
Since the bit position is 01001, 0, 4, and 7 are output from the AND gate 202 as bit positions where the data value is "1", input to the "1" search unit 301, and the bit position whose data value is "0". Positions 1, 2, 3, 5, 6
Is output from the AND gate 203 and "0" is input to the search unit 302.

Thus, the data pattern search means 3
C outputs a pattern number k of a binary data pattern whose data value at the same bit position as the output of the data search means 2C is "1" or "0".

That is, according to Tables 1 and 2, the data pattern in which the 0th bit is “1” is 1, 3, 4, 1
The data pattern whose bit is “0” is 3, 4, 5,
Data patterns in which the second bit is “0” are 2, 3,
The data pattern in which the fourth, fifth and third bits are “0” is the data pattern in which the fourth, fifth and fourth bits are “1”, the data pattern in which the fourth, fifth and fifth bits are “0” is three, The data pattern in which the fourth, fifth, and sixth bits are “0” is 2, 3, 4, 5, and the data pattern in which the seventh bit is “1” is 2, 4, so that k = 1, 3, 4,. 3, 4,
5, 2, 3, 4, 5, 4, 5, 3, 4, 3, 4, 5,
2, 3, 4, 5, 2, and 4 are sequentially input to the counting means 10.

The count enable decoder 4 of the counting means 10 outputs an enable signal to the counter 9 _k with the same number as the output of the data pattern searching unit 3C. Therefore, once for counter 1, three times for counter 2, six times for counter 3, eight times for counter 4, and five times for counter 5.
Since times enable signal is input, the final value of the counter, the counter 9 ₁ 1, the counter 9 ₂ 3, counter 9
₃ 6, the counter 9 ₄ 8, counter 9 ₅ becomes 5.
Therefore, when both the data values “0” and “1” are to be calculated, it can be understood that the data pattern 4 is the pattern having the highest similarity.

It is of course possible to apply this embodiment to the second embodiment shown in FIGS. When the output of only the AND gate 201 is used in FIG. 7, the data value "1" is used as described in the first and second embodiments.
Only the target device, and AND gate 20
When only two outputs are used, as described in the third embodiment, the device is designed for only the data value "0".

(Embodiment 5) FIG. 8 shows the data pattern search means 3 used in FIGS. 1 and 2 or FIGS. 5 and 6.
FIG. 9 is a block diagram showing the configuration of A, 3B and 3C. FIG. 9 shows the data storage states of a memory 31 (third memory) and a memory 32 (fourth memory) used for the data pattern search means 3A, 3B and 3C. It shows.

The memory 32, which is the fourth memory, is divided into regions as shown in FIG.

In [0], the pattern number k of the binary data pattern in which the data value of the 0th bit counted from the first bit is “1”, and in the area [1], the data value of the first bit counted from the first bit is “ 2 which is 1 "
The pattern number k of the value data pattern is stored, and the pattern number of the binary data pattern whose data value at the m-th bit counted from the first bit is “1” is stored in the area [m].

The leading addresses correspond to 0 to N corresponding to [0] to [m]. End data De indicating the end of each area is stored at the end address of each area, and the memory 31 as a third memory corresponds to addresses 0 to m as shown in FIG. The first address of each of the 32 areas is stored. The bit position output from the data search means 2A becomes the address of the memory 31, the head address of the specific area of the memory 32 is read from the memory 31, and the other address of the specific area is changed to the end data D by the stepping means 30.
It is formed while sequentially stepping up to the address where e is stored.

In the above configuration, when the binary data patterns are the five types shown in FIG. 4 and the binary input data patterns are the patterns shown in FIG. Shown in

Hereinafter, a more specific description will be given using the binary input data pattern and the binary data pattern shown in FIGS. Since the data search means 2A outputs the number of the data value "1" of the binary input data pattern counting from the first bit, the data search means 2A outputs 0, 4, 7 to the input data 10001001 shown in FIG. Are output in order. Therefore, 0 is first input to the data pattern search means 3A as the memory 31 address. This memory 31
Since the start address of each area of the memory 32 is stored in the area of the memory 32, the input of the above address causes the selection circuit 33 to input a 0 from the address 0 of the memory 31, that is, an area where the value of the 0th bit is “1”.

The head address of [0] is output.

The selection circuit 33 selects the memory 31 side as an initial state, and 0 is output from the memory 31.
Is input to the first buffer, and the value 0 is stored in the memory 32.
Address value. Here, as shown in FIG. 11 (FIG. 10), the area of the memory 32 is

In [0], since the pattern number k of the data pattern whose data value of the 0th bit counted from the first bit is “1” is written, it corresponds to the data pattern 1 in response to the input of the address 0. The number k = 1 is output and stored in the second buffer 36, and the content is output to the counter 10 at the next stage.

Area of the memory 32

The address [0] is incremented by the stepping means 30 to the last address of the area as follows. That is, the selection circuit 33 selects the incrementer 34 side in accordance with the output of the second buffer 36. In this state, the output of the first buffer 35 (input to the memory 32) is also input to an incrementer 34 constituting the stepping means 30, where it is incremented and again passed through the memory 32 via the selection circuit 33. Is input to Thereby, the memory 3
2 becomes 1 and k corresponding to the data pattern 3 stored at address 1 of the memory 32
= 3 is output from the second buffer 36.

In this manner, the pattern number in which the 0th bit is “1”, that is, the area of the memory 32

The pattern numbers k = 1, 3, and 4 stored in [0] are sequentially output. Next, the area of the memory 32

When the end mark De is output from [0], the selection circuit 33 again selects the memory 31 side, and the data next to the address 1 of the memory 31, that is, the address 4, is input. Then, the top address of the area 4 of the memory 32 in which the pattern number k whose 13th bit is 1 is stored is output. As a result, the pattern numbers k = 3 and 4 are sequentially output from the area 4. In this way, the pattern number k is sequentially processed and the pattern number k whose bit corresponding to the 0th, 4th, and 7th bits is "1" is output, and the next stage counting means 10 shown in FIG. 1, FIG. 2 or FIG. Will be entered.

The above example is limited to the case where the data value to be determined is "1" in the first and second embodiments, but the data value to be determined is "0" in the third embodiment. Of course, it can be applied to the case of. In this case, each area of the memory 32

[0] to [m] store a pattern number in which each bit position 0 to m is "0".

The leading addresses of [0] to [m] are stored corresponding to the addresses of 0 to m.

Further, the present invention can be applied to the case where the data values to be determined shown in the fourth embodiment are "1" and "0". In this case, a search unit (eg, 301 in FIG. 7) including the memories 31 and 32 corresponding to the data value “1” and the stepping means 30 and the memories 31 and 32 corresponding to the data value “0” and the stepping means 3
0 (for example, 302 in FIG. 7).

Further, in the above, the input data of m bits is 8 bits.
Although only the case of bits has been described, it is needless to say that the present invention can be applied to a case where m bits are two-dimensional (i × j) or three-dimensional (i × j × k).

[0053]

[Table 1]

[0054]

[Table 2]

[0055]

As described above, according to the present invention, the binary pattern matching for calculating the number of coincidences of the bit whose value is "1" or "0" between the binary input data pattern and the binary data pattern is performed. The amount of calculation at the time of performing can be reduced, and data processing can be made extremely efficient.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an embodiment of the first invention.

FIG. 2 is a more detailed configuration diagram of one embodiment of the first invention.

FIG. 3 is a diagram showing an example of a binary input data pattern.

FIG. 4 is a diagram showing five examples of binary reference data patterns;

FIG. 5 is a configuration diagram of an example of the second invention.

FIG. 6 is a more detailed configuration diagram of one embodiment of the second invention.

FIG. 7 is a partial configuration diagram of an embodiment of the fourth invention.

FIG. 8 is a configuration diagram of a data pattern search unit used in the present invention.

9 is a configuration diagram of a memory 32 in FIG.

FIG. 10 is a configuration diagram of a memory 31 in FIG. 8;

FIG. 11 is a diagram showing a data storage state of memories 31 and 32 in FIGS. 9 and 10;

FIG. 12 is a configuration diagram of a conventional data processing device.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 first memory 2A, 2B, 2C data search means 3A, 3B, 3C data pattern search means 4 count enable decoder 5 second memory 9 _k (9 _{1 to} 9 _n ) count means 10 count means 31 third memory 32 fourth memory 110 increment means

Claims (5)

[Claims] 1. A data processing apparatus for performing pattern matching between an m-bit binary input data pattern and a m-bit binary reference data pattern, the data value of the m-bit binary input data pattern Is 2
A data search unit that searches for a bit position of a bit that is one of the values, based on an output of the data search unit, among the binary data patterns to which first to n-th numbers are assigned A data pattern search unit that outputs a binary data pattern number in which a data value at the same bit position as the output of the data search unit is any one of the above-described two values; A data processing device comprising: a counting unit that counts the number of times a number is output. 2. The count means comprises a counter corresponding to each of the binary data patterns, and a count enable decoder for enabling the corresponding counter based on a pattern number output from the data pattern search means. The data processing device according to claim 1. A second memory having an address value of a pattern number output by the data pattern searching means; and adding one to the content corresponding to the address when the address is input. 2. The data processing apparatus according to claim 1, further comprising increment means for storing the data at the same address again. 4. The data pattern search means includes an area corresponding to each bit of 0 to m, and stores a pattern number in which a data value of a bit corresponding to each area is one of two values. A fourth memory, a third memory in which a bit position output by the data search means is used as an address, and a start address of each area of the fourth memory is stored in each address; 2. The data processing apparatus according to claim 1, further comprising a stepping means for sequentially stepping from a first address of a specific area of the fourth memory to a final address of the area. 5. A method according to claim 1, wherein said data search means searches for both data values of the binary input data pattern, and said data pattern search means searches for a pattern number corresponding to both of said binary data values. Item 5. The data processing circuit according to items 1 to 4.