JPS5957284A - Image information processor - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] The present invention relates to an image information processing device, and particularly to an image information processing device that combines image information created using an arithmetic processing device such as a microcombinator with reproduced video information reproduced from a recording medium. The present invention relates to a useless image information processing device.

Conventional image information processing devices for image synthesis include:
There are various devices that create composite video signals by combining or switching signals at the video signal stage. A schematic block diagram of the synthesis apparatus shown in FIGS. 1(5) to 1 is shown.

In FIG. 1, for example, a color video signal source 101 and a monochrome (black and white) video signal source 102 are synchronized with the vertical and horizontal synchronization signal rates by a synchronizer 103 and mixed by an adder 104. be. ) in the same figure, two color video signal sources 101
, 105 are synchronized by performing time axis correction at the subcarrier signal rate by a synchronization device 103, and selectively derived as appropriate by a video switcher 106, thereby synthesizing a color image.

In the same figure (in Q, two video signal sources 101 and 105
In this method, the signal from one of the sources 105 is synchronized with the signal from the other signal source 101 by a synchronizer 103, and is selectively derived by a switcher 106. In FIG. 6, for example, the reproduced video signals f from two VTRs (video tape recorders) 107 and 108 are each T
BC (Time Base Collector) 109.

110 to perform time axis correction at the subcarrier signal rate and perform phase synthesis, the signal is selectively outputted by the switcher 106. Furthermore, in the one shown in FIG. 6, the outputs of the two signal sources 101 and 105 are converted to
2 and digitized each to TBC113.

After performing time axis correction via 114, the synthesizer 11
5 and is digitally synthesized. After that, D/A
In this method, the video signal is converted into an analog video signal using a (digital/analog) converter 116.

In this way, conventional compositing methods basically perform compositing at the video format stage before inputting it to a display device such as a CRT (cathode ray tube), or digitize it using a high-speed A/D converter and perform calculations. It is synthesized after processing.

Since the conventional device is configured as described above, extremely accurate time axis correction is required. Furthermore, when combining color signals, accurate phase matching must be performed because even the slightest phase error will result in hue fluctuations.
Malfunctions may occur due to the influence of temperature characteristics and changes over time.Furthermore, in order to prevent these adverse effects,
This method requires a large number of compensation circuits, and has the disadvantage of increasing costs and decreasing reliability due to an increase in the number of components.

The present invention has been made in view of the above-mentioned drawbacks of the prior art, and an object thereof is to provide an image information processing device capable of image synthesis with an extremely simple configuration.

The image information processing device according to the present invention synthesizes first image information in the form of a composite video signal and second image information that has been subjected to arithmetic processing by an arithmetic processing device (including a microcomputer, etc.) and displays an image. The object is a device that displays the first image information on the image display device, and includes a conversion means for converting the first image information into a predetermined luminance component for displaying on the image display device, and an output of the conversion means and the second image information. It is characterized by having a selection means for selectively outputting and supplying the output to the image display device.

Embodiments of the present invention will be described below with reference to the drawings, but in order to facilitate understanding of the present invention, a case where the present invention is applied to a video game will be described.

FIG. 2 is a schematic block diagram of a video game device configured using the present invention, in which a game player is
The user makes a judgment according to the image shown on the screen, and operates the information sword device 2, which is composed of switches, potentiometers, etc., in accordance with the judgment.

The information obtained from this input device 2 is converted into a signal form capable of digital information processing by a decoder 3, and is supplied to a control device 4, which is comprised of, for example, a microcomputer. This microcomputer 74 mainly consists of a cPU (central processing unit) 5, and receives information supplied by the decoder 3 based on a program stored in advance in a storage means 6 consisting of a ROM (read only memory) or the like. Process. CPU
5 configures the results of predetermined calculation processing as an image displaying the game development, and sends the calculation results to the video generator 8.

The information processed by the CPU 5 in accordance with the program according to the signal from the decoder 3 is primary display information that directly contributes to the development of the game, and secondary display image information that does not directly contribute to the development of the game is obtained. Therefore, for example, a VDP (video disc player) 9 is used as an external memory.

The secondary image information recorded in this VDP 9 includes background images and message information that do not directly contribute to the development of the game. recorded on a video disc. VD as external memory 9
The P output is supplied to demodulation circuit 10. External memory device 9
The operation is controlled according to a control signal from the CPU 5.

The output of the demodulation circuit 10 is supplied to a video generator 8 and a detector 11. The output of the reference signal generating circuit 12 and the timing signal from the CPU 5 are further input to the detector 11 . On the other hand, the demodulation circuit 10 outputs a synchronization signal of reproduced color video information, and is supplied to the CPU 5.

The operation will be explained in detail below. The FM color video signal reproduced from the video disk is once FM demodulated in the demodulation circuit 1O, and after the synchronization signal is separated, this synchronization signal is decoded into an appropriate form and supplied to the CPU 5, thereby allowing the external memory device 9 and the CPU Synchronization with the output that has been subjected to arithmetic processing is established.

Furthermore, in the demodulation circuit 10, the color video signal is separated into information signals of R (red), G (green), and B (blue), which are the three primary colors in video. The separated KGB information signal is supplied to a video generator 8, where the CPU
The image information is combined with the image information calculated by 5 and displayed on the image display device 1.
The image is displayed.

On the other hand, the RGB information signal is further supplied to the detector 11, where it is compared with a reference signal from the reference signal generation circuit 12, and the hue of the image at a predetermined timing supplied from the CPU 5 is detected. . Furthermore, in the video generator 8, the output of the demodulation circuit 1° and the calculation output from the CPU 5 are directly combined.

FIG. 3 shows a specific example of the configuration of the detection circuit 11. That is, the RGB information signals outputted from the demodulation circuit 10 are respectively supplied to the first gate array 13 constituted by the ANDGs 13α to 13h connected in parallel. Each gate) 13cL to 137L is input via an inverter in the necessary order, and depending on the RGB information pattern, one of the AND gates 13c to 13h outputs logic "'1" and the other gates output logic "'1". All output logic "φ". and gate 13
The outputs of α to h are 9 as shown in the truth table at the end of the detailed explanation. Each output of the first gate array 13 is supplied to one input terminal of the analog gates i4a to 14h constituting the second gate array 14, respectively. This AND gate 14a
The reference signal generation circuit 12 is connected to the other input terminal of ~141L.
output is supplied. The output pattern of the reference signal generating circuit 12 is determined by a control signal from the CPU 5.

All output terminals of AND gates 14α to 14A are OR
It is connected to the input terminal of the circuit 15, and the output of the OR circuit 15 is supplied to the other input of an AND gate 16, which receives the timing information signal from the CPU 5 as one input.

The output of this AND gate 16 is sent to the CPU 5 as a command signal.
It is supplied to.

Next, an example of the operation of this detection circuit will be explained. For example, when the external memory 9 outputs color video information corresponding to red, the RGB information output from the demodulation circuit 10 becomes the pattern indicated by A in the truth table. Therefore, only the AND gate 13d of the first gate array 13 outputs the logic @VJ, and all the other AND gates output the logic "φ". Of these, only those supplied to 14d are set to logic tl I II, and the others are set to logic ``φ'
'', the logic of the AND gate 144 is established and the logic 111'' is output. If the output of the reference signal generation circuit 12 is maintained in this state, the OR will be performed every time the external memory 9 outputs information corresponding to red.
An output corresponding to the logic °'1''' is supplied from the circuit 15 to one output of the AND gate 16.The output pattern of the output of the reference signal supply means 11 is controlled according to the color to be detected.Here, From the other input of the AND gate 16, the CPU 5
A signal corresponding to logic ``1'' is supplied only during a predetermined period determined and output by .

When the AND gate 16 outputs a signal corresponding to the logic "l", a command signal is supplied to the CPU 5, and predetermined processing is performed within the CPU 5. The output from the demodulation circuit 10 is used in the video generator 8 to implement the present invention. A video switch 17 of the type shown in FIG.
It is combined with the image information from U5.

That is, the switch elements 17α in the normal switch 17
C selects the RGB information signal side supplied from the demodulation circuit 10, but when any of the RGB information is supplied in the output from the CPU 5, the OR circuit 18 detects this, and during this period each RGB from CPU5 for elements 17α to C
It switches to select information.

Note that the control signal is sequentially transmitted to the reference signal generation circuit 12 at regular intervals.
14 (L to 14h inputs are made to correspond to the logic t+1#, and the AND gate 16
The timing signal supplied to the period logic to I n
If the color is made to correspond to the output of the AND gate 16, the color at that time can be detected based on the timing at which the output of the AND gate 16 is generated.

Further, a game device to which the present invention is applied, in which a plurality of signals corresponding to logic "1" are supplied to the second gate array 14 as the output of the reference signal generating circuit 12, will be described in detail with reference to the drawings.

FIG. 5 shows a screen reproduced on the image display device 1 based on image information supplied from the external memory device 9. The targets 19α to 19d appearing on the screen have different colors, and move randomly as time passes. Further, the color of the target 19cL-d is also different from the color of the background. FIG. 6 shows a screen created from the image information supplied by the CPU 5, with a score display section 20α showing the score at the upper left corner and a cursor section 20b at the center. The score display section 20α displays the scores obtained as the game progresses, and the cursor section 206 can be freely moved on the screen by operating the input device 3. The image in the external memory device 9 and the image from the CPU 5 are synthesized by the synthesis circuit shown in FIG. Now, looking at the scanning line is set to detect red color, the output signal from the OR circuit 15 is as shown in Fig. 7 (1).
) and is supplied to one input of the AND gate 16.

Here, depending on the position of the cursor 20b, CP, U5, and timing signals (Cf in FIG. 7) are supplied to the other input of the AND gate 16, but since the logic does not hold with the output signal of the OR circuit 15, , no command signal is generated (Fig. 7 (
(see g)).

On the other hand, as shown in FIG. 8(α), when the cursor section 20b is positioned on the target 19c, the timing signal
The timing of occurrence of the command signal (see Figure 8(a)) changes, and a command signal is obtained (see Figure 8(σ) 8). This command signal is sent to the CPU
5, the score of the game is counted, and the score displayed on the score display section 20α changes (FIG. 8(α)
reference). It is also possible to detect the υ color using the method described above and change the score value for each target. Similarly, it is also possible to configure the game so that the game ends when the cursor portion 20b hits a target of a specific color.

Further, in the above embodiments, a video game device has been described, but the same applies to learning devices and the like.

For example, JP-A-54-157027 (Japanese Patent Application No. 53-6
5371), when inputting the answer to a question, targets 21α to C of different colors are displayed in front of the choices as shown in FIG. Depending on the location, it is possible to have the CPU confirm the answer of the answerer.

Furthermore, the information obtained from the external memory device may be color video information with arbitrary brightness, lightness, and saturation, or it may be a monochrome information signal.The information from the CPU may also be monochrome information. good. In the former case, it is sufficient to slice the level of the RGB information signal at a predetermined comparison level and supply it to the detection circuit. Thus, according to the present invention, as shown in FIGS. Since the configuration combines the two image information to be imaged not in the form of a video format signal but as luminance components corresponding to each of the three primary colors, for example, image synthesis is possible extremely easily, and the device can be made smaller and cheaper. High reliability can be expected, and this type of image information processing device can be widely used in consumer equipment.

The composite output obtained by the present invention (the R, G, and B outputs of the video switch 17 in FIG. 4) is a luminance component corresponding to each of the three primary colors, so it can be used as is as a CRT drive signal. be able to.

Of course, the configuration of the above embodiment can be modified in various ways.

truth table

[Brief explanation of the drawing]

FIG. 1 is a block diagram of various conventional image synthesis devices, FIG. 2 is a block diagram of an example of a video game to which the present invention is applied,
3 is a diagram showing one example of the detection circuit in the block of FIG. 2, FIG. 4 is a circuit diagram of one embodiment of the present invention, and FIG. 5 is a diagram showing one mode of image display from an external memory. Figure 6 is C
FIGS. 7 to 9 are diagrams illustrating one mode of image display from the PU, and are diagrams illustrating one mode of a composite image. Explanation of symbols of main parts 1... Monitor 5... CPU 8... Video generator 9... VDP 10... Demodulation circuit 17...
Video switch jJ@, k Pioneer Video Co., Ltd. agent
Patent Attorney Motohiko Fujitoshi #5vJ Hata 7 Diagram (ln'JI>6 Diagram #8 Diagram (3)

Claims (1)

[Scope of Claims] Q) First image information in the form of a fixed video signal and second image information processed by an arithmetic processing device are image-composed and displayed on an image display device. An image information processing apparatus comprising: a conversion means for converting the first image information into a predetermined luminance component for displaying on the image display device; and an output of the conversion means and the second image information. an image information processing apparatus, comprising a selection means for selectively outputting and supplying the output to the image display apparatus. (2) The first image information includes hue information, and the converting means is configured to output three types of luminance components corresponding to the three primary colors of light, respectively. The image information processing device described in . (3) The second image information is three types of binary information corresponding to the three primary colors of light, and the selection means determines that at least one of the three types of binary information exists in the image information. The image according to claim 2, characterized in that the image is configured to select the three types of binary information when the information is significant, and select the three types of luminance components when the information is residual. Information processing device 0