JPS5942686A - Information processing device - Google Patents

Abstract

PURPOSE:To facilitate the control between a store buffer and a buffer memory and to extract the capacity of read/write operation at its maximum, by providing the store buffer where write requests to a main storage device and the buffer memory are stored, and providing a means, which compares all write addresses stored in the store buffer with a read address attendant on a read request, in the store buffer. CONSTITUTION:A store buffer 13 is arranged in the preceding stage of a stage where the write request from an operation processing part 11 is executed to a buffer memory 12 and a main storage device 2. In this constitution, the store buffer 13 is the object of indexing also in case of a read request. For this indexing, the first comparing means which compares write addresses with read addresses in a block unit to detect their coincidence and the second comparing means which compares them in a preliminarily set write data width unit to detect their coincidence are provided. Thus, the store buffer is swept up easily during the block transfer, and sweeping-up of the store buffer for the read request is restrained to the minimum to transmit read data to a request source quickly.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an information processing apparatus having a buffer memory and a store buffer for storing write requests to a main memory.

<Prior Art> In an information processing device having a buffer memory, reading instructions and reading operands from the arithmetic processing unit of the processing device,
Access the buffer memory for reading and writing data such as writing. If there is no sofa memory,
Since the main storage device, which is slower and has a larger capacity than the buffer memory, is constantly accessed, the access time is long and no improvement in performance can be expected.

When there is a read request from the arithmetic processing unit, the buffer memory is accessed, and if the desired data exists, the data can be retrieved directly from there; starting the slow main memory is done by loading the desired data into the buffer memory. This occurs only when there is no data and one block of data containing the desired data is transferred from the main memory to the buffer memory.

In response to a write request from the arithmetic processing unit, ・<The sofa memory is a copy of the main memory, and ・(This would likely cause a discrepancy in the data content between the sofa memory and the main memory, so
A method is used in which the same data is written to the main memory at the same time as a write operation is performed to the buffer memory, and this method is called store-through.

That is, in a write operation, it was always necessary to start up the slow main storage device.

In order to avoid this, when a write request is received from the processing unit, the write operation is limited to the buffer memory for the time being, and the replacement is performed at an appropriate time, for example, when one block of buffer memory needs to be replaced. If the target block has been rewritten, there is also a method of writing that block to the main memory.

This method is called store swapping, but in systems where multiple information processing devices share the memory area of the main memory, it is difficult to synchronize data in the main memory and buffer memory. That is, when a read request for one block is made to the main memory, it is necessary to constantly check the buffer memories of other information processing devices to see if there is flf(7) data. From the above, most of the write methods currently in use are store-through methods.

A write operation to a buffer memory takes more time than a read operation due to its control and the characteristics of the RAM (random access memory) element used. That is, the write operation has a longer cycle time than the read operation. It's Tong.
In the store-through method, it is necessary to store data into the buffer memory and the main storage device at the same time, and if the main storage device cannot accept a write request, the processing of the information processing device must be temporarily stopped and corrected.

In order to solve the above problem, a store buffer is provided in the information processing device to hold write requests from the arithmetic processing unit, and the operation of the write request is terminated once it is stored in the store buffer. Receives the next request from the processing unit. The store buffer finds free time in the buffer memory and main memory and executes the write operation. The store buffer (is treated as part of the buffer memory, and is naturally referenced in response to a read request from the arithmetic processing unit.

In order to improve performance, it is necessary to supply read data to the arithmetic processing unit as quickly as possible.

This indicates that it is necessary to minimize the draining of the store buffer due to read requests. ′! .

If the desired data resulting from a read request does not exist in either the buffer memory or the store buffer, a block transfer is performed, but there is a possibility that a write request for the same block internal address exists in the store buffer. It is necessary to either stop purging of the store buffer or delete the registration in the buffer memory when the same block is encountered, and this has been implemented.

<Summary of the Invention> An object of the present invention is to facilitate control between the store buffer and the buffer memory in an information processing device equipped with a backup memory and a store buffer, and to maximize the performance of read and write operations. It is said that

According to the present invention, in an information processing apparatus having a buffer memory connected to a main memory and holding a copy of the memory contents of the main memory in units of blocks, write requests to the main memory and the buffer memory are stored. The store buffer has a means for comparing all the write addresses stored in the store buffer with the E1 address associated with the read request, and the comparing means has a A first comparison means that compares units to detect a match, and a preset write data '1h.
rr IP and a second comparison means for comparing and detecting a match (1.

<Embodiment> The present invention will be described below with reference to the drawings.3. Referring to FIG. 1, an information processing device 1 to which the present invention is applied is connected to a main storage device 2 via an interface 3. ing. This information processing device 1 includes an arithmetic processing section 11,
The arithmetic processing unit 11 sends read and write requests with addresses to the buffer memory 12 and the store buffer 13 (1), and write data is provided from the arithmetic processing unit 11 to the store buffer 13 .

In the present invention, the store buffer 13 is arranged in a stage before a write request from the arithmetic processing section 11 is executed to the buffer memory 2 and the main storage device 2. The write data from the arithmetic processing unit 11 is usually given later than the write request and the accompanying write address, so by arranging it as described above,
This delay can be absorbed. If this configuration is adopted, the store buffer 13 will also be indexed when a read request is made.

FIG. 2 shows a detailed example of the buffer memory 12 and store buffer 13 in FIG. 1. Store buffer 1 in Figure 1
3 is divided into an address section 13-1 and a write data section 13-2 indicated by broken lines in FIG. In this embodiment, one block of the buffer memory 12 is 64 bytes, and the write data width, the read data width, and the data width of the interface 3 in FIG. 1 are all the same, which is 8 bytes.

Therefore, the block transfer from the main storage device 2 to the buffer memory 12 is performed eight times. This information processing device 1 operates at a clock cycle, and when it requires one clock, it is called IT, and when it requires two clocks, it is called 2T, and so on.

At the time of a read request, a read address is set in the register (FAI) 31 from the arithmetic processing unit 11 via the first switching circuit 41. The read address written in register 3J is
The storage section of the buffer memory 12 is accessed. This storage sound 15i is the address array 21 (abbreviated as A).
A) and a data array 22 (abbreviated as DA). The address array 21 stores the tiles of each block, and the data array 22 stores the data of each block.

The third comparison circuit 46 detects a match to determine whether or not there is a block containing the scattered address in the address array 21, and registers (AHR) 3 at the next clock.
Set to 6.

Store buffer address register (STB-ADR) 2
3 stores the incision address accompanying the write request,
All the input addresses stored in this 5TB-ADR 23 are compared with the input and output addresses by the first comparison circuit 44 and the second ratio conversion circuit 45, and the results of these comparisons are used in the next clock. Each register (SHRI) 3
7 and register (SI(R2)) 38. The first comparison circuit 44 performs a comparison in units of blocks, that is, units of 64 bytes, and the second comparison circuit 45 performs comparison in units of 8 bytes, which is the read and write data width. Make a comparison.

The read address set in the register (FAI) 31 is transferred to the register (PA2) 32 at the next clock, and the results of the first to third comparison circuits 44 to 46 are set in registers 5HRI, 5HR2 and AHR, respectively. Further, if a match is detected by the third comparison circuit 46, the read data width indicated by the read address is set in the register (RDR) 34.

This determines the operation for the read request. This operation is one of the following four.

Operation: The write request stored in the varnished buffer 13 is flushed out, and then block transfer is performed.

Operation 2: Send the read data set in the register (RDR) 34 to the requesting arithmetic processing unit 11.

Operation 3 Block transfer is performed without cleaning out the varnish buffer 13. .

Operation 4: Flush out the write request stored in the painted buffer J3, and then read the buffer memory 12.

The operation for the read request is determined by the register S](HR1
', 5HR2 and AHR contents.

FIG. 3 shows the operation of the three registers 36-38. The register SHR1 stores the result of the first comparing means which compares and detects a match at the block rii, and the result of the third comparing means is stored.
In the figure, if a match is detected, it is represented by "T-bi", and if there is a mismatch, it is represented by "M". 4r>3 The expressions in the figure are the same.Register A I-I Ru Indicates the presence or absence of a block containing the read address in the buffer memory 12; ;3
The combination is expressed as "M". Here, register 5HR27
)K”H”, register SHR1u” I-1
” and register S HR1 is “M'V), then v
Sister 5J-TR2 is also u MII.

The reason why the processing for the read request is determined to be operation 1 is expressed in a logical formula as 5HRI-AHR. Since the desired data does not exist in the buffer memory 12, block transfer should be performed, but if the data is transferred to the same block internal address. Since there is a write request, the block transfer is performed after the store buffer 13 is flushed out. This guarantees against flushing out the store buffer 13 during block transfer. That is, when the store buffer 13 is flushed out during block transfer, after the write data is written in the buffer memory 12, it is rewritten with old data from the block transfer, resulting in data conversion 4.

What is determined to be action 2 is 5HR2 when expressed by a logical formula.
- AHR, the desired data exists in the buffer memory 12, and there is no write request for the same address in the store buffer 13. In operation 2, buffer memory 12
The contents of the register RDR in which the data read from the register RDR is stored are sent to the arithmetic processing unit 11 that is the request source.

What is determined as action 3 is 5HRI when expressed by a logical formula.
- AHR, which issues a block transfer request to the main storage device 2.

What is determined for action 4 is 5HR when expressed by a logical formula.
2. In AHR, the desired data exists in both the buffer memory 12 and the store buffer 13, but the store buffer 13
Since the write data is the latest, after cleaning out the store buffer 13, the buffer memory 12 is read out again.

Now, returning to Figure 2, we will explain block transfer by DJ JJ. Starting from register PA2 1. ζ (When a block transfer request is issued to device 1q2, main storage device 2
The information necessary to receive read data from is stored in a buffer (RZB) 25. When retrieved data is sent from the main storage device 2, it is set in the register (WDR) 35 through the third switching circuit 43. At the same timing, the read address stored in the buffer (RZB) 25 is set to the register FAI, the contents of the register WDR are written to the data array 22, and set to the register (RDR) 34 through the second switching circuit 42.
Sent as a reply to the requester. In this embodiment, reading from the main storage device 2 is performed eight times in one block unit.

Next, the operation of a write request will be explained.

For a write request from the arithmetic processing unit 11, the write address is set in the register (PAL), and the 5TB is processed at the next clock.
- Stored in ADR23. To flush out the store buffer 13, the write address is set in the register FAI, and the address previously set in the register 1) A1 is evacuated to the register (BAR) 33. Then, the address array 21 of the buffer memory 12 is indexed, and the third comparison circuit 46
Check whether a block containing the write address exists. Advance the clock and set the result in register A]■H. In addition, set the write address in register I)A2, and the write data is stored in the store buffer data register (
SrI2-WD) 24 is set to the register WDR via the 2153 switching circuit 43.

At this point, 1.t, the input request to the main memory device 2 is transmitted,
Also, the register A-- HR is checked, and if a block including the write address exists, 'tφ in the register WDR is written to the data array 22.

FIG. 4 shows an example of a time chart when the store buffer 13 is flushed out. It is assumed that two write requests Sl and S2 exist in the store buffer 13, and the timing t
p is in the state before sweeping, and at timings t1 and t3, a write address is set from the 5TB-ADR 23 to the register PAL, and t11 is executed. This is a case where the write request hits the SIU buffer memory 12 and the write request S2 misses.

Incidentally, the trigger for flushing out the store buffer 13 is not only in the case of operations 1 and 4 caused by the read request, but also when the store buffer 13 becomes full and when the register PAL is empty.

The above is a description of the embodiments of the present invention.

Incidentally, the state of the buffer memory during block transfer is in an unstable state in which a directory is registered in the address array 21, but no data is yet prepared in the data array 22. In addition, block transfer requires a long access time because the main storage device 2 is accessed.

However, according to the present invention, even if the store buffer 13 is flushed out using the empty space, no inconsistency occurs in the buffer memory 12. For example, if it takes 10T to send a block transfer request to the main storage device 2 and the first read data is sent, and 2T to register the directory in the address array 21, and if the capacity of the store buffer 12 is 4 entries, then one All write requests in the store buffer 13 can be flushed out during block transfer.

Further, when a read request is made, by minimizing the amount of data being purged from the store buffer, delays in trial data can be prevented.

According to the present invention, the store buffer can be easily flushed out during block transfer, and the store buffer flushing due to read water absorption can be kept to a minimum and read data can be quickly sent to the request source.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of an information processing device 6 of the present invention, FIG. 2 is a block diagram showing a detailed example of the buffer memory and store buffer in FIG. 1, and FIG. The illustrated diagram, FIG. 4, is a time chart showing an example of purging the store buffer. 1: Information processing device, 2: Main storage device, 3: Ink 7ff
11: Arithmetic processing unit, 12: Buffer memory,
13 varnish buffer, 13-1: address section of store buffer, 13-2 1-inclusive data section of varnish buffer, 21 near address array, 22: data array, 23
: ST]3-AI)R. 24: 5TB-WD, 2s: Buff 7RZB. 31-38: Register, 41-43: Cutting circuit 44-4
6: Comparison circuit. Patent Applicant NEC Corporation Agent Taku Kusano Figure 71

Claims (1)

[Claims] (1) In an information processing device having a buffer memory connected to a main memory and holding a copy of the memory contents of the main memory in units of blocks, a request for retrieval to the main memory and the buffer memory is stored. The store buffer has a means for comparing all write addresses stored in the store buffer with a read address associated with a read request, and this comparing means compares block by block. An information processing apparatus comprising: a first comparing means for detecting a match; and a second comparing means for comparing in preset write data width units to detect a match.