JPS63247852A - Cache memory control method - Google Patents

Abstract

PURPOSE:To omit an invalidating process required for deletion of the discordance among plural maps of memories by giving a direct access to a main memory without carrying out a copying action to a cache memory against a common area. CONSTITUTION:A cache memory 4 and a memory control unit (MMU) 6 are provided. The MMU 6 consists of an address conversion buffer (TLB) 600, a TLB hit comparator 610 and an MMU control part 610. The TLB 600 serves as a memory that converts a logical address 85 into a physical address 86 at a high speed. This memory consists of a V bit showing the validity, a directory 602 for detection of the coincidence, a common bit 603 showing a shared area, etc. The MMU 6 also performs the protection check to the area received an access simultaneously with conversion of addresses.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for controlling a cache memory in a multiprocessor system.

[Conventional technology]

In order to improve the processing power of a computer, a system with a multiprocessor configuration in which a plurality of processors are connected as shown in FIG. 2 has been considered. According to this configuration, the four processors 31, 32, 33, and 34 can operate in parallel, and it is expected that the processing capacity will be four times higher than when there is only one processor. In this system, data exchange between processors takes place via a main memory 2 connected to a system bus 1. In this case, since each processor competes for access to the main memory 2, the amount of traffic on the system bus 1 increases, equivalently resulting in an increase in memory access time, and the throughput of the system decreases.

Therefore, each processor 31, 32, 33.34 prepares a cache memory 41, 42, 43.44, and has a copy of the main memory 2 in the cache memory so that the processor 31, 32, 33.34 can access the main memory 2 via the system bus 1. Reduce the number of accesses. It is said that this makes it possible to reduce the amount of traffic on the system bus 1 and prevent a decrease in throughput.

The problem in this case is that the cache memory 41°42.
43.44, when a copy of the same area exists and the contents of the same area are changed by a certain processor, there will be a mismatch between the cache memories and between the cache memory and main memory 2 despite the copies of the same area. There is a problem that occurs. Therefore, each processor 31, 32, 33 .
34 indicates that the contents of main memory 2 have been changed.
and contact other processors. For example, the cache memory 41 connected to the processor 31 has a copy 4101 of the area 201 in the main memory 2, and the cache memory 43 connected to the processor 33 also has a copy 4101 of the area 201 in the main memory 2.
Consider the situation where you have a copy 4301 of 1. When the processor 31 performs a write operation to the area 201, it rewrites the contents of the cache memory copy 4101 and immediately accesses the area 201 to make the main memory area 201 and the copy area 4101 coincide.

The cache memories 42, 43, and 44 constantly monitor whether other processors are making write access to the main memory 2, and if they have the same copy, erase the contents from the cache memory. This is called cache invalidation.

In the upper case, since the cache memory 43 has the copy 4301, the cache memory 43 invalidates the copy 4301.

Another main memory 2 and cache memory 41.42
, 43.44 are inconsistent, DMA (Dy
In FIG. 2, channel 70. When the file device 75 transfers the file device data 7501 to the main memory area 201, if the cache memory 41 has a copy 4101 of the main memory area 201, the main memory area 201 will be rewritten to the data 7501. On the other hand, the copy 4101 remains the original, and the main memory 2 and cache memory 41 become inconsistent. In order to prevent this, each of the cache memories 41, 42, 43, and 44 must constantly monitor the system bus and perform invalidation processing, as described above.

The above-mentioned problems and solutions in the prior art are discussed in the paper "Cache Memory" by Nagataka and Horikoshi (Information Processing V
o Q24, Na4, pp332-340
) is explained in detail.

[Problems to be Solved by the Invention] All of the problems related to the cache memory control method of a multiprocessor system in the prior art described above arise from the necessity of invalidating the cache memory.
It is as follows.

(1) When rewriting the contents of the main memory, communication access is required to other processors to invalidate copies of the same area in the cache memory. As a result, the amount of traffic on the system bus does not decrease, and memory accesses are blocked by other communication accesses, resulting in an increase in access time and throughput constraints.

(2) It constantly monitors whether or not other processors and input/output devices that perform DMA rewrite the contents of main memory, and when writing is performed to the same area as the area of its own cache memory, the corresponding area is Since the copy must be invalidated, hardware is required to do so,
Furthermore, the processing time of the processor is exceeded, and the rad also increases.

Furthermore, when a cache memory and a processor are mounted on the same chip using VLSI, the signal propagation delay within the same chip becomes smaller in proportion to the degree of integration. but,
Monitoring the system bus requires synchronization with the system bus clock, which reduces the effectiveness of VLSI.

(3) Since the cache memory access for invalidation and the processor's cache memory access compete with each other, the processor's cache memory access time equivalently increases. This reduces the processing performance of the processor.

SUMMARY OF THE INVENTION An object of the present invention is to provide a cache memory control method that does not require invalidation processing when a shared portion is rewritten, and therefore does not generate communication or processing overheads.

[Means for solving problems]

A text area (program, etc.) in the logical space of each processor in a multiprocessor system.

The maps in the main memory of the data area (fixed data, etc.) and the private work area are read-only or accessed by only one processor, so they are shared by multiple processors and are not rewritten. However, the remote control area is a shared area on main memory that is used for communication between processors.
Rewriting is also performed. By focusing on this point, the above object is achieved by directly accessing the main memory without copying the common area to the cache memory.

[Effect]

Since the common area is not copied to the cache memory and exists only in the main memory, there will be no mismatch between maps on multiple memories, and therefore no invalidation processing is required to remove the mismatch. do not. Furthermore, since the common area is only a part of the main memory, not using the cache memory has little effect on memory access speed reduction or bus throughput.

〔Example〕

First, the memory management system that is the premise of the present invention will be explained using FIG. In the figure, logical space 310
0 indicates the logical space of the processor 31, that is, the memory image visible to the program;
00 indicates the logical space of the processor 33. These logical spaces and locations 2 in actual main memory
00 corresponds.

Logical space 3100 includes text area 3110. Data area 3120. It consists of a private work area 3130, a common area 3140, and the logical space 3300 similarly includes a text area 3310, a data area 3320. Private work area 3330. It consists of a common area 334o. Here the text area 3110°33
Reference numeral 10 denotes an area where the instruction code of the program is stored, and data areas 3120 and 3320 are areas where fixed data used in the program are stored. These text areas 3110°3310 are also data areas 312
Both areas 0 and 3320 are read-only areas that cannot be rewritten by a program.

Private work areas 3130 and 3330 are read/write areas such as stack areas used in programs. The common areas 3140 and 3340 are areas used by the processor 31 and the processor 33 for communication such as passing parameters to each other. These private work areas 3130, 3330 and common areas 3140.

3340 is an area for both reading and writing from the perspective of the program.

Each area in the above logical space is allocated to the main memory as follows by an address translation mechanism managed by the system program.

Text areas 3110 and 3310 are allocated to text area 210 on main memory. Data area 3120
．． 3320 is allocated to the data area 220 on the main memory. The text area and data area are read-only and there is no risk of them being rewritten, so the processors 31 and 3
It is allocated so that it overlaps with 3. Private work areas 3130 and 3330 are allocated to main memory work areas 231 and 233, respectively. Since this area is rewritten asynchronously by each processor 31, 33, it is allocated to an independent area. However, common area 3
140.3340 is allocated to the common area 240 of the main memory. This area is an area for exchanging control information between the processors 31 and 33, and is an area that is read and written by both processors.

Applying the above characteristics of multiple virtual memory in a multiprocessor system to cache memory control, we get the following:
It can be seen that if copies of the common area 240 in FIG. 3 exist in a plurality of cache memories 41, 43, a mismatch with the main memory may occur. The read-only and commonly used text area 210 and data area 220 are unlikely to be rewritten, so no mismatch occurs, and the private work areas 231 and 233 are not accessed by other processors, so no mismatch occurs. . Therefore, in the present invention, when accessing the common area 240, the main memory is always accessed without copying from the main memory to the cache memory, thereby eliminating the occurrence of mismatch between the main memory and the cache memory, and processing the invalidation of the cache memory. This made it unnecessary.

Next, examples of the present invention will be described. First, FIG. 4 shows the configuration of one processor portion of a system to which the present invention is applied. This one processor.

It is composed of a processor 3 and a cache memory 4, and the processor 3 has a basic processing unit 5 (BasicPr).
cessing Llnit (hereinafter abbreviated as BPtJ) and memory management unit 6 (Memory Man
management unit (hereinafter abbreviated as MMU). The logical address 85 output from the BPO 4 is converted into a physical address 86 by the MMU 6,
It is connected to the cache memory 4. Also, BPO4
The data bus 75 is directly connected to the cache memory 4. If the cache memory 4 has a copy of the access area from the BPO 4 in itself, it sends the data to the BPO 4 via the data bus 75; otherwise, it outputs an address 84. Desired access information is transferred to the system bus 1 via the data output cuff 4, and copy access to the main memory 2 is performed.

The method of the present invention is realized by the cache memory 4 and MMU 6 in this configuration, and FIG. 1 shows an example of this part. The MMU 6 has an address translation buffer 600 (Translation Lookaside).
The MMU control section 610 includes a TLB hit comparator 610, and a TLB hit comparator 610. The TLB 600 is a memory for converting a logical address 85 into a physical address 86 at high speed, and includes a V bit 601 indicating whether it is valid or not, a directory 602 . Common bit 603 indicating whether the accessed area is a shared area; Read enable bit 604 indicating whether the accessed area can be read. It consists of a write enable bit 605 that indicates whether the accessed area is writable or not, and a portion 606 that stores a physical address.

When a memory access is performed from BPO4, the intermediate part 85M of the issued logical address 85 is used to access the TL.
The comparator 61 reads the contents of B600 and checks whether the upper part 85U and the contents of the directory 602 match.
The determination is made using 0, and the control unit 620 determines whether the V bit 601 is set. The directories 602 match.

When the V bit is set, it is determined that there is a TLB hit, and the read physical address 606 and the lower part 85 of the logical address
L and offset 850 are merged to obtain physical address 8.
Generate 6. If the determined result is that the TLB is a miss, the address conversion table stored in the main memory 2 is read out and newly stored in the TLB 600, and the above conversion operation is performed.

The MMU 6 also performs a protection check on the accessed area at the same time as converting the physical address. If there is a read access to an area where the read enable bit 604 is off, or a write access to an area where the write enable bit 605 is off, it is reported to the BPO 4 as a protection error.

The cache memory 4 stores a V bit 401 . A directory 402 that stores the physical address of a cache entry, data 406 that stores a copy of the main memory 2 of the corresponding entry. A comparator 410 that detects a match between a cache entry and an access address, and a cache memory control unit 420
It is composed of.

When a memory access is performed from BPO4, the directory 402 and V bit 401 of the cache memory are read using the lower part 86L of the physical address. A comparator 410 is used to determine whether the read directory 402 matches the upper part 86U of the physical address. If the v bit is on and the comparator 410 outputs match, the corresponding entry has been registered in the cache memory. In other words, the control unit 420 determines that it is a catch hit,
If it is a read access, the output enable signal 423 is turned on, the output gate 430 is opened, and the data 406 of the cache memory is sent to the BPO4. If there is a miss, the relevant area of the main memory 2 is copied and the data is sent to the BPO 4.

FIG. 5 is a flowchart showing the operation of the cache memory control unit 420 during read access.

First, in step 101, it is determined whether the area to be accessed is in the cache entry. This determination is made based on the output of the comparator 410 and the V bit 401 output.

If it is, proceed to step 102;
If not, proceed to step 103. Here, when the access area is the common area 240 explained in FIG. 3, in this method, since it is not on the cache memory, a miss bit is always generated, and the process proceeds to step 103.

In step 102, the output of the read data section 406 is transferred to the output gate 4 by turning on the output enable signal 423.
BPO via data bus 75 by opening 30
Send to 4.

In step 103, the common bit 603 of TLB 600
If this is on, that is, if it is a common area, the process proceeds to step 107, and if it is a private area, the process proceeds to step 104. In step 107, whether or not the common area is a read-only area is determined by determining whether the read enable bit 604 and write enable bit 605 of the TLB 600 are on/off. If read is enabled and write is disabled, it is determined that the common area currently being accessed is a read-only area such as the common part of text or data in FIG. If not, proceed to step 108.

Step 104 and subsequent steps are normal miss processing, in which the cache memory 4 stores the main memory 2 of the corresponding area.
perform this copy operation. That is, first, in step 104, the address output 84 in FIG.
Then, the desired address is output, and response data from the main memory 2 is read through the data input/output cuff 4. In the next step 105, the cache memory control unit 420 registers the read data in the cache memory, turns on the write enable signal 421 and the V-pit power 422, writes the physical address 86U to the directory 402, and
Turn on the V bit 401 and transfer the read data to data section 4.
In the primary step 106 of writing to 06, the output gate 4
30 and sends the data to BPO4.

On the other hand, in step 107, if the common area and lead
This is a light area. That is, if it is determined that the common area 240 in FIG. As described above, in the present invention, when reading access to the common area, the main memory is directly accessed, and no copy is made to the cache memory 4.

This eliminates the occurrence of mismatch between the cache memory and main memory.

FIG. 6 is a flowchart showing the operation of the cache memory control unit 420 during write access.

First, in step 110, similar to step 101 in FIG.
It is determined whether it is a catch hit or not.

If it is a hit, the process proceeds to step 111, and if it is a misset, the process proceeds to step 113. Step 111
Then, the data in the cache memory 4 is updated, and in the next step 112, the data in the main memory 2 is updated.

If it is determined in step 110 that there is a cache miss,
In the next step 113, it is determined whether the corresponding area is a common area. The common bit 603 output of the TLB 600 is used for this determination.

If the area in question is a common area corresponding to area 240 in FIG. 3, the process proceeds to step 117; if the area is not a common area, the area corresponds to private area 231 in FIG.
It is determined that the area is equivalent to 233, and the process proceeds to step 114.
In the case of the read access in FIG. 5, if the common area is a read-only area, the data is copied onto the cache memory, but in the case of a write access to the read-only area.

Since the MMU 6 performs the protection check, the cache memory 4 does not perform the check.

In step 114, the corresponding area is first copied from the main memory 2, the directory 402 and the V bit 401 are set, and the area is registered in the cache. This is done for the purpose of setting data that will not be written into the cache data section 406 because the size of one entry in the cache is larger than the size to be accessed. Next step 1
In steps 15 and 116, the contents of the cache memory 4 and the main memory 2 are updated, respectively, similarly to steps 111 and 112 at the time of cache hit.

If you proceed to step 117, common area 2 in FIG.
40. At this time, the data is not registered in the cache memory 4, but only the contents of the main memory 2 are updated, and as in the case of read access, this process prevents mismatch between the cache and the main memory.

Next, in FIG. 2, the processor 31
．． Let us consider the case where the file device 75 is activated and the data 501 in the file ¥11175 is accessed into a desired area 201 of the main memory 2.

At this time, when a copy 4101 of the main memory area 201 exists in the cache memory 41 connected to the processor 31, the processor 31 may erroneously read the data before loading after the loading is completed. To prevent this, it is possible to make the main memory area 201 writable as a common area and not register it in the cache memory 41, but the data to be loaded from the file includes various types of data, and it is necessary to use the cache memory for these. This will significantly reduce the performance of the processor.
It's not a realistic method.

Therefore, in the present invention, a method shown in FIG. 7 is used.

FIG. 7 is a flowchart showing the program executed on the processor 31 and the operations of the file device 75 and channel 70. When the processor 31 loads the data 7501 of the file device 75 into the desired area 201 of the main memory 2, first step 12 is performed.
0, the read enable bit 604 of the address translation table of the processor 31 itself. Write enable bit 6
In the next step 121, the V bit 401 of the corresponding entry in the cache memory 4 is turned off. After finishing, in step 123, channel 7
0. A read start is performed on the file device 75. After startup, the processor 31 enters the wait state 12 "4" and executes another task until the data transfer from the file device 75 is completed. Even if the main memory area 201 is accessed by mistake due to a programming error, the enable 6
Since the 04° write enable 605 is turned off, protection errors can be detected and malfunctions can be prevented. Channel 70 that received the read trigger. File device 7
5 transfers data in step 127 and then reports completion to processor 31 in step 128. Upon receiving the completion report, processor 31 enters wait state 124.
Set this task that was in the startup state to 125 and proceed to step 1.
Proceed to step 26. In step 126, the read enable bit 604 and write enable bit 605 of the corresponding area are turned on to enable access to the corresponding area. When the corresponding area is subsequently accessed, since the V bit 401 is turned off in step 121, the data can be copied from the main memory 2 and the latest data can be taken into the cache memory 41.

- [Effects of the Invention] According to the present invention, there is no copy of the main memory area that may be written by other processors or input/output devices in the cache memory, so the contents of the cache memory and the main memory do not match. Never. Therefore, communication access to other processors for cache invalidation is not required, the amount of traffic on the system bus can be kept low, the decrease in access time due to an increase in the amount of traffic on the system bus can be prevented, and throughput can be improved. In addition, there is no need to monitor whether other processors or input/output devices rewrite their own cache memory area, and if they do, invalidate the entry.
It is possible to prevent processor performance from deteriorating and maximize processor performance.

[Brief explanation of drawings]

Figure 1 is a configuration diagram of a memory management unit and cache memory, Figure 2 is a configuration diagram of a multiprocessor system,
Figure 3 shows the relationship between logical space and main memory, Figure 4 shows the configuration of one processor, and Figures 5 and 6 each show read access. FIG. 7 is a flowchart showing the cache memory control operation during write access. FIG. 7 is a flowchart showing the operation of the program on the processor and the input/output device when starting the input/output device. 2... Main memory, 4, 41-44... Cache memory, 6... Memory management unit (MMU), 31-
34...processor, 70...channel, 75...
・File device, 600...Address translation buffer (
TLB), 603...Common bit, 604...
Read enable bit, 605...Write enable bit.

Claims (1)

[Claims] 1. In a cache memory control method in a virtual memory multiprocessor system consisting of a plurality of processors that share a main memory, a logical address output by a processor when accessing the memory is set to a physical address on the main memory. The address conversion means for converting into an address is provided with a common flag that is turned on only when data corresponding to each address is shared by multiple processors, and a write flag that is turned on only when the data is in a writable area. . A cache memory control method characterized in that when both the common flag and the write flag are on, the corresponding address on the main memory is accessed directly without making a copy of the data on the cache memory. 2. If the multiprocessor system is provided with an input/output device that transfers data to and from the main memory in response to an input/output request from each processor, each processor performs input/output to the input/output device. 2. The cache memory control method according to claim 1, wherein when a request is made, a copy of the area on the main memory is erased from the cache memory corresponding to the processor.