JPS5936393A - Nonvolatile semiconductor memory device - Google Patents

Abstract

PURPOSE:To detect a change of the storage holding characteristics of a memory, by varying the read gate voltage of a variable threshold value type nonvolatile semiconductor memory. CONSTITUTION:When a transistor (TR) 13 of a voltage variable circuit RVVC is turned on, the storage information obtained by variable threshold value type nonvolatile semiconductor memory TRs 9-12 is read with the read voltage smaller than that obtained when the TR13 is turned off. Then it is possible to extract the expected information regardless of ON or OFF of the TR13. While if a nonvolatile memory becomes volatile as the time elapses, the read result differs by ON or OFF of the TR13. Thus the change of the memory storage holding characteristics is detected assuredly to ensure the proper rewriting processing, etc. This improves the reliability of a nonvolatile semiconductor memory device.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a non-volatile "1'-conductor memory device using a variable threshold cylindrical semiconductor memory, and sometimes the memory device"
Note 1. The present invention relates to a nonvolatile semiconductor memory device that can improve α retention characteristics.

A schematic configuration diagram of an example of a conventional memory device of this scale is shown in FIG. 1. In the figure, (1), (7,)
, (:3) reads 110-7 voltage NN, , determines M
OS ) transistors, these are the read voltage circuit R
It constitutes VC. (9), (10), (1
1), (12) IrJ-FAMO8.

Variable threshold semiconductor memory transistors such as MNOS (4) and (5) are memory transistors (
9) to (12) gate selection transistors (4) and (5).
) constitutes a gate selection circuit GSC. (7),
(8) is a MOS transistor for drain selection of memory transistors (9) to (12), and these transistors (7) and (8) are drain selection circuits DSC'&
It consists of (6) V soil memory transistor (9) ~
(12) MOS for flowing the flow into the drain in the evening
) is a transistor. Further, Vcc indicates a power supply voltage for supplying power to this memory device.

The operation of the memory device constructed in this way will be explained with reference to FIG. 2, which shows a characteristic diagram of the change in threshold value over time of a variable threshold type semiconductor memory transistor.

First, gate selection transistors (4), (5):
! ,-call.

Which of the memory transistors (9) to (12) is selected by the rain selection transistors (7) and (8). (7) The readout force composed of transistors (1) to (3), the JF circuit RVCH, and the threshold value VMG when the memory transistors (9) to (12) are inserted, (5th This is a circuit that determines readout values ?lJ, JF, and VMG, which are set between the erased threshold value vMGmin (see Figure 2) and the erased threshold value vMGmin (see Figure 2).Then, the selected memory transistor is t if it is non-conducting and t if it is erased
I'm going to climb a mountain.

Also, the threshold value of the written memory transistor is
It changes with the passage of time t, as shown in FIG. 2, due to the discharge of the injected charges of the memory transistor. Then, when the threshold value VMGmaX at the time of writing decreases with the passage of time t and goes around the read voltage vMG,
When a read voltage VMG is applied to the memory transistor, it becomes conductive like the memory transistor in the erased state. This is the cram school volatilization, which is commonly referred to as a call.

In addition, in Fig. 2, ■MGL is the read voltage VMG
Another smaller read voltage is shown.

However, even in a volatilized memory transistor, the second
As is clear from the figure, although the correct content can be obtained by slightly lowering the read voltage vMG (see read voltage VMGL), since the conventional read voltage VMci was fixed, such read 2
It was not possible to utilize the voltage margin.

For this reason, conventional memory devices have the disadvantage that changes in the memory retention characteristics of nonvolatile semiconductor memory transistors cannot be detected, and also have the disadvantage that high reliability cannot be obtained. .

In view of the above points, the present invention has been made to solve such problems and eliminate such drawbacks, and its purpose is to change the read voltage, thereby making it possible to utilize the read voltage margin of the memory transistor. It is an object of the present invention to provide a nonvolatile semiconductor memory device which enables detecting changes in the memory retention characteristics of a nonvolatile semiconductor memory transistor, improves the memory retention characteristics, and provides a highly reliable nonvolatile semiconductor memory device.

In order to achieve this purpose, a transistor for voltage control is connected in parallel with the transistor of the readout voltage circuit according to the present invention, and a control voltage is applied to the gate of this transistor to make it conductive. , embodiments of the present invention will be described in detail based on the drawings.

FIG. 3 is a block diagram schematically showing an embodiment of a nonvolatile semiconductor memory device according to the present invention, and only the parts necessary for explanation are shown.

In FIG. 3, the same reference numerals as in FIG. )Vl: control signal C8
The readout voltage is controlled by the transistors (1) to (3) that determine the readout voltage VMG, and the readout voltage is controlled by a voltage variable that changes uJ the voltage applied to the gate of the variable threshold nonvolatile semiconductor memory transistor selected at the time of readout. It constitutes the circuit RVVC.

Next, the operation of the embodiment shown in FIG. 3 will be explained with reference to FIG. 4, taking as an example a case where a FAMO8 type transistor is used as a variable threshold type nonvolatile semiconductor memory.

Figure 4 shows the voltage/current characteristics during erasing and blue coloring, with the horizontal axis representing the gate voltage VG and the vertical axis representing the drain current ID. (a) shows the characteristics during erasing. ,
(b) shows the characteristics immediately after writing ti, and (e) shows the characteristics after writing Vl.

First, before explaining the operation of the embodiment, the memory retention characteristics of the nonvolatile memory transistor will be explained in order to facilitate understanding of the present invention.

In the case of the FAMO8 type memory transistor, erasing corresponds to the case where electrons are emitted from the floating gate by irradiation with ultraviolet rays7, and electrons are injected into the floating gate by applying a high voltage to the drain and control gate. The case corresponds to writing. and,
In the above two state branches, for a constant reading voltage, the fourth
As shown in the figure, it can be determined whether a drain current ID corresponding to the sense level SL of the sense amplifier flows or not. Here, the layout tζ1 of the nonvolatile semiconductor memory device
, Retention characteristics ￥, 1, Non-volatile +'1゛Semiconductor memo IJ l
Ranjistor's Iil'i (JY hold/l'! "t'l
There is a close relationship with

In other words, as shown in Figure 4, immediately after insertion, V''-
ilq shown in characteristic (b), pressure 1) S5 flow P1. , and even if a read voltage is applied to the gate, the sense level S
Since 11c6fi: of L or higher does not flow, the sense amplifier can identify the write state. However, as the electron state in the floating gate decreases over time, the current/voltage characteristics of the memory transistor in the written state change to the erased state side, as shown in 1jE characteristic (C) in Figure 4. shift to. Therefore, this property (c
) Voltage ・■ If the voltage reaches the 1st current characteristic, it will be 1st, and at a constant readout voltage VHG, the sense level SL
The above drain current In flows, and it is no longer possible to identify the late night state.

What should be noted here is that even when the characteristic (c) in FIG. can.

The present invention is based on the above-mentioned operating principle, and as shown in the embodiment of FIG.
), (3) applies a constant readout voltage to the gate of the selected memory transistor.

The transistor (13) constitutes a read voltage variable circuit RVVC, and the transistor (13) can be turned on and off by the control signal C8.

Here, the transistor (13) has a control signal C of:4
When reading with VMG 8 applied, a read result with the constant read voltage VMG described above is obtained. Furthermore, when reading is performed with the control signal C8 applied to the transistor (13), the transistors (3), (
13) A read result is obtained using another read voltage VMGL (see FIG. 2) which is smaller than the constant read voltage VMG determined by the resistance ratio.

On the other hand, since the threshold value of the memory transistor changes continuously over time, the transistor (1
Expected information can be obtained regardless of whether 3) is on or off.

Then, as time passes and the transistor in the writing state reaches the state of characteristic (c) in FIG. 4, the transistor (1
The readout results differ depending on whether 3) is on or off.

In the conventional case, the nonvolatile memory device would have been volatile at this point.

However, according to the present invention, in the above case, if the read result obtained when the transistor (13) is turned on is used, non-volatile information can be used correctly. Further, by performing rewriting using the read result obtained when the transistor (13) is turned on at this point, the nonvolatile memory transistor can be brought into the state of characteristic (b) in FIG. 4.

As described above, the present invention is applied to FAMO as a variable threshold type memory.
Although the description has been made taking the case of a type 3 memorite memory transistor as an example, the present invention is not limited to this, and the present invention is not limited to this.
An O8 type memory transistor can also be used in the same manner, and the same effect can be obtained.

As explained above, according to the present invention, since the read gate voltage of the variable threshold nonvolatile semiconductor memory device is made variable, it is possible to detect changes in the memory retention characteristics of the nonvolatile semiconductor memory transistor. It is possible to improve its memory retention characteristics and obtain a highly reliable product, so its practical effects are extremely significant. Further, by changing the read voltage, it is possible to utilize the read voltage margin of the memory transistor, and it is also extremely effective in that it is possible to compare read contents at different read voltages.

[Brief explanation of the drawing]

FIG. 1 is a block diagram schematically showing an example of a conventional variable threshold type nonvolatile semiconductor memory device, and FIG. 2 is a threshold value of a variable threshold type semiconductor memory transistor used to explain the operation of FIG. FIG. 3 is a block diagram schematically showing an embodiment of a variable threshold type nonvolatile semiconductor memory device according to the present invention, and FIG. 4 is a voltage/current characteristic diagram during erasing and writing. It is. (1) to (8)...Mos transistor, (9) to
(12)...Variable threshold type semiconductor memory transistor, (13)...MOS transistor. Representative Shin Kuzuno - Figure 1 Figure 2 Figure 4 Procedural Amendment (Voluntary) Director of the Jibo Agency'1゛
-144937 No. 2, 6 vehicles of invention, 3 non-volatile semiconductor memory devices, 4 h of seizures, relationship with CFL, license 19 (! person representative old piece)
11.1 (Part 8/41 Agent 5, Subject of amendment txt Claims column of the specification (21 Detailed explanation of the invention column 6 of the specification, Contents of amendment txt Claims of the specification Correct the range as shown in the attached sheet. (2) Replace r NMG J on page 1, line 20 of the same book with “VMG
Correct it as j. (3) On page 5, lines 4 to 6 of the same Ministry, the sentence ``conducting voltage circuits'' is deleted and the following sentence is added. "It is equipped with a readout voltage variable circuit that varies the Y'C readout voltage applied to the gate of the variable threshold nonvolatile semiconductor memory transistor that is selected at the time." The reading voltage is fixed at the time of i readout] and the readout voltage is constant at the time of i readout. (5) Add "VMG" after "N pressure" on page 7, line 8 of the same book. (6) Correct the "writing status" in the second line of page 8 of the book to "v# writing status". Attachment [Variable threshold type non-volatile semiconductor memory IJ selected at read time in non-volatile semiconductor memory device using variable threshold type semiconductor memory] The read voltage applied to the gate of the transistor is varied. Non-volatile semiconductor memory device 1 characterized in that it is equipped with a variable read voltage circuit

Claims (1)

[Claims] In a nonvolatile semiconductor memory device using a variable L-tube type semiconductor memory, the first . 1. A nonvolatile semiconductor memory device comprising: a variable threshold voltage type nonvolatile semiconductor memory transistor connected thereto; and a variable read voltage circuit that varies a read voltage applied to the gate of the memory transistor.