JPS5934987B2 - electronic clock - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to an improvement of an electronic timepiece having a digital display section.
This allows other clocks to be adjusted accurately based on the time of this electronic clock.

The present invention will be explained using an electronic timepiece having both an analog display section and a digital display section.

This watch has an analog display section driven by a motor and a digital display section that optically displays digital time, and can display the current time on both the analog and digital display sections.

Furthermore, by switching and displaying the current time on the analog display section and the additional functions on the digital display section, there are many advantages such as the additional function display and the current time display being able to be visually read at the same time.

However, when the current time is displayed on both the analog and digital display sections, for example, if the time on the digital display section is corrected, the time on the analog display section must be adjusted at the same time to match the time on the digital display section.

Here, to correct the second time on the analog display, a second reset contact is usually provided in the wheel train, and by operating a switch, the pointer is kept on standby when the second time is between 0 and 29 seconds, and when the second time is between 30 and 29 seconds.
If the time was up to 9 seconds, the second hand was fast forwarded.

According to this method, the analog display time can be accurately matched to the digital display time down to the second, but the configuration becomes complicated.

This method has disadvantages in terms of cost and manufacturing, such as the complexity of the manufacturing process required to match the point of contact with the guide, which has caused problems.

Furthermore, even if the user uses a normal digital watch with a single digital display, when using that watch as a master clock to set the time of another digital or analog watch, the user must reset the seconds while looking at the digital display. Or I had to do a second return to zero, which was very difficult <<
, and was often inaccurate.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a time adjustment mechanism that is advantageous in terms of manufacturing and cost, and is easy to perform to zero or reset the seconds of other displayed times based on the digitally displayed time.

In order to achieve the above object, the present invention uses the corrected digitally displayed time as a reference and makes an audible sound when the minute is carried up in the digitally displayed time, so that the user can adjust the seconds to zero or zero according to the audible sound. It is characterized in that it is configured so that it only needs to be reset in seconds.

A detailed explanation will be given below based on examples.

FIG. 1 is a block diagram showing an embodiment of the present invention.

2 is a reference signal generator, 4 is a frequency dividing circuit, 6 is a waveform shaping circuit, 8 is a drive circuit, 10 is a motor, and 12 is a wheel train.

As a result, the time is displayed in an analog manner by moving the hands (not shown).

14 is a second counter for counting seconds, 16 is a minute counter for counting minutes, 18 is an hour counter for counting hours, 20 is a decoder driver, and 22 is a display section.

As a result, the signal from the frequency dividing circuit 4 is counted,
The time is displayed digitally on the display section 22.

Reference numeral 24 denotes a correction operation section, which has the functions of resetting the second counter 14, fast-forwarding the minute counter 16 and hour counter 18, and controlling the second hand of the clock to return to zero.

Reference numeral 26 denotes a minute carry detection circuit, which constantly detects three seconds before the one minute carry based on the count contents of the second counter 14.

Reference numeral 28 denotes a notification sound control circuit, which detects that the digital display time has been corrected by the correction operation unit 24 and outputs the IHz pulse from the divide-by-1 circuit 4 to the notification sound generation circuit 30.

This output IHz pulse is also a circuit that discriminates between pulses at the time of minute carry and pulses 3 seconds, 2 seconds, and 1 second before the minute carry.

The notification sound generation circuit 30 receives the IH signal from the notification sound control circuit 28.
This circuit mixes the z pulse signal and two types of audible frequency signals from the frequency dividing circuit 4 to generate a notification sound.

32 is a notification section, which is a circuit that receives a signal from the notification sound generation circuit 30 and makes notification.

On the other hand, 34 is a warning sound counter, which is a circuit that operates the warning sound control circuit 28 for five minutes after the modification operation unit 24 makes a correction.

FIG. 2 shows the correction operation section 24 in FIG. This is a circuit diagram of the alarm counter 34, and FIG. 3 is its time chart.

The correction operation section 24 includes a one-second counter reset switch 40.
Return to zero switch 42. flip flop 44.46,48
,50. ANDGATE 52. It is composed of an inverter 54.

Also, the alarm counter 34 is connected to the inverter 56. ANDGATE 58, 60°62.64. flip flop 66.68
, 70° quinary counter 72.

And flip-flops 44, 46, 50.66.68
A 32 Hz signal from the frequency divider circuit 4 is input to the φ input.

The operation of this circuit will now be explained.

It is assumed that this circuit operates with negative logic.

When the second counter reset switch 40 is closed, the signal on the output line 41 goes from L to H, and the flip-flop 44
input to the D input.

After this, when the 32Hz signal input to the φ input of the flip-flop 44 changes from H to L, the flip-flop 4
The signal at the output Q of the transistor 4 becomes H and is input to the ant gate 52 and the D input of the flip-flop 46.

As a result, the signal on the output line 53 of the ant gate 52 becomes H.
is inverted by the inverter 54 and the second counter 14 is reset.

Thereafter, when the 32 Hz signal changes from H to L again, the signal on the output Q of the flip-flop 46 changes from H to L, the signal on the output line 53 also changes from H to L, and the reset of the second counter 14 is released.

The signal on this output line 53 is input to the φ input of the flip-flop 48.

When the signal on the output line 53 falls from H to L,
The output Q of the flip-flop 48 becomes H and is input to the AND gate 58.

When the second counter reset switch 40 is opened, the signal on the output line 57 of the inverter 56 becomes H, and the signal on the output line 59 of the AND gate 58 also becomes H, which is input to the input of the flip-flop 66.

And the 3 input to the φ input of the flip-flop 66
When the 2 Hz signal falls from H to L, the output Q of flip-flop 66 becomes H and is input to the D input of AND gate 60 and flip-flop 68.

As a result, the signal on the output line 61 of the AND gate 60 changes from L to H.

After this, when the 32Hz signal falls from H to L again,
Since the signal of the output Q of the flip-flop 68 becomes L, the signal of the output line 61 also changes from H to L, and the output of the flip-flop 7
Input to the φ input of 0.

As a result, the signal at the output Q of the flip-flop 70 becomes H, is generated on the output line 71, and is input to the AND gate 62 and the notification sound control circuit 28.

Here, output line 8 is connected to one of the inputs of ANDKETRO 2.
A minute carry signal for the seconds counter 14 is inputted via the pin 2c.

Therefore, when the signal of the output Q of the flip-flop 70 becomes H, the output line 63 of the AND gate 62 is connected to the output line 8.
A carry signal having the same phase as the signal of 2c appears and is input to the φ input of the quinary counter 72.

The quinary counter 72 begins counting the one-minute carry signal.

Here, in order for the user to return the pointer to zero, press the zero return switch 4.
2 for one hour, the signal on the output line 43 becomes H and is input to the D input of the flip-flop 50.

Here, 3 is input to the φ input of the flip-flop 50.
When the 2Hz signal falls from H to L.

The output Q signal of the flip-flop 50 becomes L.

Input to AND gate 64.

As a result, the signal on the output line 65 of the AND gate 64 changes from H to L.

Quinary counter 72. Flip flop 48,50°70
to be reset.

As a result, the signal on the output Q of the flip-flop 50 changes from L to H, and the signal on the output line 65 also becomes H again, so that the reset is canceled.

Even if the return-to-zero switch 42 is not closed, the quinary counter 72 counts the minute carry signal, and after 5 minutes, the output Q signal falls from H to L, and the output line 6
The signal No. 5 falls from H to L, and the same operation as described above is performed.

In this way, the alarm counter 34 is reset by the second reset switch 40.
An H signal is output to the notification sound control circuit 28 via the output line 71 after the switch 40 is closed until the zero return switch 42 is operated, or after 5 minutes after the switch 40 is closed.

FIG. 4 shows the second counter 142 minute carry detection circuit 26 in FIG. Notification sound control circuit 28. 5 is a circuit diagram of the notification sound generation circuit 30, and FIG. 5 is a time chart thereof.

The second counter 14 consists of a decimal counter 802 that counts the first digit of the second and a hexadecimal counter 82 that counts the middle digit of the second.The one-minute carry detection circuit 26 includes an AND gate 84,
86, 88, and inverters 90 and 91.

The notification sound control circuit 28 also has an AND gate 92. Nantes Gate 94. Flip-flop 96, 98, 100, 10
2,104, and the notification sound generation circuit 30 is composed of AND gates 108, 110, 112, 114. or gate 11
Consists of 6.

First, the output Q1 of the decimal counter 80. Q2. Q3゜Q4
, the outputs Q5, Qa, and Q7 of the hexadecimal counter 82 are as shown in the table of FIG.

From this, when the count content of the second counter 14 is 56 seconds, the signals on the output lines 80a, 80b, and 80c are respectively 1.

It becomes H, H.

Here, the signal on the output line 80a is inverted by the inverter 91 to become H, and is input to the AND gate 84.

Similarly, output line 82a. Since the signals 82b and 82c also become H, L, and H, respectively, the signal on the output line 82b is inverted by the inverter 90 to become H, and is input to the AND gate 86.

As a result, the output lines 85 and 87 of AND gates 84 and 86
The signal on the output line 89 of the AND gate 88 also becomes H.

When the count content of the second counter 14 reaches 57 seconds, the signal on the output line 85 of the AND gate 84 becomes L, so the signal on the output line 89 of the AND gate 88 also becomes L.

This signal on output line 89 is input to AND gate 92 .

When the second reset switch 40 of the correction operation section 24 is pressed here, the signal on the output line 71 of the alarm counter 34 becomes H as described above.

Input to AND gate 92.

As a result, the output line 93 of the AND gate 92 has the output line 8
A signal in phase with 9 appears and enters the 7 input of flip-flop 96.

When the signal on the output line 93 changes from H to L in 57 seconds, the signal on the output Q of the flip-flop 96 becomes H, generated on the output line 97, and input to the Nant gate 94.

The 1Hz signal from the frequency divider circuit 4 is input to the other input of the Nant gate 94 via the output line 5.

Therefore, the output line 95 of the AND gate 94 has an opposite phase IH.
z signal is generated.

Flip-flop 98°10 forming a shift register
φ input of 0.102,104 and AND gate 108
, 110.

As a result, the outputs Q of the flip-flops 98, 100, and 102 are 57 seconds and 5 seconds, which are the count contents of the second counter 14.
Each time an IHz pulse corresponding to 8 seconds or 59 seconds is input, the signal becomes H in sequence.

At this time, the output line 10 of the output Q of the flip-flop 102
Since the signal No. 5 is H, a signal in phase with the IHz signal on the output line 95 appears on the output line 111 of the AND gate 110, and is input to the AND gate 114.

Since the audio frequency signal from the frequency dividing circuit 4 is input to the AND gate 114, a modulated frequency signal as shown in the time chart of FIG. 5 appears on the output line 115 of the AND gate 114, and the OR gate 116 Enter.

As a result, the output line 117 of the OR gate 116 has the output line 1.
A signal having the same phase as 15 appears and is input to the notification section 32, and the signal 57
A notification sound is generated every second, 58th second, and 59th second.

Here, when the digital display time is 0.5 seconds before the minute carry, the output Q of the flip-flop 102 becomes H, which is generated on the output line 103 and input to the AND gate 108.

Also, since the output Q of the flip-flop 102 becomes L,
The signal on the output line 111 of the controller H10 becomes L.

Therefore, an IHz signal in phase with the output line 95 appears on the output line 109 of the AND gate 108, and
Enter.

An audio frequency signal different from the previous one from the frequency divider circuit 4 is input to the AND gate 112, so a modulated frequency signal as shown in the time chart of FIG. 5 appears on the output line 113 of the AND gate 112. , or gate 116
Enter.

As a result, the output line 117 of the OR gate 116 has the output line 1.
A signal having the same phase as the signal No. 13 appears and is input to the notification section 32, which generates a notification sound different from the notification sounds for 57, 58, and 59 seconds when the digit is increased by one.

Then, when 0.5 seconds have elapsed since the minute was carried, the signal at the output Q of the flip-flop 104 changes from H to L, causing the flip-flops 96, 98, 100° 102, and 104 to be reset.

As a result, the output Q of the flip-flop 104 becomes H,
The reset is canceled again.

The above-mentioned operation continues until the zero switch 42 of the correction operation section 24 is operated or until five minutes have elapsed since the second counter 14 was reset.

As described above, according to the present embodiment, a notification sound is generated when the digital time display is corrected to carry one minute, and the user can press the zero switch in time with the notification sound.

Analog time display and digital time display can be easily matched.

In addition, since the minute carry warning sound is generated 3 seconds before the minute is carried, the user will not miss the timing to press the zero switch.

For this reason, there is no need to provide a second reset contact in the wheel train for making seconds-by-second corrections, which has great advantages in terms of manufacturing and cost.

In addition, since the user only has to press the zero switch in time with the notification sound, there is no need to look at the digital display, making it extremely easy and accurate to set the time.

Furthermore, in this embodiment, the notification sound is generated not only once but multiple times for each minute carry, so that even if the user misses the timing to press the zero switch, he or she can try again one minute later.

In this embodiment, the time after the digital seconds and time display is reset is detected, but it is also possible to perform the above-mentioned operation by detecting the end of the hour and minute fast-forwarding operation.

Furthermore, when the present invention is used in a time signal watch, if the 1 hour signal sound and the minute carry sound are made different, the user will not have to confuse the hour signal sound and the minute carry sound, which will be more effective. Become.

As described above, according to the present invention, a notification sound is generated every time the minute is carried after the digital display time is corrected, and other display times are reset to zero in accordance with the timing at which the notification sound is generated. By doing this, it becomes easier and more accurate to set the time than before.

Furthermore, according to the present invention, it is only necessary to provide a circuit for generating an alarm sound on the digital display clock, and this can be integrated with the clock circuit.

This eliminates the need for mechanical and electrical configurations for interlocking the time-adjusted digital clock and other clocks, such as conventional parent-child clocks or analog/digital display clocks, which is extremely advantageous in terms of manufacturing and cost.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG.
The figure is a circuit diagram of the correction operation section and alarm sound counter in Figure 1, Figure 3 is a time chart thereof, and Figure 4 is a circuit diagram of the second counter, minute carry detection circuit, alarm sound control circuit, and alarm in Figure 1. It is a circuit diagram of a sound generation circuit, and FIG. 5 is its time chart. FIG. 6 is a table showing the output signal of the seconds counter. 14...second counter, 24...correction operation section. 26... Minute carry detection circuit, 28...
Notification sound control circuit, 30... Notification sound generation circuit, 3
2... Information department.

Claims (1)

[Claims] 1. In an electronic timepiece having a digital display section. a correction operation detection means for detecting that the time has been corrected on a digital display; a minute carry detection means for detecting a minute carry on the digital display; and a correction operation detection means and a minute carry detection means. and a notification sound generating means for generating a correction notification sound in response to a signal from the digital time display, and generating a correction notification sound every time a minute is carried after the digital display time is corrected. 2. The electronic timepiece according to claim 1, wherein the correction operation detection means detects that the second time of the digital display time has been reset. 3. In electronic watches with a digital display. a correction operation detection means for detecting that the time has been corrected on a digital display; a minute carry detection means for detecting a minute carry on the digital display; and a correction operation detection means and a minute carry detection means. a notification sound generating means that generates a correction notification sound in response to a signal from the digital display section, a carry-immediate detection means that detects immediately before a carry of a minute on the digital display section, a preliminary carry-up detection means based on signals from the correction operation detection means and the carry-immediate detection means. An electronic clock comprising a preparatory sound generating means for generating a sound, and after correcting the digital display time, a preparatory sound is generated immediately before the minute is carried, and a correction notification sound is produced when the minute is carried by one digit. . 4. The electronic timepiece as set forth in claim 3, characterized in that the preliminary sound and the correction notification sound are different sounds. 5. In an electronic watch having a digital display, correction operation detection means for detecting that the time on the digital display has been adjusted; minute carry detection means for detecting minute carry on the digital display; It has a notification sound generating means that generates a correction notification sound based on the signals from the operation detection means and the minute carry detection means, and a counter means that counts the number of times the correction notification sound is generated, and after correcting the digitally displayed time. An electronic clock characterized by generating a correction notification sound every time the minute is carried a certain number of times.