JPS5930372A - Synchronizing separation circuit - Google Patents

Abstract

PURPOSE:To obtain a TV picture stable at all times, by integrating a synchronizing signal output, outputting a vertical synchronizing signal and controlling a sampled and held voltage so that the synchronizing period of the outputted vertical synchronizing signal is constant, for changing a cut level depending on the state of the synchronizing signal. CONSTITUTION:A synchronizing signal tip voltage of a video signal 1 including a synchronizing signal from a terminal 2 or a voltage corresponding to the tip voltage is sampled and held at an S & H circuit 3, the voltage held at the circuit 3 and the inputted video signal 1 are compared at a synchronizing separation comparator 6, and the synchronizing signal is outputted. The signal separated synchronizingly and outputted from the comparator 6 is integrated at an LPF 27, the horizontal signal component is eliminated, a vertical synchronizing signal is detected at a vertical synchronizing signal separating circuit 28 and the vertical synchronizing signal period is detected at a vertical synchronizing period detecting circuit 29. The output of the circuits 28, 29 is applied to the circuit 3 and the cut level is changed depending on the state of the synchronizing signal, and allowing to obtain the TV picture stable at all times.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a synchronization signal separation circuit for a television receiver, and is intended to greatly improve the performance of synchronization separation using a novel circuit configuration.

Conventionally, synchronous separation methods include a transistor base input type, an emitter input type, a sample-and-hold (hereinafter referred to as S&H) type, etc., but the present invention particularly improves the performance of an S&H type synchronous separation circuit. It's about improvement.

FIG. 1 shows a block diagram of a conventional S&H type synchronous separation circuit. (1) is a video signal including a synchronization signal, (2) is an input terminal for video signal (1), (3) is an S&H circuit, (4)
is a capacitor terminal for SAH, (5) is a capacitor for SAH, (6) is a comparator for synchronous separation, (7) is a synchronous separation output terminal, and (8) is a synchronous separation output. Further, FIG. 2 shows signal waveforms for explaining these operations. Figure 2 (a
) is an enlarged view of the video signal (1) including the synchronization signal, and (9)
is the synchronization signal, Q□ is the video signal, α core is the tip of the synchronization signal,
vsYNO indicates the DC voltage. (2) is a line indicating the cutting voltage of the synchronization signal, that is, the reference voltage for extracting the synchronization signal from the video signal by a voltage comparator, vst,
rap indicates the voltage. 0 indicates ground voltage VG
ND=OV. FIG. 2(b) shows a synchronous output signal that is synchronously separated from the video signal. α→ is the repetition period, which is 68.5μ in the case of the NTSC system. In addition,
Although not shown here, the vertical synchronization signal 9 equivalent pulses are also output to the synchronization separation output terminal (7). Next, regarding the operation of the synchronous separation circuit shown in Figure 1, the video signal input to the input terminal (1) is sent to the S&H circuit (3) and the comparator (6).
) is applied to In this circuit, the synchronous tip voltage VSY
Voltage Va L IOR slightly lower than NO is S&-H
, l capacitor (b) two-sample self-small = o
The value of V8YNO-Vshrcn (=ΔV) is called the cutting level of the synchronization signal, and is a value indicating how many volts below the synchronization tip the synchronization separation is to be performed.

This value is usually a fixed value by a constant in the circuit. VsLIOE is 1. along with the video. Comparator + (6) l
This is input! The image signal becomes High at V8LICE.
It is divided into level and low level. That is, a synchronously separated signal is obtained as shown in FIG. 2(b). FIG. 8 shows a specific example of the S&H circuit. 0no αri is NP
A differential amplifier is configured with N transistors. Qψ (to) is the resistance that sets the cutting level △■, ni) is the constant current source,
Q◇ is an NPN l-transistor, (a) is a resistor that determines the charging time constant, (c) is an NPN ) transistor, (c)
is its emitter resistance, (to) is the synchronization signal input terminal, (g)
is a synchronization signal. In this circuit, the differential amplifier composed of NPN transistors α and αe is an NPN
) NPN by transistor Qυ ) transistor (II
Negative feedback is provided to the base of , so when (2) is input and the ring base is considered output, these act as a buffer with a gain of 1 (.
Then, when operating as a buffer, the voltage applied to R16 is 0. Since it is a TV, the current value flowing through it is 1
16 becomes. Assuming that the current amplification factor hFE of the transistor aη is sufficiently large, the current values flowing through RlB and R18 are equal, so the voltage drop at R18 is as follows.

becomes. Conventional R18=IKΩ, R,6=6.5K
Since it is set to about Ω, the voltage drop at R18 is 10
It becomes 8mV. That is, due to the presence of this resistor, an offset of ΔV=108 mV is given to the input and output of the buffer (the output is lowered by 108 mV). Moreover, an NF'N transistor (resistor at the base of IQ) and a capacitor (5
) are wired in series, the capacitor (5) is charged with a voltage of -ΔV, the maximum voltage of the waveform of the video signal (1). Moreover, since the synchronization signal (E) which is synchronously separated is applied to the terminal (in Figure 1), the voltage comparator (6) slices it at △V below the synchronization signal tip voltage of the video signal (1). The NPN transistor which separates the synchronization and applies a synchronization signal from its output to the S&H circuit (8) flows only during the synchronization signal period and is off otherwise. By the above operation (11
), a voltage △V lower than the synchronization tip voltage is sampled and held.

However, in the case of the above configuration, the cutting level △V is always constant regardless of the input signal, so in the case of a weak electric field, the amplitude of the video signal (1) becomes small, and the synchronization separation output quickly stops or the video signal You can synchronize and separate them. Furthermore, in the case of signals with strong ghosts or VTR signals, the vertical synchronization signal may be distorted or small, resulting in poor vertical synchronization separation and the TV screen tends to be distorted.

The present invention was made to eliminate the above-mentioned drawbacks, and an object of the present invention is to provide a constantly stable television screen by changing the cut level ΔV depending on the input signal.

Embodiments of the present invention will be described below based on the drawings.

FIG. 4 is a block diagram showing an embodiment of the present invention. (a) is a low-pass filter, (b) is a vertical synchronizing signal separation circuit, (b) is a vertical synchronizing signal period detection circuit, (b) is a capacitor terminal for vertical synchronizing signal period detection, and (0]) is vertical synchronizing signal period detection capacitor, (to) vertical synchronization signal input terminal,
) is the vertical synchronization signal period input terminal. The signal separated in sync by the conventional sample-and-hold circuit (3) is output to the sync separation output terminal (7) and integrated by a low-pass filter (b) to eliminate the horizontal sync signal component and convert it into a vertical sync signal. is output from the low-pass filter (b). This signal is further waveform-shaped by the vertical synchronizing signal separation circuit () and output to the vertical synchronizing signal period detection circuit (-), and is also output to the vertical synchronizing signal input terminal (A). Terminal (a)
The vertical synchronization signal input to the S&H circuit (3) charges the capacitor (5) only during vertical synchronization 4. Fifth
The figure shows the signal waveform at that time. Figure 5(b) shows the terminal (
2) shows the vertical synchronization signal portion of the video waveform input.

(to) is the equivalent pulse, (to) is the vertical synchronization signal, and (to) is V
Indicates SLZOB voltage. The arrow in FIG. 5(a) shows the vertical synchronization signal output from the vertical synchronization signal separation circuit. Since the capacitor (5) is charged during the period (b), the VSLIcE voltage becomes high as shown in (b). In other words, the cutting level becomes shallower in the latter half of the vertical gap. Therefore, for example, as shown in Figure 5(c), if the vertical synchronizing signal is shortened as (s6a) due to ghosts or poor quality VTR tape, the vertical synchronization signal as shown in (a4a) in Figure 5(b) is The sync signal disappears from the rear. Therefore, disturbances in the amplitude of the vertical synchronizing signal appear as changes in the amplitude. The vertical synchronizing signal thus obtained is input to the vertical synchronizing signal period detection circuit 4, and is converted into the voltage of the capacitor OD according to its width. On the other hand, this voltage is output to the terminal (to) and enters the S&H circuit (3), changing the voltage of the capacitor (5). That is, FIG. 6(c)
The amplitude of the vertical synchronization signal becomes smaller as shown in (84a).
When the width of the vertical synchronization signal becomes narrower, V8LIOE
The voltage (b) becomes low and acts like a normal vertical synchronizing signal (ii). Therefore, even if the vertical synchronization signal becomes short due to ghosting, VTR, etc., the cutting level is automatically deepened so that the vertical synchronization period is constant, so that a stable screen can always be obtained. Furthermore, since the cut level in the first half of the vertical synchronization signal becomes deep (t), the detection time is stable and no jitter occurs. In a weak electric field, the amplitude of the video signal (1) becomes small, so if the cutting level is constant, there is a possibility that the video components will be synchronously separated. However, with the configuration of the present invention, the noise component included in the video signal (1) is output from the terminals (to) C, so the capacitor (5) is randomly charged according to if, and on average it becomes V8LIO.
The E voltage increases and the cutting level becomes shallower. That is, even if the video amplitude and synchronization amplitude become small due to a weak electric field, the cutting level becomes shallow due to noise, so that only the synchronization signal can be stably separated.

FIG. 6 is a circuit diagram showing an example of an S&H circuit used in the present invention. eon is an NPN transistor whose base is connected to the vertical synchronization signal input terminal. (stomach)(
b) is a resistor whose connection point is connected to the sample and hold capacitor terminal (4) to control the sampled and held voltage. (6) is a bias terminal, (I4- constitutes a differential amplifier with an NPN transistor. θ repulsion θ
F is a constant current source and (G) is a resistor. The vertical synchronizing signal (2) separated by the vertical synchronizing signal separating circuit (2) is input to the terminal (-). This signal is charged to the capacitor (6) by the NPN transistor (g). In other words, it works to make the cutting level in the latter half of the vertical gap shallower.

Further, the capacitor 0 is vertically synchronized and charged by an NPN transistor (8a) and a resistor (resistor), and a constant current is always drawn by Qfi. Therefore, a voltage corresponding to the vertical synchronization period 4 is applied to the capacitor (b). Vertical sync 4
If the gap is short, this voltage will drop, so the current value flowing to - will increase and the cutting level will become deeper.

As described above, according to the present invention, since the cutting level is changed depending on the state of the synchronization signal, a stable television screen can always be obtained.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a conventional sample-and-hold sync separation circuit; FIG. 2(a) is a diagram showing a video signal waveform including a sync signal; FIG. 2(b) is a diagram showing a sync signal output waveform; FIG. 4 is a circuit diagram showing a specific example of the S&H circuit in FIG. 1, FIG. 4 is a block diagram showing an embodiment of the present invention,
5(a) to 5(d) are signal waveform diagrams for explaining the present invention in detail, and FIG. 6 is a circuit diagram showing an example of the S&H circuit used in the present invention. Note that the same reference numerals in the figures indicate the same or corresponding parts. (3)...S&H circuit, (5)...
・Capacitor for song S&H, (6)・・・・・・Comparator for synchronization separation,）・・・・・・Low pass filter,）・・・・・・...superimposed synchronization signal separation circuit) ... Vertical synchronization signal period detection route agent Makoto Kuzuno - Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6

Claims (3)

[Claims] (1) Sample and hold the sync signal leading edge voltage of a video signal containing a sync signal or a voltage corresponding to the sync signal leading edge voltage, and compare the video signal including the sync signal with the sampled and held voltage. A synchronization separation circuit that outputs a synchronization signal integrates the synchronization signal output to output a vertical synchronization signal, and adjusts the sample-and-held voltage so that the synchronization interval of the output vertical synchronization signal is constant. A synchronous separation circuit characterized by controlling. (2) The synchronization according to claim 1, characterized in that the sample-hold voltage of the synchronization separation circuit is changed during the vertical synchronization period, and the change between the vertical synchronizations is performed in the latter half of the synchronization period. Separation circuit. (3) The synchronization separation circuit according to claim 1, wherein the sample-and-hold voltage is changed depending on the noise component of the synchronization signal output.