JPS59212036A - Program channel selecting device - Google Patents

Abstract

PURPOSE:To eliminate the need for special operation for storing a program in a memory by writing the state of channel selection in the memory in program form from a channel control means as it is on the basis of channel selecting operation performed through a commanding means. CONSTITUTION:A tuner A is switched automatically; according to a selected channel by controlling a remote control means provided in the channel control means B according to program information read out of the memory D. When the program information is written, it is inputted by the commanding means C during the switching of the channel means, and channel information on a channel selected by the tuner A through the channel control means B is taken out of the channel control means B and written and stored as the program information in an address specified by the address switching means E of the memory D together with time information.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention is used in television receivers, etc., in which channels to be selected by a tuner are programmed in advance and stored in memory, and channels are selected according to this stored program. 1, which relates to a program selection device that controls
゜Conventional configuration and its problems When a conventional program selection device stores, for example, one week's worth of channel information in memory, all write addresses in the memory can be stored by operating a keyboard or the like. While switching, the time at which all channels should be switched (hour and minute) and the channel to be selected at that time were input in the IIFj next in association with each other, and written to each channel in memory33. The writing operation must be performed using a completely different special operation, and this operation is time-consuming and extremely burdensome.

Purpose of the Invention The present invention focuses on the periodicity of broadcast programs such as television broadcasts at a certain period (for example, -week), and inputs them as program information into memory as they are when performing daily channel selection operations. The purpose is to provide a program selection bag Rk 4M with a small memory capacity and practical operability. .

Structure of the Invention The present invention provides a means for storing a program in a memory in a channel selection device used in a television or the like that controls the selection of a predetermined channel at a predetermined time according to a program stored in the memory in advance. , the channel selection state is determined based on the channel selection operation by the command means actually performed by the user over a period of, for example, one week during normal real-time use. By writing the program into the memory from the channel control means, there is no need for a special operation to store the program in the memory.

DESCRIPTION OF EMBODIMENTS A television program selection device according to an embodiment of the present invention will be described below with reference to the accompanying drawings.

First, the configuration of this device will be explained by showing the configuration of this device using functional blocks in Figure 1. In the figure, A is a tuner that selects the channel of the television broadcast to be received, and B is a tuner that applies voltage to the tuner. This channel control means generates a control signal for controlling all of the selected channels. This channel control-1B includes a remote control signal generation means using a microcomputer, and a tuner control means for controlling Ai based on the remote control signal.

Further, C includes a keyboard which is actually operated by the user at the time of manual switching in order to manually switch the channel selected by the tuner, and inputs channel information to the channel control means B to select the channel 6 channel to be selected. It is a means of command.

Furthermore, D is for example 16 channels for automatic switching according to the entire program selected by the tuner.
It is a memory that stores minute-by-minute program information for, for example, one week, and has, for example, 672 types of addresses.

E is the write/read address of the memory D, for example 1.
Address switching means that switches and specifies addresses at fixed time intervals such as 6-minute intervals and circulates the address specifications at a fixed cycle; F is input by the command means C during the manual switching and is selected by the tuner via the channel control means Bi. A writing means takes out the channel information from the channel control means B and writes and stores it as program information in the address designated at that time in the memory D, and G is a memo IJ.
]) from the program information--reading times at fixed intervals, for example, 0 minutes and 16 minutes every hour.

By reading out the 3 minutes and 45 minutes and inputting all the channel information to the channel control means BK based on the program information, the reading means automatically switches the selected channel by the tuner based on the program information. be.

These address switching means E, writing means F and reading means G may also be implemented by the microcomputer used in the channel controller 1-roll means B.

As mentioned above, in this device, all the channels selected by the tuner are controlled by the remote control IC, and the program read from the memory D is provided in the channel control unit 12B or the control unit 12B. By controlling the information one by one, the selected channel is automatically switched according to the entire program. Further, a memory D in which write/read addresses are switched at regular intervals (referred to as step time) is used as a memory for storing program information. The step time is 15 minutes here, and every hour is 0 minutes', 15 minutes.

30 minutes, 45 minutes. Further, the addressing of the memory D is repeated every week. The timing relationship among address resent, address switching, read, write, and write permission time of the program memory D is extremely important. .

Now, to explain specifically using the above example, the timing of reading from the memo IJ]) is at 0 and 15 minutes of every hour.

30 minutes, 45 minutes 1, step time 1d As mentioned above, it is 16 minutes, so when resetting the address, the memory read time must match either of these times correctly.

In general, manual channel switching operations when using all TV channels will cause broadcast programs to change at 0 minutes, 16 minutes, 30 minutes, and 4 minutes after the hour.
Since the change occurs every 5 minutes, it is thought that the occurrence occurs intensively before and after this readout time, so write it to the channel selection register in the RAM in the remote control microcomputer, and then write the final channel selection. Write to memory D. Therefore, if the channel is manually switched several times during the write permission time of, for example, 5 minutes each, before and after the read time, the channel selection information is updated one after another in the channel selection register. When the write permission time ends, the information in the channel selection register is written to the program memory D. On the other hand, it is necessary to switch the address before reading, but if there is no channel selection register, it is necessary to switch the address before the write permission time (ie, 6 minutes before the read time).

FIG. 2 1d is a block diagram showing an embodiment of the present invention. 1
lr: i microcomputer, 2 is a program memory consisting of four 1-bit RAM, 3゜3/,
311 is a latch for address output, 4 is WE (write
6 is an I10 port, and 6 is an internal pass line. 7 is a crystal oscillator for clock, 8-digit clock oscillator, 9 is a clock divider, 10 is a counter, 11 (dALU, 12 is an accumulator, 13 is a register stack pointer, 14
is RAM.

16 is a program counter, 16 is a ROM, 17 is an instruction decoder, 18 is an output port, 19 is an input port, 20 is a keyboard, 21 is an input port, 22 is a mode selection switch, 23 is a reset switch, 24 is an output port, 26 is an amplifier for remote control signals, and 26 is an infrared diode for remote control signal amount and power.What is inside the dotted line 27 is on the chip of the microcomputer 1.The power supply is omitted. 28 is a photodiode for receiving a remote control signal, 29 is a tuner, and 28' is a control circuit for controlling all selected channels of the tuner 29 using remote control signals.

In FIG. 2, when the mode selector switch 22 is opened and the write mode is set, the keyboard 2o serving as the command means C is a manual remote control channel command keyboard, and one of them is operated. By specifying a channel, a pulse code string of the type corresponding to each selected channel is generated in the microcomputer 1, and is outputted from the output port 24 to the remote control signal amplifier 25.
'j The diode 26 is driven to output an infrared remote control signal. This 'J-1? - A control signal is received by the phototransistor 28 and applied to the tuner control circuit 28', so that the channel actually commanded from the keyboard 20 at that time is selected by the tuner 29. This chew control circuit 2
8' is the channel control means B in Fig. 1.
include. .

Separately, the output of the clock oscillator 8 is divided into a frequency divider 9. The frequency is divided by a counter 1o, and an interrupt is generated every 0.6 seconds.

This interrupt is used to generate a timing signal within the microcomputer 1 using software. Now, an interrupt occurs every 0.5 seconds, the step time for address switching by the address switching means F is 15 minutes, the address cycle time of memory 2 is 7 days, and writing is permitted for 5 minutes before and after the read time. It is assumed that the last selected channel information within the time period is written into the memory 2. Writing to the memory 2 is done immediately after the end of the write permission time, and the address switching timing is just before the end of the write permission time.

The timing relationship at this time is shown in the time chart of FIG. 3o is the read time that is synchronized with the time, and is accurate to each 0.
The time can be set by pressing the reset switch 23 according to any of the minutes, 16 minutes, 30 minutes, and 45 minutes. Third
In the figure, 31 is a memory address signal, 32 is a WE (write enable) signal for memory 2, and when this is 1'', writing is possible. 33 is an R/W (read/write) signal.
At the rising edge from "o" to 9'1, the signal on the data bus is written to the memory 2. 34 writes the tuning information to the tuning register (described later, see Figure 3) in the microcomputer 1. The time range is 1".

The narrower the width of this range, the more it reflects the operator's intention. On the other hand, if it is too narrow, information will be missing. Also, if you widen it forward, information from one step before will be mixed in, and the fourth step will be mixed in.
As shown in the figure, if you widen the area later, the result of your selection will be reflected more strongly. However, this is also an option.

FIG. 6 shows the address switching counter with microcontroller 13.
-One! 2 is a table of the locations and addresses allocated to a part of the RAM 14 inside the computer 1.

FIGS. 6A and 6B are flowcharts showing this operation.

TO to T++ in FIG. 6 are 12-bit counters that count 600 0.5 second input signals using software to count 5 minutes. T12 and Tls are 2-bit counters that count three 5-minute inputs to count 15 minutes. TMF is a timer mode flag, and the mode changeover switch 22 in Fig. 2 is switched to auto mode (a mode in which the channel is automatically selected based on the FIAM channel selection information when the tap reading time comes). The hour is set to °゛1'', and when the mode is switched to manual mode (i.e., the mode in which automatic channel selection is prohibited), it is set to ``o''. 34 is °゛1
This is a flag that becomes 1 when ``. Ao to A9 are address counters that count 672 addresses for 7 days in 16 minute steps.

In the flowchart of FIG. 6(A), 4o beam 14
”-- Occurs every 0.6 seconds when interrupt is started by timer.

When a timer interrupt occurs, first each current register is saved (41), and the 5-minute counter 42 (address 5F~
6D)'i Increase by one. 36 minute counter 42
The software is configured to reset when the count reaches 600 (43).

When the 5 minute counter is reset, the 15 minute counter 44 is incremented by one. When the 15 minute counter is 6 minutes (45), the WEF is reset and the Wx output and Ft/W
An output is output (46).

TMRl and TMR2 refer to timers formed by software.

Next, when the 16 minute timer reaches 10 minutes (47), WEF is set and the address counter 48 is set.
The contents of address output latches 3 and 3' in Figure 2 are
, 3' (49). 15 minute timer is 16
At the minute (50), when the mode selector switch is in auto mode (51), a tuning signal is output (+52). When the mode switch is set to manual (53), no tuning signal is output. Then, the address counter 48 is incremented by 15/-'. The address counter 48 is reset after counting 672 (
54).

The return path of all of the above operations restores the registers that were initially saved (66), the interrupt ends, and the program returns to the original program.

The operation of the address counter and the mechanism for generating each timing have been described above.

Next, the flow of channel selection information will be explained. FIG. 71 is a block diagram showing the acquisition of selected channel information, and FIGS. 7(A) and (B)I are flowcharts showing the operation. Switches SW1 to SW+2 in Figure 1
．． is a group of channel selection buttons, and the switch SW is included in the channel number register 61 as channel number data.
1~5W12 corresponds to +1 in hexadecimal ``~゛''
The 3-scan counter 62 that writes "C" sequentially sets one of the bits of the output lunch 18 to "1" and scans the keys.The circuit shown in FIG. 14 is RA
M.

19 is an input port. These are connected to ALUll and the accumulator 12 by a bus 6.

The flowchart of Fig. 8 (A), ■) is shown in Fig. 6 (A),
(2) operates by interrupts, whereas it is configured as part of the overall program loop. Also, detailed parts such as chattering prevention are omitted. 66 is the output latch 18
This is a program to ensure that only one bit is '1'', and when multiple bits are 11'', only the most significant bit remains, and all bits are 1-75 (when it is 'O', the least significant bit is '0').
1". Next, at 66, this is output from the output latch 18, and the signal from the input port 19 is taken into the accumulator 12 (67). If there is no input, (the hit key is not pressed) (6B) shifts the scan counter 62 to the left by one (69) and moves to the next program.When there is an input (7o), the input values from the input port 19 are 1+1 and n2, respectively. +1, 4
1411°+8” (binary number) as ’1”, ’°2”, ’
3”.

+4” (decimal number) and write it to the temporary memory 63 (71). If there are multiple inputs, (72) 17.
.

Return to the original state in the loop and import the data again (67).

After inputting the input into the temporary memory 63 (73), the data of the output latch 18 is determined and the data of the output latch 18 is
“0” corresponding to ’1 ”, °° ”, ’°4”,
@ゝ4", +8" into accumulator 12 (74
), and the contents of the temporary memory 63 are added and stored in the channel number register 61 (76). If the mode is manual mode (7) R (76), this data is written to the channel selection register (77).

Then, a channel selection signal is output (78) in accordance with this.

When the data of the aforementioned output latch 18 is 8 (79),
Since a key other than the channel selection key is pressed, the process branches to remote control processing for the song (80). In this way, the circuit configuration shown in FIG. 2 can perform the desired operation.

Also, as shown in FIG. 9, in FIG. 6 (R), the channel selection data from the RAM at the read time is compared with the data in the channel number register 61 (56), and if they match, the channel selection operation is performed. It can also be configured not to tune the same channel to the same address over n (n is an integer greater than or equal to 2) cycles of memory addressing, for example over n weeks. By adding a discrimination program to the RAM, the selected channel data is effectively input to that address only when the selected channel data is input, and only when the same channel is received for n consecutive weeks. It is also possible to configure the selected channel information to be programmed.

Effects of the Invention As explained above, the program selection device according to the present invention allows program input of a selected channel under almost natural usage conditions, and no special program input operation is required. Therefore, it is possible to provide a convenient program selection device suitable for use in television receivers and radio receivers.

[Brief explanation of the drawing]

1 and 2 are block diagrams showing the structure of a program selection device according to an embodiment of the present invention, FIGS. 3 and 4 are timings 19 and 5 showing the operation of the same device, and FIG. FIG. 6A is a diagram showing the positions and addresses of counter flags related to address counters in the RAM in the microcomputer used in the same device.
(B) is a flowchart of the address counter and various timing generation in the same device; FIG. 7 is a partial block diagram of the key human power section of the device and a diagram showing the positions and addresses of register flags related to the channel selection register in the internal RAM; Figures 8 (A) and (B) are flowcharts showing the channel selection operation of the same device, and Figure 9 is a flowchart of the part that prohibits automatic operation when the same channel is the same as the channel that the device was receiving immediately before. . A...Tuner, B...Channel control means, C...Command means, D...
・Memo IJ-1E・・・Address switching means, F・
...Writing means, G...Reading means, 1...
...Microcomputer, 2...Program memory, 14...RAM, 16...
・Program counter, 16...ROM, 2
0... Keyboard, 22... Mode changeover switch, 23... Reset switch, 25
...Remote control signal amplifier, 26
...Infrared diode, 2B...Photodiode, 28'...Control circuit, 29...
...Chew. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 4
Figure R/'1Mt Ground Figure 6 (Bl Figure 7 Figure 8 (13) Figure 9 215-

Claims (3)

[Claims] (1) A tuner for selecting a receiving channel, a channel control means for generating a control signal applied to the tuner to control the selected channel, and a switching means for manually switching the channel selected by the tuner. A command means that is actually operated by the user at the desired time and inputs channel information indicating the channel to be selected to the channel control means, and stores program information for automatically switching the selected channel by the tuner according to a program. an address switching means that switches and specifies the write/read address of the memory at a constant time interval and cycles the address designation at a constant cycle;
Writing means for writing and storing the channel information inputted by the command means at the time of the manual switching and selected by the tuner and used as the program information in the address designated at that time in the memory. Then, by reading out the program information from the memory at readout times at regular time intervals and inputting all channel information to the channel control means based on the program information, the selected channel in the tuner is controlled according to the program information. A program selection device equipped with reading means for automatically switching based on the program. (2) The writing means stores channel information of the channel last selected during a predetermined period after the time when the selected channel is switched by the reading means and before the next switching time. 2. The program selection device according to claim 1, wherein the program is written to an address to be read during a period. (3) The writing means stores the channel information 11-memory only for addresses to which the same channel information has been input after n cycles (n is an integer of 2 or more) of address designation by the address switching means. The program selection device according to claim 1, wherein the program selection device is configured to write.