JPS59207658A - Semiconductor device having schottky electrode - Google Patents

Semiconductor device having schottky electrode

Info

Publication number
JPS59207658A
JPS59207658A JP58082070A JP8207083A JPS59207658A JP S59207658 A JPS59207658 A JP S59207658A JP 58082070 A JP58082070 A JP 58082070A JP 8207083 A JP8207083 A JP 8207083A JP S59207658 A JPS59207658 A JP S59207658A
Authority
JP
Japan
Prior art keywords
bonding pad
bonding
layer
schottky
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58082070A
Other languages
Japanese (ja)
Inventor
Masamitsu Yamauchi
山内　正充
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP58082070A priority Critical patent/JPS59207658A/en
Publication of JPS59207658A publication Critical patent/JPS59207658A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/47—Schottky barrier electrodes
    • H01L29/475—Schottky barrier electrodes on AIII-BV compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01024—Chromium [Cr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1032—III-V
    • H01L2924/10329—Gallium arsenide [GaAs]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1203—Rectifying Diode
    • H01L2924/12032—Schottky diode

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To prevent the occurrence of purple break, by forming a bonding part for a Schottky electrode by a Schottky material and a Cr-Ti bonding material, thereby avoiding the separation of metal at a bonding pad part. CONSTITUTION:An Al Schottky gate electrode is formed on a GaAs substrate 1 and extended in the lateral direction of the substrate, and an Al layer 2 is provided. An insulating film 3 is formed on the layer 2, and an opening part for forming a bonding pad part is provided on the Al layer. Cr 8 is deposited on the semiconductor substrate 1 and the opening part of the bonding pad part is coated. On the Cr 8 of the bonding pad forming part of the semiconductor substrate 1, Ti 4, Pt 5 and Au 6 are sequentially deposited, and a bonding pad is formed.

Description

【発明の詳細な説明】 不発明はショットキー電極をもつ半導体装置。[Detailed description of the invention] The uninvention is a semiconductor device with a Schottky electrode.

例えばＧａ　Ａｓ電界効果トランジスタのゲート電極の
ボンディングワイヤー接続部の構造に係る。For example, it relates to the structure of a bonding wire connection portion of a gate electrode of a GaAs field effect transistor.

近年超高周波帯で使用する半導体装置として、ショット
キーゲートのＧａＡｓ電界効果トランジスタが提案され
実用段階に入っている。ショットキー金属としては一般
的にはＮｇが用いられているが、ＡＪはＡｕと反応して
脆弱なパープルプレイブを形成するので、ゲート電極の
ボンディングワイヤー接続部（以下、ボンディングパッ
ト部といり）はＴｉ−Ｐｔ−Ａｕで形成されている。ゲ
ート電極のショットキーＡ［とボンディングバラ）　部
Ａｕがパープルプレイブを形成する事が無いように、Ａ
ｌはＴｔ−ｐｔと接続され、Ａ［の表面から数μ以上離
れた領域のＴｉ−ｐｔ上にポンディング用のＡｕ層が形
成されなければならない。In recent years, a Schottky gate GaAs field effect transistor has been proposed as a semiconductor device for use in an ultra-high frequency band, and is now in practical use. Ng is generally used as the Schottky metal, but AJ reacts with Au to form a brittle purple plave, so the bonding wire connection part of the gate electrode (hereinafter referred to as the bonding pad part) is is made of Ti-Pt-Au. In order to prevent the Schottky A [and bonding rose] part Au of the gate electrode from forming a purple plave,
l is connected to Tt-pt, and an Au layer for bonding must be formed on Ti-pt in a region separated by several microns or more from the surface of A[.

この様に形成されたゲート電極のボンディングパット部
はパープルプレイブに対しては有効であるが、Ｇａｐｓ
基板と接するＴｉ層の密層性が悪いために、ボンディン
グパット部に外部引き出しのためのＡｕ　ワイヤーをボ
ンディングする際、　０ａ７ＬｓとＴｉの界面でボンデ
ィングパット部の金属がはがれるという欠点があった。The bonding pad portion of the gate electrode formed in this way is effective against purple plaits, but gaps
Due to the poor layer density of the Ti layer in contact with the substrate, there was a drawback that when bonding an Au wire for external extraction to the bonding pad, the metal of the bonding pad peeled off at the interface between 0a7Ls and Ti.

本発明はショットキーメタルをゲート領域からそのまま
ボンディングパット領域まで延在させ、このボンディン
グパット領域のＡＩＪ層上にＣｒ　を介してＴｔ−ｐｔ
およびボンディング材料と同じメタル層を設けた構造と
したことを特徴とし、ボンディングパット部でのメタル
の剥れをなくシ、かつパープルプレイブの発生を防止し
た半導体装置を提供するものである。In the present invention, the Schottky metal is extended directly from the gate region to the bonding pad region, and Tt-pt is deposited on the AIJ layer in the bonding pad region via Cr.
The present invention also provides a semiconductor device which is characterized by having a structure in which the same metal layer as the bonding material is provided, and which eliminates peeling of the metal at the bonding pad portion and prevents the occurrence of purple plaave.

まず、従来のＧａＡｓ電界効果トランジスタのホンディ
ングバット部の構造について図面を用いて詳細に説明す
る。First, the structure of a honding butt portion of a conventional GaAs field effect transistor will be described in detail with reference to the drawings.

第１図は従来のＧａ　Ａｓ電界効果トランジスタのボン
ディングパット部の断面図であシ１はＧａＡｓ基板、２
はグー）Ａ［電極の引出部、３はシリコン酸化膜若しく
はシリコン窒化膜等の絶縁膜、４は’ｌ’ｉ層、５はＰ
ｔ層、６はＡｕｌ’ｉｉ％７は該バット部にボンディン
グされたＡ、ｕ線ｆそれぞれ示す。Figure 1 is a cross-sectional view of the bonding pad portion of a conventional GaAs field effect transistor.
A [Leading part of the electrode, 3 is an insulating film such as silicon oxide film or silicon nitride film, 4 is the 'l'i layer, 5 is P
t layer, 6 indicates Aul'ii%, 7 indicates A bonded to the butt portion, and U line f, respectively.

それぞれの膜厚はＡ／二３０００　Ａ、絶縁膜宇２００
０３００（ｌが一般的である。この様な構造を有するボ
ンディングパット部はＡｌ１層４はその終端部において
Ｔｉ層５と接続され、このＴｉ層がＧａＡｓ基板のボン
ディングパット上に設けられている。Ａｕ線７はＡｕ層
６と接続されているのでパープルプレイブが発生する事
は無い。The thickness of each film is A/2 3000 A, and the insulating film is 200 A/2.
0300 (l is common.) In the bonding pad portion having such a structure, the Al1 layer 4 is connected to the Ti layer 5 at its terminal end, and this Ti layer is provided on the bonding pad of the GaAs substrate. Since the Au wire 7 is connected to the Au layer 6, no purple play occurs.

しかしＧａＡ、ｓ基板とＴｉ層との密着性が悪いので％
Ａｕ線７とｌＬｕ層６をボンディングする際。However, due to poor adhesion between the GaA and S substrates and the Ti layer,
When bonding the Au wire 7 and the lLu layer 6.

Ｔｉ層４とＧａ八へ基板１の間でボンディングパット部
の金属が剥れるという現象が多発していた。A phenomenon in which the metal at the bonding pad portion between the Ti layer 4 and the Ga substrate 1 was peeled off occurred frequently.

またボンディング時にはそのような剥れが生じなかった
としても、その後の使用状態で接着力の低下しているボ
ンディングパット部での断線が生じることが多かった。Further, even if such peeling does not occur during bonding, wire breakage often occurs at the bonding pad portion where the adhesive strength has decreased during subsequent use.

次に不発明の好ましい一実施例について第２図乃至第４
図を用いて詳細に説明する。Next, FIGS. 2 to 4 show a preferred embodiment of the invention.
This will be explained in detail using figures.

第２図ではＧａ　Ａｓ基板１上に形成されたＩ’ｌｌシ
ョットキーゲート電極を基板横方向に引出してＡ１層２
が設けられている。この上に絶縁膜３を形成し、フォト
エツチング法によ多ポンディングパッド部形成のための
開孔部＝ｉＡ／層上に設ける。第２図に於てＡ６はおよ
そ３０００Ａ、絶縁膜３はおよそ２００ＯＡの膜厚であ
る１次に半導体基板１上にＣｒ　Ｂ　６およそ２０００
〜３０００　Ａ被着させ、ホンディングバット部の開孔
部を被覆する。これはフォトエツチング法或いはリフト
アウェイ法によって形成できるが、この際開孔部の周辺
の絶縁膜の端部とＣｒ膜とをオーバーラツプさせた方が
良い。In FIG. 2, an I'll Schottky gate electrode formed on a GaAs substrate 1 is drawn out in the lateral direction of the substrate, and an A1 layer 2 is formed.
is provided. An insulating film 3 is formed on this, and an opening for forming a multi-ponding pad portion is provided on the layer=iA/layer by photo-etching. In FIG. 2, A6 has a thickness of approximately 3000A, and the insulating film 3 has a thickness of approximately 200OA.
~3000 A is applied to cover the opening of the honding butt part. This can be formed by a photoetching method or a lift-away method, but in this case, it is better to overlap the edge of the insulating film around the opening and the Cr film.

この状態を第３図に示す０次に半導体基板１のポンディ
ングパッド形成部のＯｒ　８上にＴｔ　４．　ｐｔ膜厚
でこの順に被着し、ポンディングパッドを形成する。こ
の状態を第４図に示す。This state is shown in FIG. 3, where Tt4. A PT film is deposited in this order to form a bonding pad. This state is shown in FIG.

この様にして形成された不実施例によるボンディングバ
ットはＧａ　Ａｓと密着性の曳いＡＡがボンディング下
においてＧａＡｓと接しているので、ボンディングの際
にポンディングパッド部の金相がＧａ　Ａｓから剥れる
事が皆無となった。また、　’Ｉ”ｉ　−Ｐｔ−４ｕと
ＡＩの界面にＬｕに対してバリアー性の優れているＣｒ
を導入した事によ一す、ＡｕとＡｊがパープルプレイブ
を形成する危険も解除された。In the non-example bonding butt formed in this manner, the AA which is in close contact with GaAs is in contact with GaAs under the bonding, so the gold phase at the bonding pad part peels off from the GaAs during bonding. Everything went away. In addition, Cr, which has excellent barrier properties against Lu, is added to the interface between 'I''i-Pt-4u and AI.
By introducing this, the danger of Au and Aj forming a purple plave has also been removed.

更に本構造は別の利点も有する。すなわち、第１図に示
した従来のポンディングパッドの構造ではＡＩとＴｉ−
ｐｔ　　の接触面積が小さいためにＡｌの表面状態によ
ってはこの界面で抵抗を持ち良好なオーミ、り接触が得
られないという欠点があったが１本構造ではＡＡとＣｒ
−Ｔｉ−Ｐｔの接触面積　５− が非常に拡大されたために、Ｉ’ｔｌの表面状態の如何
にかかわらず良好なオーミック接触が得られる。Furthermore, the present structure has other advantages as well. That is, in the structure of the conventional bonding pad shown in Fig. 1, AI and Ti-
Since the contact area of PT is small, depending on the surface condition of Al, there is resistance at this interface and good ohmic contact cannot be obtained, but in a single structure, AA and Cr
Since the -Ti-Pt contact area 5- has been greatly expanded, good ohmic contact can be obtained regardless of the surface condition of I'tl.

不発明の実施例に於ては特に電界の大きいＧａＡｓ基板
に直接ポンディングパッドを設ける例について説明した
が、　Ａ−１はシリコン酸化膜、シリコン窒化膜等の絶
縁膜に対してＴｉよりも密着性が良いので、これら絶縁
膜上にポンディングパッドを設ける際にも本発明がその
効果を発揮する事はいうまでもない。In the non-inventive embodiment, an example in which a bonding pad is provided directly on a GaAs substrate with a particularly large electric field has been described, but A-1 adheres more closely to an insulating film such as a silicon oxide film or a silicon nitride film than to a Ti film. It goes without saying that the present invention is also effective when providing bonding pads on these insulating films.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来のＧａｐｓＦＥＴ　のボンディングパ、ド
部の構造を説明するためのポンディングパッド部の断面
図、第２図乃至第４図は不発明のポンディングパッドの
構造を説明するための各工程断面図である。 １・・・・・・ＧａＡｓ基板、２・・・・・・ゲート電
極引出部のＡＬ、３・・・・・・絶縁膜、４・・・・・
・ボンディングバットのＴｉ１５・・・・・・ボンディ
ングパットのＰｔ、６・・・・・・ボンディングパット
のＡｕ、７・・・・・・ボンディング　６一 ワイヤーのＡｕ、８・・・・・・ボンディングパ、１・
のＣｒ。 第１劇 箭？図FIG. 1 is a sectional view of a bonding pad section for explaining the structure of a conventional GapsFET bonding pad, and FIGS. 2 to 4 are cross-sectional views for explaining the structure of an uninvented bonding pad. It is a process sectional view. DESCRIPTION OF SYMBOLS 1...GaAs substrate, 2...Al of gate electrode extraction part, 3...Insulating film, 4...
・Ti15 of bonding butt...Pt of bonding pad, 6...Au of bonding pad, 7...bonding 6-Au of wire, 8...bonding Pa, 1.
Cr. The first drama? figure

Claims (1)

【特許請求の範囲】[Claims] ショットキー電極のボンディング接続部がシヨ、トキー
材料−Ｃｒ−Ｔｉ　　＋ボンディング材料より成る事全
特畝とする半導体装置。A semiconductor device in which a bonding connection portion of a Schottky electrode is entirely made of a Schottky material - Cr-Ti + bonding material.
JP58082070A 1983-05-11 1983-05-11 Semiconductor device having schottky electrode Pending JPS59207658A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58082070A JPS59207658A (en) 1983-05-11 1983-05-11 Semiconductor device having schottky electrode

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58082070A JPS59207658A (en) 1983-05-11 1983-05-11 Semiconductor device having schottky electrode

Publications (1)

Publication Number Publication Date
JPS59207658A true JPS59207658A (en) 1984-11-24

Family

ID=13764221

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58082070A Pending JPS59207658A (en) 1983-05-11 1983-05-11 Semiconductor device having schottky electrode

Country Status (1)

Country Link
JP (1) JPS59207658A (en)

Similar Documents

Publication Publication Date Title
JP2772606B2 (en) Method for forming a bump structure on an integrated semiconductor device
JPS59207658A (en) Semiconductor device having schottky electrode
JPH05243323A (en) Semiconductor device and manufacturing method
JPS6054462A (en) Semiconductor device
JP2003115512A (en) Semiconductor device
JPH04258125A (en) Semiconductor device
JPH0284725A (en) Semiconductor device and manufacture thereof
JPH0373535A (en) Semiconductor device and manufacture thereof
JP3259641B2 (en) Protective film structure of semiconductor device
JPS61170056A (en) Electrode material for semiconductor device
JP2530932B2 (en) Field effect transistor and method of manufacturing the same
JP2621543B2 (en) Method for manufacturing compound semiconductor device
JPS61112361A (en) Semiconductor device
JPH04206842A (en) Formation of pad
JPH05275501A (en) Semiconductor device
JPH08181164A (en) Semiconductor device
JP2530933B2 (en) Field effect transistor and method of manufacturing the same
JPH05251497A (en) Semiconductor device
JP2000357701A (en) Semiconductor device and manufacture thereof
JPS5823451A (en) Semiconductor device
JP3246348B2 (en) Protective film structure of semiconductor device
JPH09213653A (en) Semiconductor device
JPS60154683A (en) Schottky barrier diode
JPS59224180A (en) Semiconductor device
JPH01318240A (en) Manufacture of semiconductor device