JPS59144964A - Central processing unit - Google Patents

Abstract

PURPOSE:To expand easily a physical address space larger than a logical address space by providing a central processing unit (CPU) with a bank control register forming an expanding physical address signal exceeding an address space specified by a logical address signal. CONSTITUTION:A microprocessor consists of an arithmetic part, a control part and a register part and the register part is provided with a register (bank control register BCR) forming an address signal to expand the physical address space. A specific bit signal from the register BCR is used as an address signal to expand the address space and other bits are used as control signals for expanding functions. The contents of the register BCR are transmitted to a decoder circuit DCR and expanding address signals A16-A18 corresponding to said expanding functions are formed by the decoder circuit DCR.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a central processing unit, and, for example, to a technique effective for a one-chip microprocessor constituting a microcomputer.

[Background technology]

In a conventional 8-bit microprocessor,
It has a 16-bit address line (logical address signal). Therefore, its maximum address space is approximately 64
Up to K. However, in such an address space,
Memory capacity is insufficient for information processing using high-level languages that requires a huge number of program steps, so the AT/S signal for expansion is sent from the data terminal and taken into the external launch circuit. It is used for expanding the address space (physical address signal).

Since such a physical address expansion method requires an external circuit as described above, the price of the microcomputer system increases accordingly. Also,
-F Since an address signal is sent to the external circuit from the data terminal, its control is complicated, and it has the disadvantage that only a simple expansion operation can be performed.

[Purpose of the invention]

An object of the present invention is to provide a central processing unit that can easily extend a physical address space to a logical address space.

Another object of the invention is to provide a central processing unit with an improved address setting function in an expanded physical address space.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical aspects of the invention disclosed in this application is as follows.

In other words, by providing a bank control register in the central processing unit that forms a physical address signal for expansion beyond the address space specified by the logical address signal, it is possible to realize programmer-friendly expansion of the physical address space. be.

Hereinafter, the present invention will be explained in detail together with examples.

〔Example〕

FIG. 1 shows a block diagram of a central processing unit (hereinafter referred to as a microprocessor) to which the present invention is applied.

Although not particularly limited, the microprocessor shown in the figure is formed on a single semiconductor substrate such as silicon by a known semiconductor integrated circuit manufacturing technique. Although not particularly limited, this embodiment shows an 8-bit microprocessor having a logical address signal of 1 (hit).

The microb 11U module of this embodiment is divided into functional parts: an arithmetic section, a control section, and a register section. That is, the arithmetic unit performs arithmetic operations and logical operations, and includes an arithmetic and logic operation unit Δ1, U, an accumulator ACC, an accumulator latch FF, a temporary register R1, a flag Frisopfl:1, BU F1. G.
It consists of IO base correction BCI), etc.

The control part 10 controls the function of the microb l:1 sesoza.
It consists of an instruction register OPR, an instruction decoder and a Masson Reichlconcoder OI DCR, and a timing and control circuit 1c'J-.

The register section has functions such as master registers 1 and 2 and internal memory in one setter, working registers for rJt, temporary registers R2 to R8, and registers S
P, program counter Pc, incrementer/decrementer and address launch AD, register selection circuit S
It consists of L, multiplexer MPX, etc. The logical address signals AO to A15 of the address launch are outputted via the address buffer ADB.

In this embodiment, this register section is provided with a register (hereinafter referred to as a bank control (call register BCR)) that forms an address signal for expanding the physical address space. A specific focus signal of this register BCR is used as an address signal for expanding the address space, and other bits are used as control signals for the expanded function. The contents of this register BCR are transmitted to the decoder circuit DCH, and the contents of this register BCR are transmitted to the decoder circuit DCH.
Therefore, the extension address signal A1 according to the above extension function is
6 to A1B are formed.

A specific embodiment of the register BCR and decoder circuits DC and R will be described with reference to the block diagram of FIG.

This register BCR is an 8-bit register like the other registers, and its bit configuration is set as follows.

Although not particularly limited, in the 0.1th pill-3M5 part,
A signal that determines the size of the common memory area is set, and this 2-bit signal is decoded by the decoding circuit DEC.
．． 4.8.16, one of the four setting signals 1/4 is transmitted to the address monitor circuit AMl.

The ff12.3.4 bit BN section is set with memory bank information, or in other words, a signal corresponding to an address signal for expanding the physical address space. These 3-bit signals BNO to BN2 are inputted to the gate circuit 1/8 G1, and information conversion is performed in accordance with control signals for extended functions, which will be described next.

The 5th and 6th bit BC section has four types of expansions described below! J
l! A bank control signal T3 that specifies one of the functions.
GO and BCI are set and, although not particularly limited, are manually input to the next AND gate circuits G3 to G5.

Information for controlling the extended function itself by this register BCH is set in the seventh bin MD section.

The above AND gate circuit G3. The bank control signal BCI is applied to one input of G4, and the program fetch signal PRG and data fetch signal DAT are applied to the other input.
A is applied respectively.

Although not particularly limited, if the output signal of the AND gate circuit G3 is logic "]", the memory bank signal BNO corresponding to the expansion address signal A16 is set to logic "°0",
If the output signal of the antgame circuit G4 is logic "1", the memory bank signal BNO corresponding to the expansion address signal Δ16 is set to logic "1".
Round 1 Raku G3. If the output signals of G4 are both logic "O", write J2 and register memory bank NINAA BNO~BN of register BCR.
2 is directly sent to the next gate circuit G2 through the gate circuit G1.

The address monitor circuit AM is applied with a signal of the lower five bits of the logical address signal All to AI5. For example, if the common memory area is set to 2K, if the above address signals 1-Al1"A15 are all logic "0", in other words, the address setting operation in the range from θ to 2K is performed by the logical address signal. For example, the output signal is set to logic "1".Also, when the common memory area is set to 4, the address signals A12 to A described in -
When the address signals A13 to A15 are all logic "0", when the address signals A13 to A15 are all logic "0", 16
In this case, when the address signals AI4.15 are all logic "0", the address monitor circuit M88M is as follows.
Assume that the output signal is logic "I". The output signal of this address monitor circuit AM and the bank control signal BCO are input to an AND gate circuit G5.
The gate circuit G2 is controlled by the output signal 2- of the gate circuit G2, and converts the signal to be transmitted. For example, if the output signal of 5 is logic "1" in the AND gate circuit M3, all bits of the output signal are set to logic "0" regardless of the operator's input, and the logic "0" is set to logic "0". ``If so, the human input signal is directly transmitted to the output.The output signal of this gate circuit G2 is sent out as address signals A16 to Δ18 for expanding the physical address space by UTIL the output buffer circuit OB.

The signal MD is not particularly limited, but is used as a control signal for the output cover sofa, and if the logic is "1", the gate circuit G2
The signal formed by the logic is sent to the output terminal as it is, and the logic
0”, force output terminal address holder AI6~A
18 is set to logic "0", in other words, it specifies the memory area of memory bank BAO, which will be described later.

FIG. 3 shows a block diagram showing t=physical address space expanded by the above embodiment.

A memory bank selection signal BA (+ to) 3 A 7 is formed by the address decoder 1/8 which receives the expansion address signals AI 6 to A 18 of the 3 hino 1-. By using this memory bank selection signal B A O (L2BA7), it is possible to identify, for example, eight 64 memory devices that receive the logical address signals S+A (l to A15), so the physical address space is expanded to eight times the logical address space. can do. Each of the above memory banks BΔO to B7 is
Although not particularly limited, 64 Quinamink type RAM
(random -1 access memory).

This embodiment does more than just extend the physical address space.1. It is equipped with the following types of extended functions set by control signals as in the above embodiment.

FIG. 4 shows a conceptual diagram of an address space in one embodiment. In this embodiment, the bank control signal BCO
is logic "0", indicating an extended function set by bank control signal BCI. If this bank control signal BCI is logic "0", AND gate circuit G3.G
Since the output signal of 4 becomes logic "0", the memory bank signals BNO to BN2 are transmitted as they are.
Due to the logic "0" of the bank control signal BCO, the output signal of the AND gate circuit G6 also becomes "0", and as described above, the gate G2 also transmits the signal as it is, so that the memory bank signal BNO~13N2 is Since the corresponding address signals A16 to A1B are formed, a simple expansion of the physical address space is performed.

On the other hand, when the bank control signal BCI is set to "1", if the handled signal is a program, the program fetch signal PRG is "1", so the gate circuit G3
Since the output signal becomes "1", the memory bank signal νI B N O is set to "[)" as described above, so that the even numbered memory specified by the upper 2 bits of memory bank signals BN1 and BN2 While bank selection is performed, if the signal handled in 7 is a data signal, the data fetch signal DATA is logic "1°", so the AND gate circuit G
Since the output signal of 4 becomes "'", the memory bank signal BN O is set to "1" as described above, so that the odd numbered memory th determined by the upper 2 bits of the memory bank signal BN1 and BN2 Bank selection is performed. That is, the memory banks marked with diagonal lines in FIG.

FIG. 5 shows a concept 1 of the address space of another embodiment. In this embodiment, the bank control (t'i
WBC] is logic "0", indicating the extended function set by the bank control signal BCO.

This bank system filIl trust! , lco is logic "0", the output of the AND gate circuit G5 becomes logic "0" as described above, so two types of extended functions set by the bank control function Bc1 are performed.

On the other hand, if the bank control signal BCO is at logic "1°", the output signal of the AND gate circuit G5 is determined according to the output signal of the address monitor circuit AM. for example,
If it is a logical address space in the common memory area set as above, its output (a is "1" and 42),
Since the memory bank signals BNO to BN2 are all forcibly converted to logic "0", the common address space set in memory bank BAO to 2 to 1F3 is fixed for 1h. Therefore, the address space indicated by diagonal lines extending from memory banks BAI to BΔ7 will not be used.

On the other hand, for a logical address signal that exceeds the common memory area set as described above, the output signal becomes 0'', and the above conversion operation of 1-circuit c'' and 2 is not performed. Therefore, since the memory bank signals BNO-BN2 transmitted to that person are output as they are, the remaining address spaces in each of the memory banks BAO to BA7 are designated.

Of course, this extended function uses the common address space S set above and the remaining address spaces in each memory bank BAO to BA7. In this case, when the bank control signal BC1 is set to "1", the remaining address space of each of the memory banks BAO to BA7 is automatically divided into a program area and a data area.

Therefore, this embodiment has expanded functions corresponding to the combination of four types of common memory area settings and four types of bank control operations.

[Effect J (1) In this embodiment, there is a register (bank control 1) for expanding the physical controller space in the central processing unit.
Since it is equipped with a microphone with an expanded physical address space without the need for a special external circuit,
: I, J-bin L-k system easy 1' second purchase rule)
, -Togatete Z〕 and ・) effect can be obtained.

+2+4- (1) has the effect of simplifying the sostenography of an information processing device such as a microcomputer.

(3) In this embodiment, since the R address for expansion and its control arch are formed using built-in registers, the settings can be made in the FCL grammar6. :
, Therefore - (Yorai's physical address space expansion method, if I may say so, requires the setting of the above-mentioned common address space, which is virtually impossible in the Memo Management 1 function, and the separation of programs and takes. The effect of being able to realize new functions such as this one within the cylinder is positive.

Although the invention made by the present inventor has been specifically explained based on Examples above, this invention is not limited to the Examples described above, and it is understood that various changes can be made without departing from the gist of the invention. Needless to say. For example, the circuit configurations of the arithmetic unit, control unit, and register unit that constitute the central processing unit can take various embodiments.

The setting of the physical address space to be expanded by the register for expanding the physical address space can be modified in various ways.

[Application field]

In the above explanation, we have mainly explained the case where the invention made by the present inventor is applied to a one-chip microprocessor having a 16-bit logical address signal and having an E) hino[ configuration, which is the field of application in which the invention was made. However, the present invention is not limited to this, and can be widely used in a central processing unit (CPU) that processes information according to a program.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a "4-micro processor" showing one embodiment of the present invention. FIG. A block diagram for explaining the physical address space, Figure 4 is a conceptual diagram of the address space for explaining its extended functions, and Figure 5 is a conceptual diagram for the address space for explaining other extended functions. A1., TJ...Arithmetic logic unit, Acc...
・Accumulator, FF...Accumulator, ヂ. R1...temporary register, 1"LG...flag flip-flop, BCD...decimal correction, OPR...instruction register, 0P-DCR...instruction decoder and machine cycle encoder, TC...timing and control circuit, R2i, x
IshiR8: General-purpose working register and temporary register, SP: Sukusokuboin destination PC-niprogram counter, AD: Incrementer/decrementer and address check. SL: Register selection circuit, MPX: Multiplexer, BCR: Bank control register. DCR...decoder circuit, DEC...decode circuit:
AM...address monitor circuit, G], G2...gate circuit, 03-G5...and1. : (-circuit. OB... Output sofa circuit

Claims (1)

[Claims] 1. An address launch forming a logical address signal, and a logical address signal formed by this address launch.
A central processing unit comprising: a bank control register for forming a physical address register for expansion beyond a predetermined address space. 2-, the puncture control register listed in lZ includes an address focus for expansion, a control bit for determining whether or not to separate the program bank and data bank, a control bit for determining whether or not a common memory area is provided, and the above-mentioned common memory area. A circuit that decodes each of the control bits in ``2'' allows a signal obtained by selectively converting the expansion address pinto to be used as an expansion address in the physical address space. The central processing unit according to claim 1r14, wherein the central processing unit is output as a signal. 3. The central processing unit is a microprocessor with an 8-via configuration, the logical address signal consists of 16 bits, the bank control register is an 8-pin register, and of the 8 bits, the address for expansion is 3. The central processing unit according to claim 1, wherein the number of bits is three, and the remaining five bits are used as control bits. 4. The central processing unit according to claim 1, 2 or 3, wherein the central processing unit is configured as a one-chip semiconductor integrated circuit device.