JPS5942331B2 - Prosetsusasouchinoseigiohoshiki - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a control method for a processor device integrally equipped with a direct memory access controller.

In recent years, with the advancement of semiconductor technology in information processing systems, single-chip microprocessor devices (
Processors (hereinafter abbreviated as CPUs) have become widespread.

Along with this, the I/O (input/output) devices that make up computer systems have become diverse, and various types of I/O devices have appeared that operate faster than the processing speed of processors. . If the operating speed of the I/O device is faster than the processor, intervening the processor in data transfer between the main memory and the I/O device will reduce data transfer efficiency, so direct memory access (DI) is generally used.
A method called rectMemoryAccess (hereinafter abbreviated as DMA) is employed to directly transfer data between the main memory and the I/O device without intervening the CPU. In other words, the DMA method aims to reduce the burden on the CPU and improve data transfer efficiency, thereby achieving effective and efficient data processing. FIG. 1a is a block diagram showing the configuration side of a general computer system, in which the CPU
I can directly control access to the main memory 12 by monopolizing the memory data bus (MB), and D
By monopolizing the bus (MB), the MA controller (hereinafter abbreviated as DMAC) 13 directly connects the main memory 12 and the plurality of input/output devices 14. It is designed to allow data transfer. As described above, the DMA transfer method generally provides the DMAC 13 as hardware independent of the processor, thereby making it possible to control data transfer. However, as processors have become increasingly integrated into LSIs, it has become possible to combine the Imada processor itself with a DMAC, use them as common hardware, simplify the device, and combine them into a single LSI. This is as shown in Figure 1b, and the single processor unit 15 has CPU and DMAC functions, which simplifies the system configuration (reduces the number of chips and overall logic) and allows high-speed control. etc. will be achieved. In this case, DMAC operation and C
What is program operation by PU? Processor unit 15
Since the switching is controlled by the internal logic of the unit 15, the delay time (loss time) due to the switching control is
This is an internal logic delay time, and therefore enables more efficient high-speed control than control by an external device.
However, even in this case, simply integrating the hardware may result in an overall reduction in processing performance in the following cases.

That is, if, for example, the combined processor unit enters the DMA operation mode at a certain point, the program operation of the processor itself will stop. SUMMARY OF THE INVENTION An object of the present invention is to provide a control method for a processor device that eliminates the drawbacks of the conventional method and improves overall data processing efficiency.

An embodiment of the present invention will be described below with reference to the drawings. FIG. 2 shows the flow of program execution, where the thick line is the execution process of the program itself, and the thin line is the data transfer process using DMA instructions. Instruction A is a DMA instruction and is generally a block transfer instruction. For example, it is possible to transfer data from address X to address X+N in memory to the I/0 device. This DMA instruction has the following instruction format, for example. Here, the start address is stored in R1, and the stop address is stored in R2.

In other words, the area from address [R1] to [R2] is 1/
The block is transferred to the 0 device. FIG. 3 is an execution flowchart of this instruction. First, instruction A is fetched, and then, by calculating the execution address, the contents of [R,] and [R2] are set to the start address and stop address of the DMA mode, respectively. It is interpreted as Next, the processor executes this instruction A.
However, since all the information necessary to execute instruction A is available, execution of instruction A in the processor can be started. This is initiated by the address of the input/output device previously identified and the start and stop addresses for the memory. On the other hand, while executing instruction A, that is, the processor changes from program mode to DMA mode and
While the transfer control operation is being performed, the memory data bus etc. are shared, so by using this memory data bus etc. in a time-sharing manner, instruction A+1 is fetched at the same time, and the DMA operation is changed from the program operation. It is possible to switch to fetch this instruction A+1, switch from DMA operation to program operation and execute this instruction A+1. After executing the instruction A+1, it similarly operates in a time-division manner and further fetches and executes the instruction A+2. In this way, the processor executes instructions A+1 and A one after another before the end of DMA execution.
+2...... is executed in parallel by fetching it in advance, but for example, fetching up to instruction A+N and executing this instruction A+N
If is again a DMA instruction, then this new MA
The instruction waits just before the execution step.

This control is performed by the PSW (
For example, X
This can be done by using the pit as a DMA execution flag. Here, the lower 3 to 4 bits are C (Carr
y), N (Negative), Z (AllZerO)
, V (0verf10w), etc. The X bit functions as an index section for displaying the DMA execution status as follows. (1) When X-1, DMA is being executed and other DMA instructions are made to wait. (2
) When X-0, DMA execution has finished and a new MA instruction will be executed immediately.

By performing this kind of control, one unit (that is, one
System efficiency is improved because DMA transfer and program execution proceed in parallel in processors (unitized on separate chips), and there is no duplication even if DMA transfer instructions are double fetched.

Generally, when DMA transfers overlap, hardware such as start address and stop address registers, address counters, memory data bus time-sharing controllers, etc. are duplicated and have a very complex configuration. Unfavorable for becoming. In particular, an LSI processor unit cannot incorporate such a DMAC function for multi-channel parallel operation. In addition, the number of lead-out pins for external data buses and the like is limited and must be shared, and unless the control method as in the embodiment described above is used, the efficiency will be reduced due to multiplexing. Therefore, it can be seen that in the above embodiment, by setting the single-channel DMA mode and the program mode in a time-sharing manner so that they coexist, the system efficiency can be surely and easily improved. Note that, as shown in Figure 2, during program execution, the DMA
There is no difference from setting the normal program mode, such as the ability to enter an interrupt routine even during execution. As detailed above, according to the present invention, it is possible to improve the overall data processing efficiency, and the DMA
It is possible to provide a control system for a processor device that is particularly effective in the case of a microprocessor in that it is equipped with a function to proceed with a DMA operation in parallel with a program operation.

[Brief explanation of the drawing]

1A and 1B show an example of a microcomputer system, FIG.
FIG. 3 is a flowchart showing an embodiment of the present invention;
FIG. 4 is a diagram showing the format of the PSW in the same embodiment.

Claims (1)

[Claims] 1. In a processor device having a direct memory access control function, a direct memory access operation is enabled in a time-sharing manner during program execution, and a specific bit of the program status word of the processor is used as an indicator for direct memory access execution. Control of a processor device, characterized in that when the processor reads a direct memory access execution instruction again during execution, the instruction is made to wait until the direct memory access operation currently being executed is completed as indicated by the indicator section. method.