JPS5912646A - Error correcting decoder - Google Patents

Abstract

PURPOSE:To improve the correcting ability of a titled recorder, by allocating a zero digital code to a symbol not transmitted, in an error correcting decoder performing a soft decision. CONSTITUTION:A receiving signal from input terminals 100', 101' is compared with a threshold value by comparators 51-54, and 55-58 of a soft decision circuit 60 and used as an address of memories 61, 62. An output of the circuit 60 is calculated for the correlation with each transmission pattern by adders 30'-33'. The output of the adders 30'-33' is inputted to a processor 40' and a discriminating output is obtained from a terminal 102' based on the Viterbi algorithm. Since the 0 of the discrimination output is a so-called zero digital code, the zero digital code is assigned to a symbol not transmitted actually.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an error correction decoder, and particularly to an error correction decoder that improves correction capability by performing multilevel soft decisions on received signals.

Conventionally, in the output of the soft decision circuit of such an error correction decoder, there is no value that represents the median value of the transmitted signal points, and even in cases where it is completely unknown which signal point was sent, This method has the disadvantage that the error rate increases because it outputs a value close to .

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the drawbacks of the conventional error correction decoder described above and to provide a more flexible error correction decoder.

According to the present invention, a received signal is input to an error correction decoder that performs a multi-level soft decision on the received signal and reduces the error rate after decoding by realizing decoding based on the soft decision. a soft decision circuit which outputs a digital code, and has a zero digital code in the output code representing the central value of the transmitted signal point, and the output of the soft decision circuit; and an error correction decoder that decodes information regarding which of the transmitted signal points is not present when the zero digital code is input, and a received signal. In an error correction decoder, the error correction decoder reduces the error rate after decoding by performing multilevel soft decisions and decoding based on the soft decisions. a decision circuit, a conversion path for converting the output of the soft decision circuit into a zero digital code representing the central value of the transmitted signal point based on No. 46 from the control terminal; When the output is input and the zero digital code is input, t is related to which point among the transmission signal points was sent.
It is possible to provide an error correction decoder comprising a decoding circuit that decodes the # information as if it does not exist.

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a conventional error correction decoder. The example shown in FIG. 1 is a Viterbi decoder using soft decision for a convolutional code with a coding rate of 1/2. A convolutional code encoder with a coding rate of 1/2 outputs 2 bits for 1 bit of information. Each of these values is converted into a binary value of ±1 and transmitted, passes through a transmission path, and is received with noise added thereto.

Input terminals 100 and 101 each receive an analog value with noise added to a value of ±1. These analog values are converted into digital codes by converters 10 and 11. The relationship between the input and output of the converter 10.11 is, for example, as shown in Figure 2 (1) and (21). In Figure 2, the converter converts a 3-bit normal binary code. The output is expressed as a decimal number.The Viterbi decoder calculates the correlation between this received signal and the transmitted Isa pattern and decodes it using the Viterbi algorithm.The transmitted pattern is (1°1), ( 1,-1), (-1,1), (-1,
-1), so all you have to do is calculate the correlation with each one. The correlation between the received signal and $ 1 // is obtained by using the air quality converter output as is, and the correlation with '-1'' is obtained by inverting the % converter output for each bit.

Therefore, by the inverting circuit 20, 2], 22.23, '-1
By adding the output of the converter 10.11 and the adders 30, 31, and 32.33, respectively,
,IL (1,-1), (-1,1), (-1,
-1) It is possible to find the correlation with the 4th letter 9 nokutan. The adder 30 has a correlation with (1°1), and the adder 31 has a correlation with (1°1).
1, -1), the adder 32 calculates the correlation with (-1, 1), and the adder 33 calculates the correlation with (-1, -1). In FIG. 1, diagonal lines on the connections mean that a plurality of connections exist in parallel, and the inverting circuits 20, 21, 22, .
23H means that each bit is inverted.

The outputs of adder circuits 30.31, 32.33 are from O to 141
It will take one of the values in .

Normally, the correlation value between a positive value and a negative value is negative, but in the Viterbi decoder, decoding is performed based on information about which one has a relatively larger correlation, so it is different from normal correlation. As long as the magnitude relationship does not change, the absolute value of the correlation does not matter. Therefore, as in the example shown in FIG. 2 (1), the output of the t-transformer is intentionally expressed as only positive values without taking negative values.

The four correlation values obtained by the adders 30, 31, 32, and 33 are processed by a process that executes the Viterbi algorithm.
The signal is input to the terminal 102, Viterbi decoded, and output from the terminal 102.

FIG. 3 is a block diagram showing one embodiment of the present invention. The embodiment shown in FIG. 3 is also a decoder using the Viterbi algorithm for convolutional codes with a code rate ↓, as in FIG. 1.

The received signals inputted from the input terminals 100', 101' are sent to the comparators 51, 52, 53, 54, '55, 56, 57 .
It is compared with a preset threshold value at 58. The threshold values of the comparators 51 and 55 are shown in a of Fig. 2 (2), respectively, and the threshold values of the comparators 52 and 560 are shown in Fig. 2 (2), respectively.
2, the thresholds of comparators 53 and 57 are set to C in FIG. 2(2), and the thresholds of comparators 54 and 58 are set to dK in FIG. 2(2). Comparator 5], 52
The output of ゜53.54 is 11-de only memo 1ba II
M)1(0) is used as the address of M61, and the outputs of comparators 55.56 and 57.58 are used as the address of kLOM62.

The output of the ROMs 61 and 62 is a digital code as shown in the output column of FIG. 2 (2). In the present invention, two's complement is used to include the zero digital code in the output. In FIG. 2 (2), this digital code is expressed as a decimal number rLA. When the received signal takes a value between the threshold value and C, the output from the ROMs 61 and 62 becomes 10'', which is a zero digital code.

This comparator 51. 52. 53. 54. 55,5
657.58 and ROM 61.62 together constitute a soft decision circuit 60.

The soft decision circuit 6o is output in the same way as in the embodiment shown in FIG. However, the adder 32' calculates the correlation with the bang (-1, 1), and the adder 33' calculates the correlation with the bang (-1, -1). The correlation with '-1'' is determined by the inverting circuits 20', 21',
It is obtained by inverting the output of the soft decision (b) path at 22' and 23'. However, the inverting circuit in this case is not a bit-by-bit inverter, but a circuit that inverts the sign of the output of the soft decision/circuits 60 and 61. For example, if the output of the soft decision circuit is expressed in two's complement, bit by bit inversion is performed and '1' is added.

The outputs of the adders 30', 31', 32', and 33' are input to the processor 4()', and a determined output is obtained from the terminal 102' based on the Viterbi algorithm. Inverting circuit 20'.

21', 22', 23' and adders 30', 31'
, 32'.

33' constitutes a decoding circuit 70 together with the haprocessor 40'. When performing normal decoding, the error correction post-coder of the present invention has a correction capability that is not much different from that of conventional error correction decoders, but it can be , when decoding a code that has passed through a transmission path where impulsive noise is present, it is possible to obtain a larger correction ability than the conventional method.

FIG. 4 is a block diagram showing the configuration of a punctured code encoder and decoder. The output of the convolutional encoder 210 with a coding rate of 1/2 is decimated by a decimation circuit and then transmitted. The decimation circuit 220 stores the output of the convolutional encoder 210 in a buffer, decimates it based on a predetermined erasure map, and transmits it.

For example, if the erasure map is (1, 1, 1, O), 4 bits output from the convolutional encoder for 2 clocks are stored in a buffer and only 3 bits are transmitted from the beginning.

By doing this, the coding rate increases from 1/2 to false.

Noise is added to the transmitted signal on the transmission path before it is received. On the receiving side, every time three symbols are received in the insertion circuit 230, dummy data that was not actually transmitted is added and inputted to the decoder 240. At this time, although the fourth symbol was not actually transmitted, it is decoded as if it had been transmitted. At that time 4
It is preferable to decode the symbol by regarding it as a value in the middle between +1 and -1. However, conventional soft decision circuits with thresholds as shown in Figure 2 (1) do not have a so-called zero digital code as an output, so the input will output a value close to zero, that is, 3 or 4. Become. Since this value r is close to either +1 or -1, there is a strong possibility that an error 9 will occur during decoding.

On the other hand, in the decoder of the present invention, 10" of 1 judgment output
Since this is a so-called zero digital code, this zero digital code can be assigned to a symbol that was not actually transmitted.

FIG. 5 is a block diagram when the error correction decoder of the present invention is applied to a punctured code.

Analog signals received from input terminals 300 and 301 are input. Also, erasure map information is input from input terminals 302 and 303. This eraser knob information is ' 0
For the symbol ``, connect the switches 310 and 311 to the ground side and use zero port as the input signal.

In this way, the error correction decoder 320 side-twists the cello digital code for signals that were not actually sent, making it possible to realize decoding with fewer #9s. Like detection by a J frequency discriminator in FM modulation, input information from terminals 302 and 303 as to whether or not impulsive noise appears on the transmission line where impulsive noise appears, and detect innocuous noise. When there is noise, the influence of innocuous noise can be reduced by inputting zero volts to the error correction decoder.

FIG. 6 is a block diagram showing another embodiment of the present invention. In Fig. 6, input terminal 1 (10″, 1 f)]
An analog signal is input from σ.The analog signal is input to the soft decision circuit 6 (B). The control signal is input from the extra terminals 110 and 111.This control signal 1.-1 is the control signal input from the terminals 302 and 303 in the example of the m5 diagram. The conversion circuit 90 performs an AND operation between the control signals from the iL terminals 110 and 111 and the soft decision results of the inputs 1oO'' and 101'' from the soft decision circuit 60'. Calculate 1ri with AND gate 91.92 and get -CI/-1.

By doing this, the control 4.5 gin is % (1// throat %
+-, 1 code where all bits are 10", i.e. -
1! The digital code is disconnected and the control signal is
1'', the soft decision result is sent to the decoding circuit 70'.The decoding circuit 70' also has the same configuration as the decoding circuit 70 of the embodiment shown in FIG. 3.The decoding result is output. It is output from the terminal 102''. The post-encoder C in FIG. 6 has the same function as the decoder in FIG.

Therefore, in the embodiment shown in FIG. 6, strong decoding can be realized for punctured codes, impulsive noise of FM thread, or fading. Note that in the embodiment 1° of FIG. 6, the output of the soft decision circuit 60' already has a zero digital code, but if the configuration shown in FIG. It is sufficient that a zero digital code exists at the output of the circuit, and it is also possible to use a conventional soft decision circuit as is.

As described above, according to the present invention, it is possible to provide an error correction decoder that can reduce the influence when the received symbols are completely unreliable.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing a conventional Viterbi decoder 1, Fig. 2 is a diagram explaining the input/output relationship of the soft decision circuit, and Fig. 3 shows a 1μ embodiment of the present invention. In the block diagram, reference numeral 60 represents a soft decision circuit, and reference numeral 70 represents a decoding circuit. FIG. 4 is a block diagram for transmitting and receiving a punctured code, FIG. 5V is a block diagram showing an example of applying the error correction decoder of the present invention to a punctured code, and FIG. It is a block diagram showing an example. In the figure, reference numeral 60' is a software decision circuit, reference numeral 90 is a conversion circuit, and numeral 77 ()' is the first
Figure-I O+I Gi 2 Figure-haya 3 Figure-I 4th

Claims (1)

[Claims] (1) An error correction decoder that inputs a received signal, performs a multilevel soft decision, and reduces the error rate after decoding by realizing decoding based on the soft decision,
A soft decisicon circuit that inputs the received signal and outputs a digital code with a zero digital code in the output code that represents the central value of the transmitted signal point, and inputs the output of the soft decision circuit. and a decoding circuit that decodes information regarding which of the transmitted signal points is not present when the zero digital code is input. decoder. 2. Input the received signal and perform multi-level soft decision I
A1 In an error correction decoder that reduces the error rate after decoding by realizing decoding based on the soft decision, the soft decision circuit that inputs the received signal and outputs the digital code, and the signal from the control terminal. a conversion circuit that converts the output of the soft decision circuit into a cello digital code representing the central value of the transmitted signal point,
a decoding circuit which inputs the output of the conversion circuit and decodes it assuming that there is no information regarding which of the transmission signal points was sent when the zero digital code is input; An error correction decoder comprising: