JPS59124099A - Fault repair processing system of common storage area - Google Patents

Abstract

PURPOSE:To facilitate processing in a fixed fault by dividing a data receiving and passing area into a main and an auxiliary area and indicating which area is used, and allowing hardware to access the indicated area automatically. CONSTITUTION:If a fixed fault occurs to the data receiving and passing area CiA, a CPU program transfers necessary data based upon an instruction to the auxiliary CiA and sends out a switching signal indicating the switching of the CiA to send execute I/O signal (XiO signal) to turn on. When a CHP receives the signal XiO, a switching signal for switching the CiA is sent out in case of a fault and the instruction is interrupted as instruction processing damage. If the CPU detects a fault when receiving an accept signal, instruction processing damage processing is performed and the switching signal is sent out. Consequently, the subsequent actuation is performed by using the CiA having no fault.

Description

Detailed Description of the Invention [Technical Field of the Invention] The present invention relates to a system configured such that a plurality of processing devices (or a plurality of processing units in one device) communicate with each other via a commonly accessible storage means. The present invention relates to a recovery method when a failure occurs in the common storage means in a data processing system.

[Prior art to the invention]

With the increase in the capacity of main storage devices, the use of firmware in hardware has become popular, and firmware has come to use part of the main storage device as a hardware area.

Generally, an ECC circuit is added to the main memory,
Countermeasures have been taken for 1-bit failures, but when it comes to 2-bit failures or fixed failures, even if an error is detected, only that error is dealt with, and almost no measures are taken for recovery.

This is because countermeasures are taken on the assumption that double failures occur extremely rarely.

However, if a fixed failure occurs in the transfer area for important data such as communication between microprograms, all subsequent processing will be disrupted, leading to a system down.

[Purpose of the invention]

The purpose of the present invention is to solve the above-mentioned problems.
The interface area (referred to as the interface area) is divided into a main area and a spare area, and the device or microprogram that detects a 1 error instructs the other device or microprogram which CIA to use. , the hardware automatically accesses the CIA of the instructed side so that the instructed side always accesses the main CIA without being aware of the instructions. -to! , is something.

[Embodiments of the invention]

Here, a case where the CIA is provided on the main memory will be explained.

The contents of the CIA include activation of the I10 device or
0 Information required for interrupt 1 For example, instruction code, channel number, device number, CAW (channel address)
word), condition code, or CSW
<Channel Status Word) (see Figure 2).

FIG. 1 is a block diagram showing an embodiment of the present invention, in which a microprogram-controlled CPU and a microprogram-controlled CHP (channel processor) communicate using a predetermined area of the main memory MS as a CIA. shows.

Hereinafter, the recovery processing method according to the present invention will be explained according to the timing at which a failure occurs.

fl) When the CPU microprogram recognizes the I10 instruction, etc., it sends the necessary data to C and IA,
Turns on the XIO signal (excue I10 signal) to the CHP and transmits a startup request.

If a fixed failure occurs in the CIA during this time, the necessary data will be transferred to the backup CIA and a signal indicating that the CIA has been switched (
(hereinafter referred to as a switching signal) is sent out, and the XIO signal is turned on again. In other words, the command is retried and the command is not interrupted.

(2) When the CHP receives the XIO signal, it reads the CIA, analyzes the instruction code, performs the necessary processing, writes the condition code, etc. to the CIA, turns on the ACPT signal (accept signal), and sends it to the CPU. Notify the end of processing.

If a fixed failure occurs in the CIA during this time, the processing in the CHP at this time is interrupted by channel control error processing or external damage processing. The CPU microprogram can also detect this fixed fault as a machine check, send a switching signal to switch the CIA, and interrupt the instruction as an instruction processing damage.

(If 31C-PU normally receives the ACPT signal.

Extract the condition code etc. from the CIA,
It performs processing such as loading the PSW and storing C3W at a specified address, drops the XI○ signal, confirms that the ACPT signal drops, and transfers control to the next instruction.

If a fixed fault is detected at this point, instruction processing and damage processing are performed and a switching signal is sent.

As a result, the second startup can be performed using a CIA that does not have fixed failures.

Since C1λ is placed near the maximum address of the main memory, if the capacity of the main memory changes, the address at which it is placed also changes accordingly. For this reason, CHP is used at the time of initialization when the system is powered on.

The SVP (service processor) may notify the maximum address of the main storage device and automatically calculate the CIA address, or the SVP (service processor) may notify the CIA address directly.

Furthermore, the main memory is subject to patrol by the CPU, read/written within a certain period of time, and recovery from temporary failures is performed closely.

〔Effect of the invention〕

As described above, according to the present invention, the microprogram control unit only needs to perform processing with only one CIA in mind.
, CIA switching is controlled by hardware, which simplifies processing.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention. MS is the main memory, CPU is the central processing unit, CHP is the channel processing unit, AR is the address register, DR is the data register, MSA is the main memory address register, and CIA is the common storage area. EF is a flag indicating a fixed failure. FIG. 2 is a diagram showing an example of the contents of the CIA. Figure 7 Figure 2

Claims (1)

[Claims] A plurality of microprogram-controlled processing devices. In a data processing system that communicates with each other via a common storage area that can be accessed in common, a plurality of the common storage areas are provided, and the microprogram control unit of each processing unit uses a single address as the address of the common storage area. , wherein each processing device is provided with means for detecting a failure in the common storage area, and hardware means for changing the address with respect to other processing devices when a failure is detected. Processing method.