JPS59114639A - Ready signal generating circuit of high speed operating element - Google Patents

Abstract

PURPOSE:To operate normally a high speed operating element by a simple circuit by obtaining a READY signal of the high speed operating element by AND of a one-shot multivibrator output triggered by a chip select signal, and a wait signal. CONSTITUTION:A READY signal generating circuit 14 is constituted of one one- shot multivibrator and one AND gate 16. The one-shot multivibrator 15 is triggered by a leading edge of a chip select signal CS of a high speed operating element 12, outputs a pulse having a fixed width determined by an external resistance R1 and a capacitor C1, and it appears in a terminal Q. The AND gate 16 gains logical OR of a Q output signal of the one-shot multivibrator 15, and a wait signal (pause) generated by the high speed operating element 12, and its output becomes a READY signal to a CPU11.

Description

DETAILED DESCRIPTION OF THE INVENTION The invention of this application relates to a READY signal generation circuit for a high-speed arithmetic element in a computer system. When using an AM95]]) connected, in order to ensure that operations such as reading/writing the internal registers of the high-speed arithmetic element can be performed normally, it is necessary to
In order to keep the CPU in a wait state, the high-speed arithmetic element issues a pause signal to the CPU, but as the processing speed of the CPU increases, the timing of the pause signal issued to the CPU is such that the CPU waits The detection timing is delayed, the wait signal ITi is not received by the CPU, the CPU does not enter a wait state, and the processing proceeds before the operation of the high-speed arithmetic element is completed, so that the high-speed arithmetic element can operate normally. I can't do it anymore.

In order to cope with this problem, conventional means as shown in FIGS. 1 and 2 have been proposed. In both figures, 1 is CP
U and 2 are high-speed arithmetic elements, 3 is a chip select circuit, 4 is a READY signal generation circuit, ALE is an address launch enable signal, CLK is a clock signal, AB is an address bus, DB is a data bus, RD is a read signal, and WT is a read signal. Write signal, C8 is chip select signal, pause is high-speed arithmetic element wait signal, 4-1 is ALE signal detection/
Holding circuit, 4-2 is a logic circuit, Dl, D2 are flip 70 tubes forming the detection/holding circuit 4-s, G1-G4
is a gate forming the logic circuit 4-2.

READY of high-speed arithmetic elements in such systems
The operation of the signal generating circuit 4 is performed as shown in the time chart of FIG. When 0PUI attempts to perform a read or write operation on the high-speed arithmetic element 2, the address latch enable signal ALE is output in a clock period T1 before the read signal RD or the write signal WT is sent. Due to this ALE signal, the output Q of the flip-flop D□ of the detection/holding circuit 4-1 becomes H level. After half a period, the clock signal CLK
Due to the rising edge of , flip-flop D2 outputs Q2.
is set to H level, and the flip-flop Dl is cleared by the output Q2 set to L level. On the other hand, the READY signal output from the logic circuit 4-2 changes to L level when the conditions that C8 is L level and C2 is H level are met. Next, in the clock period T2, the read signal section goes to L.
In response to this, the high-speed arithmetic element 2 changes the wait signal pause to the L level after a time tRP, but before entering the clock period T2, the READY signal has already become the L level and the CPU is the wait signal p of high-speed arithmetic element 2
Enters wait state without waiting for ause. Furthermore, the output Q2 of the flip-flop D2 is turned to L level by the rising edge of the clock signal CLK during the clock period T2. However, at this point, the wait signal PAUSE from the high-speed arithmetic element 2 is at the L level, and this wait signal p
ause will be transferred directly to the CPU. Then, after several cycles, when the high-speed arithmetic element 2 completes the processing,
The wait signal pause becomes H level, and the wait state of 0PtJ is released from the immediately following clock period.

As described above, in the above configuration, a separate wait signal (RE
ADY signal) is sent to the CPU to enable normal operation of the high-speed arithmetic element.

However, the READY signal generation circuit of a high-speed arithmetic element with such a configuration is limited to a CP with no address latch enable signal.
It cannot be used in the U, requires a clock signal from the CPU, and has a large number of parts.

The present invention was made in order to eliminate such drawbacks of the conventional READY signal generation circuit of a high-speed arithmetic element.
RE of a general-purpose high-speed arithmetic element with a simple configuration that can normally access the high-speed arithmetic element regardless of the clock speed of the CPU and without using a specific signal of a specific CPU.
The purpose of this invention is to provide an ADY signal generation circuit.

The present invention will be explained below based on Examples.

FIG. 4 is a block diagram of a converter system to which a READY signal generation circuit of a high-speed arithmetic element according to the present invention is applied. In FIG. 4, ]1 is a CPU, ]2 is a high-speed arithmetic element, ]3 is a chip select circuit of the high-speed arithmetic element 12, and 14 is an RE that requests a wait for 0PUII.
ADY signal generation circuit, AB is an address bus, DB is a data bus, RD is a read signal, Z is a write signal, inside is a chip select signal of the high-speed arithmetic element 12, pause is a wait signal generated by the high-speed arithmetic element 120, READY is 0
PUII is a terminal that detects whether there is a wait request.

The READY signal generation circuit 14, as shown in FIG.
It is composed of one one-shot multivibrator 15 and one AND gate 16. The one-shot multipipe rake 15 is triggered by the leading edge of the chip select signal C8 of the high-speed arithmetic element [2], outputs a pulse with a constant width determined by an external resistor R1 and a capacitor C1, and outputs a pulse with a constant width determined by an external resistor R1 and a capacitor C1. It will be done. A
The ND gate 16 performs a logical OR operation between the Q output signal of the one-shot multipipe rake 15 and the wait signal pause generated by the high-speed arithmetic element 2, and sets the output to 0.
It is used as a READY signal for PUII.

Next, the operation will be explained with reference to the time chart shown in FIG.

When the OPU 11 executes a read or write operation to the high-speed arithmetic element 12, first, the CPU
II outputs an address signal to address bus AB. The chip select circuit 13 inputs this address signal,
A chip select signal O8 for the high-speed arithmetic element 12 is formed. One-shot multi-bye break] 5 is triggered by the leading edge of the chip select signal O8, outputs a constant width pulse to the Q output, sets the READY signal to L level, and requests the CPU 11 to wait.

At this time, in order for 0PUII to enter the wait state,
The FLEADY terminal of CPUII must satisfy the timing specified by 0PUII and become L level. In other words, the propagation delay time of the chip select circuit 13, one-shot multivibrator 15, and AND gate 16 is from READY to 0PUII outputting the address signal.
The time in the trench to detect the terminal must be shorter. For example, in Intel's 8085 CPU (5 MHz clock), the detection time is at most 100 ns, so the configuration may be such that the propagation delay time is kept to 0 Ons at worst. is quite possible.

0PUII follows the address signal and the read signal RD or write signal 5 t , x before entering the wait state.
' I % + ' The arithmetic element 12 calculates the time (maximum 15
0ns), the wait signal pause is set to L level.

At this point, the READY terminal of 0PUII is already at the L level due to the Q output of the one-shot multivibrator 15, and 0PUII can enter the wait state without waiting for the pause signal of the high-speed arithmetic element 12. . The Q output of the one-shot multivibrator 15 is connected to the external resistor R1 and capacitor C1.
After the time determined by , it becomes H level, but at this point, the wait signal I5 from the high-speed arithmetic element 12 becomes L level, and this wait signal pause is directly connected to the READY terminal of 0PUII. That will happen.

Then, if this wait signal pause becomes H level,
The READY signal also goes to H level, and 0PUII is released from the wait state.

As described above in detail based on the embodiments, the present invention provides a one-shot multi-by-break triggered by a chip select signal in a READY signal generation circuit of a high-speed arithmetic element that requests a wait state to the CPU.
A that inputs the output of the multi-novel ibrator and a wait signal generated from the high-speed arithmetic element, and outputs a READY signal.
Since it is configured with an ND gate, it generates a READY signal requesting a wait state to the CPU before the high-speed arithmetic element outputs a wait signal, allowing the high-speed arithmetic element to operate normally. The READY signal generation circuit can be configured with a simple circuit with a small number of parts without requiring specific signals such as a CPU clock signal or an ALE signal.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a system using a conventional READY signal generation circuit, FIG. 2 is a conventional READY signal generation circuit, FIG. 3 is a time chart showing its operation, and FIG. 4 is a block diagram of a system using a conventional READY signal generation circuit. Block configuration diagram of a computer system to which the READY signal generation circuit according to the invention is applied, No. 5
The figure shows an embodiment of the READY signal generating circuit according to the present invention, and FIG. 6 is a time chart illustrating its operation. In the figure, ]1 is a CPU, 12 is a high-speed arithmetic element, and 13 is a high-speed calculation element.
is a chip select circuit, ]4 is a READY signal generation circuit, 15 is an oscillator, ]6 is A
ND gate is shown. Patent Applicant: Olympus Optical Industry Co., Ltd. Figure 1 Figure 2 Figure 3 Procedural Amendment February 1981 Commissioner of the Patent Office Mr. Kazuo Wakasugi 1 Indication of the Case 1988 Patent Application No. 224037 2 Invention Name: READY signal generation circuit for high-speed arithmetic element 3; Relationship with the case of the person making the amendment: Patent applicant: 6; Number of inventions to be increased due to the amendment: None; 7; Subject of amendment: Drawing 8; Contents of the amendment:

Claims (1)

[Claims] In a computer system comprising a CPU, a high-speed arithmetic element, and a chip select circuit for the high-speed arithmetic element, and configured to control the CPU and drive the high-speed arithmetic element, the computer system is triggered by a chip select signal of the chip select circuit. It is characterized by comprising a one-shot multivibrator, and an AND gate that inputs the output of the one-shot multivibrator and a wait signal generated from the high-speed arithmetic element, and outputs a READY signal requesting a wait state to the CPU. A READY signal generation circuit for a high-speed arithmetic element in a computer system.