JPS5911222B2 - Multi-frame synchronization method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a multiframe synchronization method in a time division multiplex transmission communication system.

In a time division multiplex communication system, in order to separate information spanning a plurality of multiframes, it is necessary to identify the boundaries of the multiframes, that is, to synchronize the multiframes.

Conventionally, to achieve this, there is a method in which a part or all bits of a specific channel of a specific frame are used as a multi-frame synchronization pulse.

In order to maintain stable communication in this system, it is desirable that multiframe synchronization is difficult to break down and that resynchronization is performed quickly when synchronization breaks down. for that purpose,
It is effective to increase the number of multiframe synchronization pulses in one multiframe. However, this method is undesirable because it causes a reduction in the effective capacity of the transmission line.

In addition, for example, P
In the CM-24B system, one multiframe consists of 12 frames, and due to its structure, for example, synchronization is performed every 5 frames or 7 frames, which have no relation to the integer ratio of 10.
Alternatively, it is difficult to implement a method of defining and synchronizing multiple frames larger than 12 frames.

On the other hand, when transmitting various control signals 15 separately from audio signals, some kind of error detection code is often added to ensure transmission quality.

An object of the present invention is to provide a multiframe synchronization method that does not reduce the effective capacity of the transmission path regardless of the multiframe configuration in a time division multiplex communication system that transmits messages with such error detection codes added. It is about providing.

In order to achieve the above object, the multi-frame synchronization method according to the present invention provides a time division multiplex communication system that periodically transmits a series of messages over multiple frames that are a fixed integer multiple of the basic frame. The data of both the error detection codes added to the message are transmitted in one multiframe, and after frame synchronization is established on the receiving side, the multiframe break is identified using the error judgment result of the received message. . According to the above configuration, a multi-frame synchronization method that does not reduce the effective capacity of the transmission path becomes possible, and the object of the present invention can be completely achieved35.

The principles and embodiments of the system of the present invention will be described below with reference to the drawings.

, η− FIG. 1 is a diagram explaining the principle of the system of the present invention.

In the figure, the PCM-24B system, which is currently commercially available in Japan as a time division multiplex transmission system, is taken as an example, and a case is assumed in which a certain channel, for example, the 24th channel, is dedicated for transmitting data messages. Furthermore, here, we will take as an example the case where the data message has a fixed length format consisting of 24 bits in the message part C and 16 bits in the error detection code part FCS, a total of 40 bits.
Therefore, in this example, since each message can transmit 8 bits per PCM frame, it is transmitted every 5 PCM frames. As a result, it becomes necessary to define a multi-frame with a cycle of 5 PCM frames to transmit this message, and to identify the boundaries of this cycle on the receiving side, that is, to take a multi-frame of 5 Pa1v1 frames. However, as is well known to those skilled in the art, the multi-frame structure of the PCM-24 system has a cycle of 12 PCM frames, and the above-mentioned 5 PC
It is not compatible with multi-frame of M frame. For this reason, PCM-24B is used for message transmission as described above.
Multiframes that are independent of the system-specific multiframes must be defined and multiframe synchronization must be achieved.
For the above reasons, in this example, as shown in FIG. 1a, data message C is transmitted using Fl, F2, and F3,
The error detection code FCS is transmitted at subsequent F4 and F5. A data message in this format and an error detection code are as shown in FIG. 1c in a multi-frame synchronization state. In addition, in the case of a multi-frame asynchronous state, the state is as shown in FIG. 1b or FIG. 1d.

The principle of the present invention is that once the state shown in FIG.
The synchronization timing is shifted frame by frame. 3. FIG. 2 is a diagram showing an embodiment of a device constructed according to the method of the present invention described above, in which the present invention is applied to a time division multiplex transmission line connected to a switch frame of a time division exchange.

In FIG. 2, H8 is a four-line receive time division multiplex transmission line, which is a digital interface DT having a clock recovery circuit, a code recovery circuit, and a frame synchronization monitoring circuit.
Connected to I.

Since the details of this digital interface are well known to those skilled in the art, their explanation will be omitted here.

The information pulse train reproduced by the digital interface is sent to the time division exchange switch frame TD-SWF and the control signal separation circuit CSEP via the signal line S1. The extracted clock pulse is also input to the control signal separation circuit CSEP via the signal line S7. This control signal separation circuit CSEP extracts the 24-bit data message inserted between the audio signals and the 16-bit error detection code added thereto. The signal formats of this data message and error detection code are as explained in FIG. Control signal separation circuit CSEP
The separated data message and error detection code are sequentially sent to a 40-bit shift register SR via a signal line S2.

After sending out 40 bits, the contents of the shift register SR are changed to the gates Gl, G2, . . .
4O and is transferred to the error detection circuit FDE.

The output of the error detection circuit FDE is input to the communication control processor CCP via the signal line S3. If it is determined that there is no error, the data message excluding the error detection code is sent to the control information processor CTP via the signal line S4. On the other hand, if it is determined that there is an error, the data message is discarded. Furthermore, if the determination that there is an error continues, it is determined that a multi-frame asynchronous state exists, and a signal that delays the shift register transfer pulse by one frame is transmitted from the communication control processor to the control signal separation circuit CSEP via the signal line S5. Next, we will discuss the case where data is transmitted in the format shown in FIG. 1 and frame synchronization is established on the receiving side.

At time T1, the contents of the shift register are detected by the error detection circuit FDE.
If it is determined that there is no transmission path disturbance and no transmission error, it is determined that the frame is in a multiframe synchronization state.

Next, at time T2, the contents of the shift register are transferred to the error detection circuit F.
If the data message C1 is transferred to the DE, it is determined that the data message C1 is new information and contains an error.

Thereafter, error detection continues with this multi-frame phase, and a notification from the communication control processor CCP is sent to the control signal separation circuit CSEP for the first time after a certain period of time has elapsed to distinguish it from transmission path disturbance. The control signal separation circuit CSEP, which has received the notification, delays the transfer timing pulse of the shift register by one frame time to achieve multi-frame synchronization, as shown in FIG. 2c.

The above is a description of an embodiment of a device configured according to the method of the present invention, but the method of the present invention can be applied even if the arrangement method of data messages and error detection codes is different from that of this embodiment.

Furthermore, the present invention can be similarly applied to other time division multiplex communication systems, such as the CEPT system.

As explained above, the method of the present invention uses the error determination result of the error detection code added to the data message to identify multiframe synchronization, thereby achieving a multiframe synchronization method that does not reduce the effective capacity of the transmission path. realizable.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a multiplexed signal format in which a data message and an error detection code are inserted, and FIG. 2 is a block diagram showing an embodiment of a device configured according to the method of the present invention, showing the mutual relationship of various devices. It is something. DTI・・・Digital interface, H8
・・・・・・Reception time division multiplex transmission line, TD-SWF・
・・・・・・Time division exchange switch frame, CSEP・
...Control signal separation circuit, SR...Shift register, FDE...Error detection circuit, CCP...
...Communication control processor, CTP...Control information processor, Gl, G2...G
4O...Gate circuit, C, Cl...Data message, FCS...Error detection code, F...
...Frame, CH...Channel.

Claims (1)

[Claims] 1 In a time division multiplex communication system that periodically transmits a series of messages over multiple frames that are a fixed integer multiple of the basic frame, data for both the transmitted message and the error detection code added to the message are stored in one multiframe. After transmission is completed and frame synchronization is established on the receiving side,
A multi-frame synchronization method characterized by identifying a multi-frame delimiter using error determination results of received messages.