JPS5868366A - Picture recording device - Google Patents

Abstract

PURPOSE:To realize diverse picture recording by recording standard-density information while its one bit corresponds to two bits of a recording head having fine density. CONSTITUTION:A recording head is constituted with a thermal chip adhered to a substrate and on one flank of the chip, a heating body consisting of 32 resistors is provided. When information with standard density is sent from an opposite station, a clock signal with a period twice as long as a shift clock HCL outputted from an AND gate 125 has is supplied to shift registers 61 and 64 through an OR gate 109 from an AND gate 111. Thus, one bit of the standard- density recording information corresponds to two bits of the recording head with fine density during recording.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to the control of an effective image recording device such as a recording device of a facsimile machine.

For example, the sub-scanning density (standard linear density in the vertical direction) of a facsimile machine is determined to be 385 dots/WII11 and 7.7 dots/m; , a general 7-axis 1) device (or one of them with a fixed sub-scanning density (usually 3.85 dots/m).

Therefore, the recording density of conventional devices is limited,
The conventional device (3.85 dots/rrtn) had the disadvantage that it could not transmit documents with high precision.

The present invention solves these problems and provides an image recording apparatus that can record at any density.

That is, according to the apparatus of the present invention, as this recording system, recording elements (approximately 0.13 m/dot) corresponding to the sub-scanning density of 7.7 dots/llll11 are arranged in the vertical direction,
We have created a recording device that can perform recording with this precision (7.7 dots/scale) and coarse density recording (sub-scanning density (385 dots/tone)) in which 2 dots of the recording element are recorded as one block. It is something.

A facsimile machine equipped with an image recording device of the present invention will be described below.

FIG. 1 is a block diagram showing an extracted image recording section of a facsimile machine.

In FIG. 1, reference numeral 1 denotes a line control device called NCU, which controls connection of a public line to a modem 2. The modem 2 converts the analog information transmitted from the other station into digital information and supplies it to the image processing device 3.

The image processing device 3 performs processing according to the procedure determined by the CCITT recommendations. In addition, the processing device 3 determines whether the image information transmitted from the other station has precision (hereinafter referred to as fine information) or coarse density (hereinafter referred to as standard information). The determination is made based on the control information or the operation switch of the receiving station, and the flag 8 is controlled.

In this case, if it is fine information, flag 8 to [F]
If it is a small output or standard information, it will be output.

4 is a memory for storing the transmitted image information;
It has a capacity that can store two blocks of information for six lines.

5 is a recording control circuit which outputs 32 bits of image information in the vertical direction to the recording device 7 according to a synchronization signal from the clock generation circuit 6.
Output to Heserial. The details of the recording control circuit 5 are specifically shown in FIG.

The clock generation circuit 6 supplies a plurality of synchronization signals to the image processing device 8 and line memory 4 described above.

To explain a little about the processing operation of the image processing device 3 mentioned above, image information transmission according to the CCITT recommendations is as follows.
First, before transmitting image information, synchronization with the other station is established\and image information is transmitted line by line based on this synchronization signal (6Hz). On the other hand, the receiving station sequentially stores each line in the line memory 4 in accordance with the synchronization signal. As described above, the line memory 4 includes two memory blocks each having a capacity of 16 lines (1 line - 1728 bits) and is used in a denial buffer system.

In addition, the above-mentioned recording device 7 performs main scanning (main scanning) by moving a recording head (thermal head) equipped with 32-bit recording elements in the vertical direction in the line direction, and performs recording while the head returns after line recording is completed. Move the paper vertically (sub-scanning).

Details of this recording device 7 are shown in FIG.
The diagram will be explained. Reference numeral 18 denotes a carriage for fixing the thermal head 23, and is movably attached to guide shafts 12 and 13 supported by side plates 10 and 11.

This carriage 18 is linked to a pulse motor that performs main scanning, and this pulse motor guides the carriage 12.
．． It moves back and forth on 13.

The pulse motor that performs the main scanning moves at a constant speed (moves to the right) in response to a main scanning pulse signal, which will be described later, and moves faster than the main scanning pulse signal (2
(double speed) is returned at high speed by the return pulse.

A thermal head drive circuit (
A circuit board 19 (see FIG. 3) is mounted thereon, and a thermal head 23 is attached by screws 24, 24 to a portion 18 that stands up at an inclined end at the tip of the goatee ridge 18.

This thermal head 23 is connected to the substrate 19 via a connector 21 with a flexible cable 22. Therefore, the thermal head 23 can be easily removed from the carriage 18 by removing the screw 24 and removing the flexible cable 22 from the connector 21. Further, the substrate 19 is connected to the recording control circuit 5 via a flat cable 25.

The flat cable 25 is flexible, and is connected to the substrate 19 after being fixed to the carriage 18 with a fixture 31. The number of signal lines in this flat cable 25 is preferably as small as possible for stable running (constant speed) of the carriage 18. Therefore, the drive signal is serially supplied to the drive circuit (circuit board 19) of the carriage 18, converted into a parallel signal by the circuit of the board 19, and then supplied to the thermal head 23. This aspect of the configuration will become clearer in the circuit configuration shown in FIG. 3, which will be described later.

26 is fixed to the side plates 10 and 11, and the thermal head 23
This is the back plate facing the

15.16 has recording paper guide rollers, side plates 10°11
One end is connected to a sub-scanning pulse motor by a transmission mechanism 30, and moves the recording paper upward. Therefore, a rotatable presser roller 14 is pressed against the roller 15, and a presser roller 17 rotatably supported by a shaft 27 that is moved away from the roller 16 by a lever 28 is pressed against the roller 16 by a spring 29. has been done.

Therefore, the leading end of the recording paper is pulled out from the rear roll paper of the recording device and held between the rollers 15 and 14, and the rear back plate 2
6 and the thermal head 23, and the rollers 16 and 1
7 and sent out.

The construction of the thermal head 23 is shown more clearly in FIG.

In FIG. 5, the thermal head 23 has a thermal chip 47 bonded to a substrate 46 (heat radiator), and on the left side of this chip 47 are heating elements 40 (resistors R1, R2, . . .
R32) is provided. These resistors R1, R2...
- As shown in Fig. 6, the arrangement of R32 is a 32-dot arrangement with an interval of approximately 0.18 dots, which corresponds to precision recording.

The other end of the heating element 40 (resistor RI+R2...R32) is led out to one end of the chip 47 as a contact, and this contact is connected to one end of the flexible cable 22 by a fixture 43.

The thermal head drive circuit mentioned in the above description will be explained with reference to FIG. 3. The circuit is constructed on a circuit board 19 mounted on a carriage 18.

A power supply +V is applied to one end of the resistors RI+R2...R82, and the other end is connected to a pair of drive circuit groups of A group and B group.

The A group is composed of Nant gates of GAI-GA32, and one input of these games GA to GA82 is connected to each corresponding bit output of the shift register 50, and the other input is connected to a recording control circuit. The drive pulse STR from 5 is input. The shift register 50 sequentially stores the recording data IN from the circuit 5 while being shifted by the shift clock signal HCL.

On the other hand, the B group consists of Nant's gates GB and GB32, and each corresponding bit output of the shift register 51 is connected to one input of GB and GB32, and the recording A temperature correction pulse 5TR2 output from the control circuit 5 is input. The shift register 51 sequentially stores the correction data IN2 from the recording control circuit 5 while being shifted by the shift clock signal HCL. This driving pulse STR,
is a pulse with a width of about 0.4ms, and 5TR2 is a pulse with a width of about 0.4ms.
This is a 6ms wide pulse.

Since the correction circuit made up of the B group is a thermal or heat-sensitive recording, the temperature rise time of the heating element differs depending on the presence or absence of previous data, and in order to keep the temperature of the heating element constant and the recording density constant. The correction is made to

Next, the specific structure of the recording control circuit 5, which clearly shows the characteristic structure of the present invention, will be explained in detail with reference to FIG.

61 is a shift register consisting of 17 bits,
It has a 16th bit output terminal 61a and a 17th bit output terminal 61b.

The shift register 61 is sequentially supplied with one column of recording data consisting of 16 bits from the line memory 4 and stored therein, and the data from the shift register 61 is transferred to a buffer register 63 consisting of 17 bits.

Further, the shift register 61 outputs an output 61a and an output 61 according to a clock signal supplied from the OR gate 109.
Shift output from b. Note that the same data is stored in the 16th and 17th bits of the shift register 61 from the line memory 4.

One input to the AND gate group 101 to 104 is the output of each bit of the shift register 61, and the other input is the output of each bit of the buffer register 63 that stores the record data of the previous column. is input via inverters 105-108.

The outputs of the AND gates 101 to 104 are stored in corresponding bits of another shift register 64 consisting of 17 bits. .

Therefore, the record data of one column before, that is, the output from the buffer register 63 is stored in the shift register 64 as "0".
and when the data in the shift register 6I is "1'2", 1"1++ is stored, and temperature correction data is stored. This shift register 64 is the shift register 61
It has the same configuration as .

This shift register 64 shifts output from outputs 64a and 64b in accordance with a clock signal supplied from OR gate 109.

The shift output 61b of the shift register 61 is input to the AND gate 115 which becomes valid when the flag 8 (see FIG. 1) is fine information [F].

The output of this AND gate 115 is derived as an output IN via an OR gate 117, and is introduced into a shift register 50 (FIG. 3) via a flat cable 25 as shown in FIG.

On the other hand, the shift output 64b of the shift register 64 is input to an AND gate 118 that becomes valid when fine information [F] is present, and the shift output 64a is input to an AND gate 112 that becomes valid when standard information is 0, and these gates 113 The outputs of and 112 are derived as output IN2 via OR gate 114, and introduced into shift register 51 (FIG. 8) via flat cable 25.

This is a 66ft reference clock generation circuit, which includes a frequency dividing circuit 67 for applying voltage to the shift registers 61, 64 and 50, 51, and a pulse motor for moving the carriage 18 (see FIG. 4) in the main scanning direction. A frequency dividing circuit 69 that generates pulses, a frequency dividing circuit 71 that generates drive pulses for a pulse motor that moves the recording paper in the upward sub-scanning direction, and a frequency dividing circuit 7o that generates a synchronizing signal for transmission of each line. is supplied to.

The frequency dividing circuits 67, 69 and 70, 71 described above are constituted by counters, and the frequency dividing circuit 67 further supplies a signal to a 1-bit flip 70 tube 68 to generate a pulse with a double period.

Further, a frequency dividing circuit 69 for main scanning of the carriage 18 outputs a pulse with a width of about 1.3 ms to an AND gate 126, and outputs a pulse with a period of about 14 seconds to an AND gate 126.
30, and this latter pulse is the drive pulse for the pulse motor in returning the carriage 18.

The frequency dividing circuit 71 supplies a pulse number to a counter 72, and has an a terminal that outputs "0" when 32 pulses are counted, and a b terminal that outputs "℃" when 16 pulses are counted. There is.

Further, the frequency dividing circuit 70 generates a synchronizing signal for transmission, but synchronization is established with the transmitting and receiving stations before image transmission, and a 6 Hz synchronizing signal is constantly generated.

74 is a heptadary counter, which counts the pulses from the AND gate 125 (output from the flip-flop 68) which are made valid by the output "P" from the inverter 122 and the set output from the flip-flop (F/F) 78.

When the counter 74 counts 7, the AND gate 12
It continues to output "1" until it is reset from 6. When the counter 74 outputs "1", the AND gates 121 and 113 through 116 become valid.

The output from the AND gate 121 is supplied to the AND gate 10 which becomes valid when the fine information is present, and the OR gate 109 outputs a clock signal for the shift operation.

In addition to the pulse of the AND gate 125 mentioned above, the pulse of the AND gate 111!, which is valid at the time of standard information, is applied in addition to the heptadary counter 74. The signal is supplied to the AND gate 118 which becomes valid when =71-in information is output, and the output of the gate 111 is as shown in FIG. It is output as the shift clock HCL of the shift register 50.51.

On the other hand, the pulse of the AND gate 124, that is, the 14-cycle pulse of the flip-flop 68, is outputted as the shift clock HCL via the AND gate 119, which becomes valid during standard information.

75 is a 32-decimal counter that counts the shift clock HCL, and a first timer 80 (0, 4
m5) and a second timer 8 that generates a correction pulse 5TR2.
1 (0,6m5). These pulse STR,
and 5TR2 are supplied to the drive circuit shown in FIG. 8 via a flat cable 25 (see FIG. 4).

Also, although the output of the 32-decimal counter 75 is not shown as 1,
It also serves as a start signal for transferring one column of data in the line memory 4 to the shift register 61.

The output of the frequency divider circuit 70 that generates the transmission synchronization signal (6 Hz) described above is supplied to the AND gate 129, and as the other input of this gate 129, the signal 200 output from the processing circuit when storage of 16 lines is completed is supplied. signal is being supplied. The output of this gate 129 causes a flip-flop (F/F) 73 to be set. Note that the signal 200
It is preferable to output the signal before the 17th synchronization signal.

The set output of the flip-flop (F/F) 7B is activated to output the main scanning pulse from the main scanning frequency divider circuit 69, and the counter 74
and 75, and supplies a drive pulse to the main scanning pulse motor via the OR gate 128.

Further, the main scanning pulse is supplied to an n-ary counter 76. This n-ary counter 76 is a counter that compensates for the rise of the pulse motor until it reaches a constant speed, and when it counts the n-ary, it outputs 111''.
Enable. The output of the AND gate 127 sets the flip-flop 78 and outputs the AND gate 1 for clock generation.
24,125 is valid. Further, the output of the AND gate 127 is supplied to the main scanning line counter 77 via an OR gate 181.

The main scanning line counter 77 counts the pulses and calculates +
Terminal a outputs “1” when counting 728 (corresponding to the recording width of A4 size), and terminal b outputs “1” when counting 1728+n (approximately the same as n of the n-ary counter 76 above).
These outputs continue to output "1".

The output from the a terminal continues to reset the flip-flop (F/F) 78 and also serves as a stop control signal for the pulse motor. The output of the b terminal resets the counter 76 and also inverts the flip 70 (F/F) 79. This F/F 79 serves as an instruction signal for the running direction of the carry nozzle 18, and instructs rightward movement when setting.

At the rise of the set output of the flip-flop (F/F) 79, the counter 77 and F/F 78 are reset, and the processing circuit 3 is instructed to complete the main scanning recording, and the data is transferred from the line memory 4 to the shift register 61. Stop the transfer.

Furthermore, the set output of this F/F79 is AND gate 18
7 is enabled, and the sub-scanning pulse from the AND gate 134 or the AND gate 135 is supplied to the sub-scanning pulse motor.

Next, the control operation (FIG. 2) of the apparatus of the present invention will be explained with reference to the time charts shown in FIGS. 8, 9, and 10.

This is a precision record, and flag 8 shown in FIG. 1 is set, and [F] indicating fine information is output.

Then, image information is transmitted from the transmitting station in accordance with the synchronizing signal, and this image information is stored for 16 lines in the line memory 4 shown in FIG. 2.

Before this 17th line image information synchronization signal is transmitted, a signal 200 is generated from the image processing circuit 3, and the AND gate 129 is opened to set the F/F 7B. Further, 16 bits of recording data of the first column are transferred from the line memory 4 to the shift register 61. At this time, please note that the same data is stored in the 16th and 17th bits.

The data introduced into the shift register 61 is first led out to AND gates 101-104. In the initial stage, the buffer registers 63 are all reset, so the shift register 64 stores the same data as the shift register 61. After this operation, the data in shift register 61 is transferred to shift register 63.

Here, ``■'' in FIG. 8 indicates the above-mentioned synchronization signal, and ``■'' is the signal 200 indicating the completion of storage, and the signal 200 is preceded by the synchronous signal ``200''.
00 is occurring.

In addition, ■ in FIG. 8 is a signal from the frequency dividing circuit 67, ■ is a signal from the frequency dividing circuit 68, and ■ is a signal from the frequency dividing circuit 69 (main scanning pulse).
are shown respectively, and ■ indicates the output of the adjacent 73 and ■ indicates the output of the F/F 78. Furthermore, the area [F] shows various signal waveforms when fine information is used, and the 0 area shows various signal waveforms when standard information is used.

On the other hand, as described above, by opening the AND gate 129, the F/F7 is
B is set, which enables AND gate 126.

As a result, a main scanning pulse (■ in FIG. 8) is output from the gate 126, which resets the counters 74 and 75 and supplies a driving pulse to the main scanning pulse motor via the OR gate +28. Further, the main scanning pulse is supplied to an n-ary counter 76, and the counter 76 counts it.

When the n-ary counter 76 counts the n-ary, the AND gate 127 opens, setting the F/F 78 and also supplying the signal to the counter 77. The AND gate 125 is enabled by the set output of the F/F 78, and the double period pulse from the F/F 68 is supplied from the gate 125 to the heptadary counter 74, and the AND gate I18 and H, t
A shift clock HCL is output via the agate 120. This shift clock HcL is supplied to the 32-decimal counter 75 and also to the shift registers 50 and 51 shown in FIG.

Further, the counter 74 is “0” until it counts in hexadecimal.
”, therefore AND gates 113 and 11
6 remains closed, and the recording data IN and correction data IN2 are not output. Therefore, the previous shift registers 50° and 51 are shifted to 7 bits “0” (
(See SAI in Figure 9).

On the other hand, when the counter 74 counts a hexadecimal value, the AND gate 121 becomes valid and the AND gate 11
3 and 116 are valid.

When the AND gate 121 opens, the shift clock H is transmitted through the AND gate 110 and the OR gate 109.
Pulses from the 8th CL are sent to shift registers 61 and 64.
supplied to The AND gates 113 and 116 are supplied with the respective outputs of 64b of the shift register 64 and 61b of the shift register 61, and the outputs of the shift register 64 and 61b are supplied to the recording data IN.
, and shift registers 51 and 50 as correction data IN2.
are supplied respectively.

Therefore, the recording data and correction data are sequentially shifted and stored in the shift registers 50 and 51.

The signals are shifted sequentially as described above, and when the counter 75 counts the 32-decimal value, it outputs "1".

At this time, as is clear from FIG. 9, the shift register 50 (51) has 17 bits of SA9 to SA25 set to "1".
It becomes. In other words, 17 lines (17 dots) of recording data are set for I6 line (16 dots) data.

The signal 5Al-3A26 in FIG. 9 indicates the state of each bit of the shift register 50 in FIG. 3, and in this example, the data indicates the state of output "1P" at all points.

AND gate 1 is activated by the “1” output of the counter 75.
24 and 125 are closed, the timer 80.81 is activated, and GAI-GA32 receives STR, GB, ~
GB - 5TR2 is supplied. This STR, and 5
While TR2 is being supplied, each gate opens and the heating element R
1 to R32 are energized and recorded.

In addition, since the GBI-GB82 is supplied with STR and the pulse 5TR2 with a longer width, the shift register 51
The corresponding bit where "!" is stored is energized for a long time to perform correction.

Further, the "■" output of the counter 75 is supplied to the processing circuit 3, which transfers the next column to the shift register row 1,
The above operation is repeated for each main scanning pulse.

When the recording of all the main scanning lines is completed by repeating the above operation, "1" is output from the a terminal of the counter 77, and the F/F
Reset 78. Therefore, AND gates 124 and 125 are closed. Further, the main scanning pulse motor is controlled to stop by the output of the a terminal. After that, counter 77's b
When "1,n" is output from the terminal, the counter 76 is reset, the F/F 79 is inverted and set, and the set output resets the F/F 7B, and the AND gate 12
6 to stop outputting the main scanning pulse.

On the other hand, AND gates 130 and 137 are enabled by the set output of F/F 79, and when this AND gate 130 is opened, a return pulse shorter than the main scanning pulse period output from frequency dividing circuit 69 is supplied to the main scanning pulse motor. Returns the carry/discharge at high speed.

Furthermore, when the gate 137 is opened, the sub-scanning pulse motor is caused to feed the paper for 16 lines.

It should be noted here that since the recording consists of 17 lines, the first line of the next 16 lines of recording overlaps with the recording position of the 17th line.

This is to correct the pitch unevenness of the sub-scanning lines by overlapping the recording positions.

It should also be noted that, as is clear from FIG. 9, the center 16 dots (17 dots) of the 32 bits, that is, 5A25 to SA9, are used for this fine information. This is because a stable image can be obtained because the center of the recording head is in close contact with the recording paper, and in the case of facsimile, it is also equipped with an image reading device, and in this case, the carriage with the recording head is A reading optical system is also provided. For this reason, the same synchronization signal is used, so when reading precision, the optical system lens is flattest at the center, resulting in a stable reading output (2) Standard information In this case, since this is coarse density recording, the flag 8 in the rod 1 diagram is reset and a symbol ``■'' indicating standard information is output.

This coarse density recording also operates in the same way as the precision (fine information) recording described above, but especially when the clock signal HCL
The difference is that is a clock signal with a circular period at the time of fine information.

That is, in FIG. 2, the signal ■ indicating standard information
by Antogame r 111, 112° 115 and 1
19 becomes valid, and the 1/2 cycle clock signal output from the AND gate 124 is supplied to the shift register 50.51 as HCL via the OR gate 120.

In addition, a clock signal with a period twice that of the shift clock HCL output from the AND gate 125 is output from the AND gate 125.
11 to shift register 61 via OR gate 109
, 64.

The 16th bit output 61a of the shift register 61 is connected to an AND gate 115. INI via or gate 117
The signal is shifted into the shift register 50 based on the clock signal.

Further, the 16-bit output 64a of the shift register 64 is connected to the AND gate 112. The signal is shifted into the shift register 51 as the IN2 signal via the OR gate 114 based on the clock signal.

In this way, the clock signal of shift register 50.51 is supplied with two pulses for each clock signal of shift register 61.64, so that shift register 61.
Two bits of data are stored in shift registers 50 and 51 for one bit of 64.

Figure 10 shows the shift register 50 in Figure 3 at this time.
This example shows the case where only 14 bits and 16 bits of image information are 1''.

Then, counter 75 in Figure 2 hits base 32! Then, as shown in the electrical diagram above, 5A27.5A2
8 and 5A811sA82 become 1"1".

In this way, a coarse density image is recorded with a head having a precision bit array. Note that the operations other than the above are the same as those for the fine information described above, so the details will be omitted.

f3) Nidori 11 The last bit (16th bit) for the above fine information
Although the 17th bit is added to the 17th bit so that it overlaps with the beginning of the next line, conversely, 1 bit may be added before the beginning bit and it overlaps with the 16th bit of the previous line. In addition, as shown in FIG. 7, the resistor RI+ of the thermal head
A resistor (heating element) 1.5 to 2 times larger than other dots may be formed at the end (or beginning) of R2...R82.

On the other hand, in the shift register 64 in FIG. 2, "1" is recorded only in the newly recorded bits by comparing the data with the data in the previous column, but conversely, "1" is recorded only in the bits that have already been recorded.
1゛, and the output of ri81 is shorter than this by 0.4ms.
You can also use it as

Further, the timers 80 and 81 are provided with a sensor for detecting the temperature of the resistor, and the pulse width is set to 5TRI according to this temperature.
, 5TR2 may be made variable.

As described above, the image recording apparatus of the present invention records images with a coarse density (standard information) and a precision (fine information) that is at least twice the coarse density. By providing a recording head with a dot density and recording one bit of precision recording information corresponding to at least two or more bits of the recording head when recording at a coarse density, it is possible to record at any density. This eliminates the problems of fixed devices.

Characteristic configurations of the embodiments of this invention are listed below.

■ By providing a recording head with at least a precision dot density and recording one bit of precision recording information in correspondence with at least two or more recording heads when recording at a coarse density, it is possible to An image recording device designed to record images.

■ In the device described in ■ above, at least the V of the recording head
a first storage means for accommodating recording data having a capacity of 2 or less; and a second storage means for accommodating the recording data having a capacity corresponding to each dot of the recording head; An image recording device configured to perform a shift operation and transfer data from a storage device to a second storage device using a clock that is twice or more faster.

(2) An image recording apparatus according to (2) above, which uses all dots of the recording head for coarse density recording, and uses the central portion of the recording means for precision recording.

[Brief explanation of the drawing]

Figure gJ1 is a block configuration diagram showing the image recording section of the facsimile apparatus according to the present invention, Figure 2 is a block circuit diagram showing a more specific configuration of the recording control in Figure 1, and Figure 3 is a recording head drive circuit diagram. , FIG. 4 is a perspective view showing the configuration of the recording apparatus, FIG. 5 is a diagram showing the specific configuration of the recording head, FIG. 6 is a diagram showing the arrangement of resistors of the recording head, and FIG.
The arrangement diagrams, FIGS. 8, 9 and 10 showing other embodiments of the figure are time charts for the control operation of FIG. 2. 1: NCU, 2: Modem, 3: Image processing device. 4 two-line memory, 5: recording control circuit, 6: clock generation circuit, 7: recording device, 50 and 51: shift register, 61.63 and 64: shift register, 66 two reference clock generation circuits, 67, 69°70 and 71: frequency divider circuit, 68: flip-flop, 74 linear counter,
75: 32-decimal counter. 76: n-ary counter, 77: main scanning line counter, 8
0: first timer, 81: second timer. Agent Patent Attorney Aihiko Fukushi

Claims (1)

[Claims] 1. An apparatus for recording an image with a coarse density (standard information) and an image with a precision (fine information) at least twice the coarse density; It is equipped with a recording head that has a dot density of about 100 degrees, and when recording at a coarse density, one bit of recorded information with one-frame precision is recorded in correspondence with at least two or more dots of the recording site. An image recording device characterized by the following.