JPS5867479A - Heat-sensitive recorder - Google Patents

Abstract

PURPOSE:To record a good-quality picture without causing uneven density of recording due to inuniformity of the temperature of heating element by providing a compensatory means for preventing the unevenness of recording density. CONSTITUTION:In a circuit controller 1 called NCU, a public telecommunication circuit is connected to a modem 2 and controlled, and analong information to be sent from a partner office is converted into digital information by the modem 2 and then supplied to an image processor 3. In the image processor 3, processing made according to a procedure determined under the advise of CCITT, judgement is made on the basis of control information from the partner office or the operation switch of a receiving station, and a flag 8 is controlled. In this case a fine information is output to F and also a standard information is output to S. Picture information sent is stored in a memory 4, and a vertical 32-bit picture information is serially output to the heat-sensitive recorder 7 according to synchronous signal from a clock generation circuit 6 by a recording control circuit 5.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to control of a thermal recording device that is effective for recording devices such as facsimile IJ devices.

In particular, the present invention provides a compensation means for compensating for uneven recording density due to uneven temperature rise of the heating element in a thermal head, that is, continuous [2. The present invention provides a thermal recording device equipped with the following.

As a compensation means, in addition to the current recorded data to be recorded, the previous recorded data that preceded the current recorded data by one is stored and held, and the heating element corresponding to the dot position where this previously recorded data is located and the previous recorded data are stored. Regarding the heating element for a dot position where there is no recording data, the latter is driven longer than the former.

A facsimile machine equipped with a thermal recording device of the present invention will be described below.

FIG. 1 is a block diagram showing an extracted image recording section of a facsimile machine.

In FIG. 1, ■ is a line control device called NCU, which controls the connection of the public line to the modem 2. The modem 2 converts the analog information transmitted from the other station into digital information and sends it to the image processing device 3. supply

The image processing device 3 performs processing according to the procedure determined by the CCITT recommendations. In addition, the processing device 3 determines whether the image information transmitted from the other station has precision (hereinafter referred to as fine information) or coarse density (hereinafter referred to as standard information). The judgment is made based on the control information or the operation switch of the receiving station, and the flag 8 is controlled. In this case, if it is fine information, the [F] ratio is output from the flag 8, and if it is standard information, it is output.

4 is a memory for storing the transmitted image information;
It has a capacity that can store two blocks of information for six lines.

Reference numeral 5 denotes a recording control circuit, which serially outputs the clock generation circuit 6 report to the thermal recording device 7. The details of the recording control circuit 5 having the characteristic configuration of the present invention are specifically shown in FIG.

The clock generation circuit 6 supplies a plurality of synchronization signals to the image processing device 3 and line memory 4, which are indicated by 1-.

To explain a little about the processing operation of the image processing device 3 mentioned above, image information transmission according to the CCITT recommendation is as follows.
First, before transmitting the image information, synchronize with the other station, and then determine which synchronization signal (6Hz) is used to transmit the image information! Transmit each line. On the other hand, the receiving station sequentially stores each line in the line memory 4 in accordance with the synchronization signal. As mentioned above, the line memory 4 has a capacity of 16 lines (1 line =
It is equipped with two memory blocks each having +728 pits and is used in a dual-balance system.

In addition, the recording device 7 described above performs main scanning (main scanning) by moving a distribution head (thermal head) equipped with a 32-bit recording element in the vertical direction in the line direction, and performs recording while the head returns after line recording is completed. Move the paper vertically. (sub-scan).

The details of this thermal recording device 7 are shown in FIG. 4, and O 18, which will be explained with reference to FIG.
It is movably attached to the

This carriage 18 is linked to a pulse motor that performs main scanning, and is guided by this pulse motor.
2.13 It moves back and forth on the top.

The pulse motor that performs the main scanning moves at a constant speed (moves to the right) in response to a main scanning pulse signal, which will be described later, and moves faster than the main scanning pulse signal (2
(double speed) The circuit board 19 is mounted on the carriage 18 and is equipped with one driving circuit for the thermal head (see Figure 3). The part 18 that stood up with
', the thermal head 23 is attached to the
3 is connected to the board 19 via a connector 21 by a flexible cable 22. Further, the substrate 19 is connected to the recording control circuit 5 via a flat cable 25.

The flat cable 25 is flexible, and is connected to the substrate 19 after being fixed to the carriage 18 with a fixture 31. The number of signal lines in this flat cable 25 is preferably as small as possible for stable running (constant speed) of the carriage 18. Therefore, the drive signal is serially supplied to the drive circuit of the carriage 18 (circuit board +9), converted into a parallel signal by the circuit of the board 19, and supplied to the thermal head 23. This aspect of the configuration will become clearer in the circuit configuration shown in FIG. 3, which will be described later.

26 is the side plate 10. +1 fixed, thermal head 2
This is the back plate facing 3.

15. 1'6 is a recording paper guide roller, which has a side plate 10 degrees vertically, 1 rotatable 1 supported 16, and 1 with one end connected to a transmission mechanism 30.
is connected to a sub-scanning pulse motor to move the recording paper upward. For this purpose, a rotatable presser roller 14 is pressed against the roller 15, and a presser roller 17 rotatably supported by a shaft 27 that is moved away from the roller 16 by a lever 28 is attached to the roller 16 by a spring 29. It is pressed.

Therefore, the leading end of the recording paper is pulled out from the roll paper at the rear of the recording apparatus, is held between the rollers I5 and 14, and then passes between the back plate 26 and the thermal head 23, and then passes through the rollers 16 and 16.
and 17, and sent out.

The structure of the thermal head 23 described above is shown more clearly in FIG.

In FIG. 5, the thermal head 23 has a thermal chip 47 bonded to a substrate 46 (heat sink), and on the left side of this chip 47 there are heating elements 40 (resistors R1+R2...
・R32) is provided. This resistor RIIR2・
As shown in FIG. 6, the arrangement of R32 is a 32-dot configuration that corresponds to a record of spacing of about 3 centimeters and knitting precision.

The heating element 40 (resistor R+ + R2...R32)
The other end is led out as a contact point to one end side of the chip 47, and this contact point is attached to one end of the flexible cable 22 with a fixture 43.
connected by.

The driving circuit for a thermal head having the characteristic configuration of the present invention mentioned in the above description will be explained with reference to FIG.
The circuit is constructed on a circuit board 19 mounted on a carriage I8.

One end of this resistor RI rR2...R, 12 is the power supply +
V is applied thereto, and the other end is connected to a pair of drive circuit groups, group A and group B.

The A group consists of Nant gates GA+ to GAa 2, one input of which is connected to each corresponding bit output of the shift register 50, and the other input is connected to a recording control circuit. A drive pulse 5TR1 from 5 is input. The shift register 50 sequentially stores the recording data I N + from the circuit 5 while being shifted by the shift clock signal HCL.

On the other hand, the B group consists of Nant gates CB+ to GB32, one input of which is connected to each corresponding bit output of the shift register 51, and the other input is connected to a recording control circuit. A temperature correction pulse 5TR2 outputted from 5 is input. The shift register 51 sequentially stores the correction data IN2 from the recording control circuit 5 while being shifted by the shift clock signal HCL. This driving pulse STR+ is a Noculus with a width of about 0.4 ms, and the shunted 5TR2 is about 0.4 ms wide.
Since the correction circuit made up of the B group is a thermal or heat-sensitive recording, the temperature rise time of the heating element differs depending on the presence or absence of previous data. Correction is performed to keep the body temperature constant and the recording density constant.

Next, the specific configuration of the recording control circuit 5 having the characteristic configuration of the present invention will be explained in detail with reference to FIG. It is located around .64.

61 is a foot register consisting of 17 pits (
), and has a 16th bit output terminal 61a and a 17th bit output terminal 61b.

The shift register 61 is sequentially supplied with record data of 1 column of 16-bit colors of the line memory 4 and stored therein, and the data from the shift register 61 is transferred to a register 63 consisting of 17 bits. Ru.

Also, the shift register 61 is an OR gate! Output 61a and output 61 according to the clock signal supplied from 09
Shift output from b. Note that the same data is stored in the 16th pin and 17th bit of the shift register 61 from the first line memory 4.

One of the inputs to the AND gate group 101 to +04 is the output of each pit of the shift register 61, and the other input is the output register 63 which stores the recording data of the previous column. until each bit output is inputted via inverters 105-108.

The outputs of the AND gates 101 to 104 are stored in corresponding pins of another shift register 64 composed of 17 pins.

Therefore, the shift register 64 stores the recorded data of one column before, that is, the output from buffer 1/distaro 3.
'' and the data in the shift register 61 is ``1'', 1'' is stored, and temperature correction data is stored.

This shift register 64 has the same configuration as the shift register 61. This shift register 64 has an OR gate +0
According to the clock signal supplied from 9, the outputs 64a and 64b are shifted out.

The shift output 61b of the shift register 61 is input to the AND gate 115 which becomes valid when the flag 8 (see FIG. 1) is fine information [F].

The output of this ant game) + 15 is OR gate 1.17
As shown in FIG. 4, the signal is output as an output INI through the flat cable 25 and introduced into the shift register 50 (FIG. 3).

Shift output 64b of 7 register 64 with ○ to the other side] 13
and the shift output 64a is the standard information ■
The outputs of these gates 113 and 112 are led out as an output IN2 via an OR gate 114, and are introduced via a flat cable 25 to a shift register 5 (FIG. 3).

66 is a reference clock generation circuit, and a frequency dividing circuit 6 for applying the signal to the shift registers 61, 64, 50, and 51.
7, a frequency dividing circuit 69 that generates drive pulses for the pulse motor that moves the carriage 18 (see FIG. 4) in the main scanning direction, and a pulse motor that moves the recording paper upward in the sub-scanning direction. It is supplied to a frequency divider circuit 71 that generates drive pulses and a frequency divider circuit 70 that generates synchronizing signals for transmission of each line.

The frequency dividing circuits 67, 69, 70, and 71 described above are composed of counters, and the frequency dividing circuit 67 further supplies a pulse to a 1-pit flip-flop 68 to generate a pulse with a double period.

The frequency divider circuit 69 of the main scanning circuit of the carriage 1B has an output that supplies a pulse with a width of about 13 ms to the AND gate 126, and a pulse with a period of about h to the AND gate 1.
30, and this latter pulse is the drive pulse for the pulse motor in returning the carriage 18.

The frequency dividing circuit 71 supplies a pulse number to a counter 72, and has an a terminal that outputs "0" when 32 pulses are counted and a b terminal that outputs "0" when 16 pulses are counted. There is.

Further, the frequency dividing circuit 70 generates a synchronizing signal for transmission, but synchronization with the transmitting/receiving station is established before image transmission, so that the synchronizing signal of 6) Tz is constantly generated.

74 is a hexadecimal counter, which counts the pulses from the AND gate 125 (output from the flip-flop 68) which are made valid by the output "1" from the inverter 122 and the set output from the flip-flop ("/F) 78.

When the counter 74 counts 7, the AND gate 12
It continues to output ``'1'' until it is reset from 6. When this counter 74 outputs "'I", the AND gate 12
+ and the AND gate I + 3,116 becomes valid.

The output from the AND gate 121 is supplied to the AND gate 110 which becomes valid when fine information is provided, and the OR gate 109 outputs a clock signal for a shift operation.

In addition, the pulse of the AND gate 125 mentioned above is supplied to the AND gate II+, which is valid for standard information, and the AND gate 118, which is valid for fine information, in addition to the hexadecimal counter 74. The output of the AND gate 118 which outputs the shift clock signal is sent to the third gate via the OR gate 120.
It is output as the shift clock HCL of the shift registers 50 and 51 shown in the figure.

On the other hand, the pulse of the AND gate 124, that is, the pulse of half the period of the pulse of the flip-flop 68, is outputted as a shift clock HCL via the AND gate 119, which becomes valid during standard information.

75 is a 32-decimal counter that counts the shift clock HCL, and when it counts the 32-decimal number, a first timer 80 (0, 4
m5) and a second timer 8 that generates a correction pulse 5TR2.
1 (0,6m5). These pulse STR,
and 5TR2 are supplied to the drive circuit shown in FIG. 3 via the flat cable 25 (see FIG. 4).Although the output of the 32-decimal counter 75 is not shown,
It also serves as a start signal for transferring one column of data in the line memory 4 to the shift register 61.

The output of the frequency divider circuit 70 that generates the transmission synchronization signal (6 Hz) described above is supplied to the AND gate 129, and is outputted from the processing circuit as the other input of the gate 129 when the storage of 16 lines is completed. A signal of signal 200 is supplied. A flip-flop (F/F) 73 is set by the output of this gate 29. It is preferable that the signal 200 is output before the 17th synchronizing signal.

The main scanning pulse is output from the frequency dividing circuit 69 of the main scanning counter by activating +26, and the counter 7
4 and 75 and supplies a drive pulse to the main scanning pulse motor via the OR gate 128.

Further, the main scanning pulse is supplied to an n-ary counter 76. This n-ary counter 76 is a counter that compensates for the rise of the pulse motor until it reaches a constant speed.
The output of the AND gate 127 sets the flip-flop 78 to enable the clock generation ant game) 1
24.125 shall be valid. Further, the output of the AND gate 127 is supplied to a main scanning line counter 77 via an OR gate 131.

The main scanning line counter 77 counts the pulses and calculates +
The ai terminal outputs "l" when counting 728 (corresponding to the recording width of A4 size), and the b terminal outputs "l" when counting +728+n (-J = approximately the same as n of the n-ary counter 76). and these outputs continue to be l" outputs.

The output from the a terminal continues to reset the flip-flop (F/F) 78 and still serves as a stop control signal for the noise motor. The output of the b terminal resets the counter 76 and also inverts the flip-flop ("/F) 79. This "/F 79 becomes an instruction signal for the running direction of the carry nozzle 18, and instructs it to move in the right direction when cent. .

When the set output of the flip-flop (F/F) 79 rises, the counter 77 and F/F 73 are reset, and the processing circuit 3 is instructed to complete the main scanning recording, and the line memory 4 is transferred to the shift register 61. Stop data transfer.

Furthermore, the set output of this F/F79 is AND gate 13
7 is enabled, and the sub-scan pulse from the AND gate 134 or 135 is supplied to the sub-scan pulse motor.

Next, the control operation (FIG. 2) of the apparatus of the present invention will be explained with reference to the time charts shown in FIGS. 8, 9, and 10.

m In the case of fine information, this is a record of precision, and flag 8 shown in FIG. 1 is set, and ■) indicating fine information is output. Then, image information is transmitted from the transmitting station according to the synchronization signal,
This image information is stored for 16 lines in the line memory 4 shown in FIG. -) Open +29 and F//I? Set 73. Also, record data of the first column from the line memory 4]6
Pinot is transferred to shift register 61. At this time, 1
Please note that the same data is stored in the 6th bit and the 17th bit.

The data introduced into the shift register 61 is first led out to the game) lot~104. Since the buffer register 63 is all reset in the initial stage, the shift register 64 has the same data as the shift register 61. data is stored. After this operation, the data in shift register 61 is transferred to shift register 63.

Here, ■ in FIG. 8 indicates the above-mentioned synchronization signal, ■ is a signal 200 indicating the completion of storage, and the signal 2 is placed before the synchronization signal ■.
00 is occurring.

In Fig. 8, ① shows the signal of the frequency dividing circuit 67, ② shows the signal of the frequency dividing circuit 68, ③ shows the signal (main scanning pulse) of the frequency dividing circuit 69, and ② shows the signal of the frequency dividing circuit 67. It shows the output of F/F78.

Furthermore, the area [F] shows various signal waveforms during fine information, and the area ■ shows various signal waveforms during standard information.

On the other hand, as mentioned above, when the AND gate 129 opens, the synchronization signal via the gate 129 causes the F/F7 to open.
3 is set, and as a result, Ant Game) +26 becomes valid.

As a result, a main scanning pulse (Fig. 8) is output from the gate 126, and this main scanning pulse resets the counters 74 and 75 with a force N5-, and outputs the output voltage (or-game).
A drive pulse is supplied to the main scanning pulse motor via '28. Further, the main scanning pulse is supplied to an n-ary counter 76, and the counter 76 counts it.

When the n-ary counter 76 counts the n-ary, the AND gate 127 opens, setting the F/F 78 and also supplying the signal to the counter 77'. The AND gate 125 is enabled by the set output of the F/F 78, and the double period pulse from the F/F 68 is supplied from the gate 125 to the hexadecimal counter 74, and the shift clock is supplied via the AND gate 118 and the OR gate 120. Output HCL.

This shift clock HCL is supplied to a 32-decimal counter 75 and is shown in FIG. shift registers 50 and 5
1.

Further, the counter 74 is 0'' until it counts in hexadecimal.
It is outputting, therefore, AND gate 113]]6
remains closed, and the recording data INI and correction data IN2 are not output. Therefore, the previous shift register 50.51 is shifted by 7 piso) ll011 (see SA+ in FIG. 9) O On the other hand, when the counter 74 counts 7 digits, the AND gate 121 becomes valid and the AND gate 11
3 and 116 are valid.

When the AND gate 121 opens, the AND gate 121 opens.
) 110 and through Orgate 109.

The eighth and subsequent pulses of shift clock HCL are supplied to shift registers 6I and 64. The AND gates 113 and 116 are supplied with the respective outputs of 64b of the shift register 64 and 61b of the shift register 61, and these are supplied to the shift registers 51 and 50 as recording data I N + and correction data I N 2, respectively. Ru.

Therefore, the recording data and correction data are sequentially shifted and stored in the shift register 50.5+.

The signals are shifted sequentially as described above, and when the counter 75 counts the 32-decimal value, it outputs 1''.

At this time, as is clear from FIG. 9, the shift register 50 (51) has 17 bits of SA, ~5A25 j"1"
It becomes. In other words, 17 lines (17 dots) of recording data are set for 16 lines (16 dots) of data.

Signals SA to 5A26 in FIG. 9 indicate the state of each bit of the shift register 50 in FIG. 3, and in this example, the data is all black and indicates the state of the output ff.

The output of the counter 75 causes the AND gate 12
4 and ]25 are closed, the timer 80.8] is activated and STR is sent to GA, -GA32.

However, 5TR2 is also supplied to GB1-GB82.

While STR+ and 5TR2 are being supplied, each gate is opened and the heating elements R1 to R32 are energized to record.

In addition, since STR and the longer pulse 5TR2 are superimposed on GB and ~GBa2, the shift register 5
The corresponding bit where 1 is stored as "'1" is energized for a long time to perform correction.

In addition, the ``1'' output of the carantara 5 is supplied to the throughput path 3 to transfer the next column to the shift register 61, and the above operation is repeated for each main scanning pulse.

When the recording of all the main scanning lines is completed by repeating the above operation, a signal of 1" is output from the a terminal of the counter 77, and the F/F
Reset 78. Therefore, AND gates 124 and 125 are closed. However, the main scanning pulse motor is controlled to stop by the output of the a terminal. After that, counter 77's b
When 1" is output from the terminal, the counter 76 is reset and the F/F 79 is inverted and set. The cent output resets the F/F 73, closes the anti-gauge +26, and stops outputting the main scanning pulse. do.

On the other hand, AND gates 130 and +37 are enabled by the set output of F/F 79, and when the AND gates +30 are opened, a return pulse shorter than the main scanning pulse period output from the frequency dividing circuit 69 is supplied to the main scanning pulse motor. , return the carriage at high speed.

Furthermore, when the gate 137 is opened, the sub-scanning pulse motor is caused to feed the paper for 16 lines.

It should be noted here that since the recording consists of 17 lines, the first line of the next 16 lines of recording overlaps with the recording position of the 17th line.

This is to correct pitch unevenness of the sub-scanning lines by overlapping recording positions.

It should also be noted that for this fine information, as is clear from FIG. 9, the central 16-dot (17-dot) grooves 5A25 to SA9 of the 32 bits are used. This is because a stable image can be obtained because the center of the recording head is in close contact with the recording paper, and in the case of a small facsimile, it is also equipped with an image reading device, and in this case, the carriage with the recording head is It is also equipped with a reading optical system. For this reason, the synchronized newsletter uses the same one, so when reading precision, the center part of the lens of the optical system is the flattest, and a stable reading output can be obtained.

(2゛- In the case of standard information, this is coarse density recording, and the flag 8 in FIG. 1 is reset, and ■ indicating standard information is output.

This coarse density recording also operates in the same way as the precision (fine information) recording described above, but especially when the clock signal HCL
The difference is that is a 1/2 cycle clock signal when fine information is available.

That is, in FIG. 2, the signal ■ indicating standard information
By and gate II+, 112° 115 and 11
9 becomes valid, and 1 is output from the AND gate 124.
/2 period clock signal goes H through the OR gate 120.
It is supplied as CL to shift registers 50 and 51.

The clock signal with twice the cycle of the shift clock HCL output from the AND gate 125 is output from the AND gate I.
11 to shift register 61 via 109
．． 64.

The 16th bit output 61a of the shift register 61 is connected to an AND gate 115. IN+ via ORGATE+17
The 16 bit output 64a of the shift register 64 is shifted into the shift register 50 as a signal based on the clock signal. The signal is shifted into the shift register 51 as the IN2 signal via the OR gate 114 based on the clock signal.

In this way, the clock signal of the shift register 50.51 is supplied with two pulses for each clock signal of the shift register 61.64.
．． Two bits of data are stored in shift registers 50 and 51 for one bit of 64.

Figure 10 shows the shift register 50 in Figure 3 at this time.
This example shows a case where only 14 bits and 16 bits of image information are 1''. Then, when the counter 75 in FIG. 2 counts 32 digits, 5A27ISA28 and 5A311SA32 become r'1'' as shown in FIG.

In this way, a coarse density image is recorded with a precision bit arrangement. Note that the operations other than "2" are the same as those of the fine information described above, so the details will be omitted.

(:3) Other embodiments When the above fine information is used, the last bit (16th bit)
The +7th bit is added to the bit to overlap with the beginning of the next line, but conversely, one bit may be added before the leading bit and overlapped with the 16th bit of the previous line. In addition, as shown in FIG. 7, the resistor R+ of the thermal head
+R2...A resistor (heating element) 15 times to twice the size of the other dots may be formed at the end of R32 or at the beginning R38.

On the other hand, in the shift register 64 in Fig. 2, 1'' is recorded only for the newly recorded focus by comparing it with the data of the previous column, but conversely, 1'' is recorded only for the bit that has already been recorded.
'', set the output pulse of timer 80 to o6ms,
The output of timer 8I may be set to 0.4 ms, which is shorter than this.

A sensor is provided to generate a pulse with a pulse width of 5 depending on the temperature.
TR1, 5TR2 may be varied.

As described above, the thermal recording device of the present invention is equipped with a compensating means for preventing recording density unevenness, and is capable of recording data caused by uneven heating element temperature as seen in conventional thermal recording devices. Capable of recording high-quality images without uneven density 6.

[Brief explanation of the drawing]

FIG. 1 is a block configuration diagram showing an image recording section of a facsimile apparatus according to the present invention, FIG. 2 is a block circuit diagram showing a specific configuration of the recording control circuit of FIG. 1, and FIG. 3 is a recording head drive circuit. 4 is a perspective view showing the configuration of the recording device,
5 is a diagram showing the specific configuration of the recording head, FIG. 6 is a diagram showing the arrangement of resistors of the recording head, FIG. 7 is a diagram showing the arrangement and configuration of another embodiment of FIG. 6, and FIG. 9 and 10 are time charts of the control operation shown in FIG. 2. 1: NCU, 2: Modem, 3: Image processing device, cold 6
．． 4 two-line memory, 5: recording control circuit, 6: clock generation circuit, 7: recording device, 50 and 51: 'shift register, 61.63 and 64: shift register, 66 two reference clock generation circuits, 67, 69. 70 and 71: frequency divider circuit, 68: flip-flow knob, 7'/I near; l immo counter, 75: 32-base counter, 76: n-base counter, 77: main scanning line counter, 80: first timer,
81: Second timer 0 agent Patent attorney Aihiko Fukushi

Claims (1)

[Scope of Claims] l In a thermal recording device that performs a recording operation by relative movement between a gutter and a recording paper, recording is provided with a recording element (heating element) for a plurality of dots (for a plurality of recording lines), a first storage means for storing the current recording data to be recorded; a second storage means for retaining the presence/absence state of recording data at the time of the previous scan that preceded the current recording data by one; The recording element is driven based on the recording data. a drive circuit; and when the drive circuit operates based on the current recorded data in the first storage means, the recording element corresponding to the dot position in the second storage means corresponds to the data "presence". A thermosensitive recording device characterized by comprising a control means for controlling the drive for a longer time than a dot.