JPS5854755A - Decoding device - Google Patents

Abstract

PURPOSE:To make the size of a decoder small and to reduce the power consumption, by omitting a conversion circuit for code train at input or output side, through the feedback of a part of an output data of a decoding circuit to an input terminal. CONSTITUTION:An information bit from a serial data input terminal 9 is divided into n blocks, applied to a coding circuit 18 and a shift register 11 and a parity bit in the input code via a serial-parallel conversion circuit 7 is applied to the circuit 18. The result of intermediate operation for obtaining a syndrome of the circuit 18 is fed back to the input side of the circuit 18 with a feedback connection 12. Through this feedback, an operation output of K bits is generated at every operation of n times and syndromes S1-Sr are applied to a decoder 5. The result of decoding at the decoder 5 is applied to the shift register 11 of m stages via an exclusive OR circuit 16 to correct the error in the information bit of K bits.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a decoding device for correcting and detecting code errors occurring in a transmission system etc. by inputting a code error correction code and a code error detection code. The present invention relates to a decoding device that performs code error correction and code error detection using .

Memory elements (ROM and RAM) and logic elements (P
LA: Programmable Logic A
Conventionally, a decoding device using a decoder (rray) has been realized using a circuit as shown in FIG. Here, n and k are the number of bits of the received code error correction code and the number of pits of information bits, respectively, and this code is (n
, k) is called a code. An n-bit error correction code b1. ...bn is input, and bit decoding output (information) is output from decoding output terminal 2 C1,...
Ck is output. n-bit error correction code W= (b
t, ..., bn) is H@
A generator matrix G with rows and n columns is defined from GT=O. The code V-(al, ag,...
...+ak), the error correction code is W-V ・G −
(bt , bg , *ee e , bn), where W is a code consisting of n bits.

The received code is expressed as W′ −(b+′, b%, 5ees,
l) n+), the receiving side calculates the syndrome, and if the obtained column vector of bits is O, there is no error, and if it is non-zero, the bit at the position corresponding to that column vector is inverted. Bits can be corrected. A decoding device 1 performs calculations of this syndrome and corrects errors.
Do it with

Figure 2 shows (al, ag, see, alO=(b+
,t)+,ass...,bk) is the decoding system ff when using an error correction code called a systematic code,
A feature is that the capacity of the memory element or the circuit scale of the logic element can be reduced. Syndrome S-(El 1,
'2)..., 8r) is the information part (bt', bg') of the received code W1.

Parity bits (pl', pg", II@1111.pr" obtained by encoding . . . , bk') in circuit 4
) in the received code W1, the parity part (p1°lPR'
l...+pr') by the exclusive OR circuit 6. The decoder 5 is a circuit that detects the position of the column vector of H corresponding to the syndrome S, and the output of the decoder 5 is added to the information portion of the received code W1 at the input terminal by an exclusive OR circuit 16 to correct errors. will be held. Circuits 4 and 5 are each composed of logic elements or memory elements.

On the other hand, when using an error correction code, input information may be serially-parallel converted and then encoded.

That is, as shown in FIG. 3, S= input from the input terminal 9
n/m bits of input information (d+, ds, amp, dB
) is converted into parallel for m time slots by the serial/parallel conversion circuit 7, and n bits (bs', bg', . . .
.

bk'+p"+pg'+""%Pr') and is input to the reprinter 17, and the error-corrected information bits are Ql
, C2, . . . , Ck. This code is converted into q = k/m bits of serial information (el, 1142.@・Φ・, eq) by the parallel/serial conversion circuit 8 in order to match the speed with the transmission codes dt, d2゜...φ・, ds. and is output to the lfj power terminal 10.

In this case, as can be understood from FIG. 3, if the conventional device shown in FIG. This has the disadvantage that the capacity of the memory element or the scale of the logic element increases because the memory element is multiplied.

This invention divides an input code organized into (n, k) into m blocks, feeds back a part of the input data to the input, and performs an operation between the feedback input and the input of each block. In order to obtain the intermediate result of the calculation to obtain the syndrome, and to feed it back as described above and obtain the syndrome by performing m calculations, the serial-to-parallel conversion circuit is omitted and the capacitance of the element is reduced. It is an object.

Another object of the present invention 1: input an unorganized input code of (n, k) into m blocks, feed back part of the output data to the input, and combine the feedback input with the input of each block. The intermediate result of the operation is performed to obtain bit information, and this is fed back as mentioned earlier, and the information bit is obtained by m operations, thereby omitting the serial-to-parallel conversion circuit. and reduce the capacitance of the element.

FIG. 4 shows an embodiment of the invention, in which an (n, k) block code is transmitted using m time slots for each S bit.
No.(b+,bg,・m-1bklp11p21""1p
r), and the received data (dl.

d2. ***, ds, gl, g2. m time slots of ``'+gj) are decoded as a block S
≧Yes.

t≧r/m0 The input code υ, which is a time slot for each S bit, from the input terminal 9 is input to the shift register 11 having m stages of S bits. On the other hand, the S bit input from the input terminal 9 is input to the code circuit 18, the intermediate calculation result obtained by the code circuit 18 is output to the intermediate data output terminal 12, and this intermediate calculation result is fed back to the input of the code circuit 18. Ru. The parity bit in the input code is input to the code circuit 18 through the serial/parallel conversion circuit 7. The code circuit 18 is comprised of preprogrammed storage elements or logic elements. The address of the code circuit 18 has an n-bit input code m
The intermediate data is divided into blocks, one block of S bits is sequentially added, and the code-converted intermediate data is fl, f2, .・
. . . is output to the terminal 12 as +f, +(j≦t). This intermediate data is an intermediate calculation result in the calculation to obtain the syndrome, and the next time slot information is code-converted and output as the next intermediate data. This is repeated, and in the m-th final time slot, a syndrome is calculated between the intermediate data and the input data, and the syndrome (Sl, Sg, . . . , Sr) is output.

The decoder 5 detects an erroneous sibit corresponding to this syndrome. The m-stage shift register 11 is configured to correct errors in the information bits in the m time slots in the final time slot. It is taken by.

For example, if the (n,k) code is a (7,4) code, the generator matrix is bj+, bg, b4 . pt, pg, ps) is (bt
, bg, ps, pg), (bs, b4.pg, *
) is divided into two time slots and transmitted.

However, the book shows don't care.

In Figure 4, at the first time slot
(dl, d2)-(b1', bg')) The intermediate result (fl, f2°fs) is calculated according to the following equation. However, bl', bgo.

b8'Ip"Ip2'Ip"") is the received code.

In the second time slot, the parity (pt") encodes the information part of the received code according to the following equation.

p2''+98°) is output.

■ indicates addition modulo 2.

On the other hand, the parity part (pl') of the received code.

pg1) and (P"+*) are converted to (p"+P"Ip"+") by the serial/parallel conversion circuit 7, and by adding the information part to the encoded parity (pl"+92Zp"), the syndrome S becomes ( 81, 82, all): (pj'■p' ” + P
"'■T""Ip" ps1) is input to the decoder 5.

Generally, when the device of the present invention is used for an (n, k) code, the capacitance C of the memory element used in the device is expressed by the following formula.

FIG. 5 illustrates this, where rn=1 is the case of the conventional device. It can be seen that by using this invention, not only can the 111 parallel conversion circuit be omitted, but also the memory capacity can be reduced depending on the value of n.

Serial/parallel conversion of input parity part 171114iA 7
The functionality of the J and syndrome decoder blocks can also be included within the encoder circuit 18. An example of this is shown in FIG.

The functions of the m-1 stage shift register 11 and the error bit correction circuit 160 can be included inside the code circuit 18. FIG. 7 shows this embodiment. Fourth
As shown in Figures 6 and 7 (10), the feedback of intermediate operation results must be delayed by one time slot with respect to the input code block that is the basis of the feedback, and this point is necessary. According to this, a delay element 13 is inserted in the feedback path as shown in FIG. 8, for example.

Even for codes that are not systematic codes, it is possible to reduce the capacitance of the elements and to omit serial/parallel circuits by feeding back the intermediate results output from the output terminals of the memory elements or logic elements to the input terminals. That is, it consists of n bits,
It receives and inputs an unorganized (n, k) code in which bits are information bits, and calculates and outputs information bits of one bit corresponding to all combinations of the n bits. Error-corrected information bits are obtained by using a decoding device comprising a memory element or a logic element. In this case as well, the input is m
Divide into blocks and input sequentially, feed back part of the output to the input, calculate the feedback result and input, obtain the intermediate result of the operation to obtain information bits, and feed back this intermediate result. , output a bit of information for every 0 input operations? 4. In this case, the embodiment is similar to the configuration shown in FIG.
k) A configuration for obtaining information bits for the code.

On the other hand, there are generally unnecessary data bits for calculating parity pits for code error correction. For example, the above (7,
4) In the case of a code, bl is not required to calculate fll.

Therefore, unreliable input data exists in the code circuit 18 for outputting each parity pin +1, and there is no need to connect this input data to the input terminal. FIG. 9 shows this example, and shows each parity pin calculation memory element or logic element 4a, 4b, fist, 4n in the code circuit 18.
Only necessary inputs among inputs d1 to d8 are selectively connected. Intermediate result feedback connections 12a-12n are connected to these elements 4a-4n, respectively. According to such a configuration, the number of elements to be accommodated can be reduced by an amount that does not require wiring. For example, if the number of wires that are no longer required to be connected is l, the capacitance of the element can be reduced one by one.

In the embodiment shown in FIG. 4, n bits of information 2
Although the correction of m time slots was performed simultaneously by inputting data for minutes and holding the information bits in shift register 1 until the syndrome is obtained, it is also possible to correct the information bits one time slot at a time by shifting the parity check output. can. An example of this is shown in FIG. That is, the block of S bits from the input terminal 9 is delayed by m time slots in the delay circuit 21, and the block of S bits from the input terminal 9 is delayed by m time slots.
time slot) and is outputted to the exclusive OR circuit 16.
is input. The first time slot of its output is directly corrected at the output of decoder 5, and the second time slot of the next output is corrected by shift register 1 delayed by l time slots.
1, and each subsequent output time slot is sequentially delayed by one time slot.
Corrected with output of 1. The embodiments shown in FIGS. 6 and 9 are similarly configured to shift the validation output, thereby reducing the number of exclusive OR circuits 16 for correction. It is better to have such a configuration (1v
Since there is no need to insert the exclusive OR circuit 16 into the signal bit delay circuit 21, the reliability of the decoder can be improved.

As explained above, by feeding back part of the output data of the encoder circuit 18 to the input terminal, it is possible to omit the serial/parallel converter circuit provided on the input terminal side or the parallel/serial converter circuit provided on the output terminal side. It is possible to reduce the capacitance of the element.

Therefore, it is possible to downsize the decoding device and reduce power consumption.

[Brief explanation of the drawing]

Fig. 1 shows a conventional decoding device using memory elements or logic elements, Fig. 8g2 shows a conventional decoding device for systematic codes, and Fig. 3 shows a conventional decoding device using a serial/parallel conversion circuit. FIG. 4 is a diagram showing a decoding device, FIG. 4 is a diagram showing an embodiment of the present invention, and FIG. 5 is a diagram showing a divided block (
FIGS. 6 to 10 are diagrams showing the relationship between the number of time slots and the number of required cumulators, respectively, and are diagrams showing other embodiments of the present invention. 1 and 4: ml storage element or logic element, 2: Reception code input terminal, 3: Decoded output (information code), 5: Decoder, 6
．． 16: Exclusive OR circuit, 7: Serial/parallel conversion circuit, 8:
Parallel-to-serial conversion circuit, 9: serial data input terminal, 10: serial data output terminal, 11: shift register, 12: intermediate data feedback connection, 13: delay element, 18: code circuit. Patent applicant: Takashi Kusano (15), representative of Nippon Telephone 8 Telephone Public Corporation

Claims (2)

[Claims] (1) Consists of n bits (n is a positive integer), one of which
(An organized (n, k) code is input, where bit (1 (is a positive integer, k < n) is an information bit, and (n-k) bits are parity bits, and The parity code of (n-k) bits corresponding to all the combinations of the information bits of the bit is calculated, and the calculated parity code and the parity bit of (n-k) bits in the input code are calculated. In a decoding device that calculates a syndrome from , decodes the syndrome with a decoder, and performs error correction on the information bits of the bits using the output of the decoder, the input code is m(2
It is divided into blocks of the above integer m (lc) and inputted sequentially, and the calculation results are inputted as feedback, and for each input of each block, calculation is performed on the input and the calculation result inputted as feedback, and the syndrome is What is claimed is: 1. A decoding device comprising: a coding circuit which obtains an intermediate result of an operation for obtaining and outputs it as the feedback input, and outputs the previous jjij syndrome every m operations. (2) An organized (n, k) code is input, consisting of n pits (n is a positive integer), of which there are pits (k is a positive integer) and k(n) is the information bit, and the input In an I-M encoding device that calculates and outputs information bits corresponding to all combinations of n pits of a code, the input code is divided into nl (2 or more ua, m<n) blocks. 91. Calculation button is returned manually, and for each input of each block, the input and the input operation result are subtracted to obtain an intermediate result of the operation for obtaining the information bit. and an encoding circuit which outputs the information bits every m operations, with an output j~ as the induction input.