KR101304570B1 - Methods of Generating Parity Check Matrix, Error Correction Methods and Devices using thereof, and Memories and Electronic Device using thereof - Google Patents

Abstract

A maximum column weight preferred decoding unit is provided that reduces the number of inputs of the decoder of the ECC module to reduce the area of the decoder. At least one decoder of the decoding unit has an input equal to the maximum column weight of the column of the H-matrix with the maximum column weight.

Description

Method of Generating Parity Check Matrix, Error Correction Methods and Devices using about, and Memories and Electronic, including parity check matrix generation method, error correction method and device, decoder for error correction device, and error correction device Device using kind}

An embodiment of the inventive concept relates to a semiconductor device, and more particularly, to memory error correction.

In order to improve the reliability of the memory, error correction code technology has been applied to the memory. In particular, in order to reduce the area of the error correction code execution circuit and to improve the operation speed, it has been developed in order to improve the structure of the error correction code execution circuit and to improve the error correction code on which it is based.

Document 1 proposes a Hamming code, which is the single error correction code that is most widely used at present. Hamming code was developed in 1950 to correct errors in communication systems. This assigns a sequential fixed value in binary to the column vector value assigned to the data bits in the H-matrix. The Hamming code is an early error correction code that greatly improves the reliability of the communication system. However, in the memory application, the Hamming code requires a large area and an operation time of the error correction code execution circuit.

Document 2 significantly reduces the area and operation time of the error correction code execution circuit by making the column weight of all columns allocated to the data bits in the H-matrix equal to two. However, it has a disadvantage of requiring much more check bits than the check bits required in the existing single error correction code, including Hamming code.

Literature 3 focuses on reducing the area and operating time of the check bit generator in the error correction code execution circuit, while requiring the same check bits as the Hamming code, reducing the overall weight in the H-matrix and increasing the largest row weight to a certain level. It decreased below. However, other parts of the error correction code execution circuit, including the decoder, are configured identically to the Hamming code.

1. R. W. Hamming, “Error detecting and error correcting code,” Bell System Technical Journal, vol. 26, pp. 147 160, Apr. 1950. 2. Document 2 P. K. Lala, P. Thenappan, and M. T. Anwar, “Single error correcting and double error detecting coding scheme,” IET Electronics Letters, vol. 41, Issue 13, pp. 758760, Feb. 2005. 3. Document 3 S. Cha, and H. Yoon, “High speed, minimal area, and low power SEC code for DRAMs with large I / O data widths,” Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on, pp. 30263029, May. 2007.

An embodiment according to the inventive concept provides a decoder unit for an error correction code.

An embodiment according to the inventive concept provides a method of generating an H-matrix.

An embodiment according to the inventive concept provides an error correction code module.

The technical objects of the present invention are not limited to the above-mentioned technical problems, and other technical subjects not mentioned can be clearly understood by those skilled in the art from the following description.

The decoder unit for the (n, k) error correction code according to an embodiment of the present invention includes a plurality of decoders receiving different numbers of inputs, wherein at least one of the plurality of decoders is the maximum column weight of the H-matrix. Has the same input as the heat weight of the column.

In one embodiment, the decoder unit comprises at least one first decoder having (n-k) inputs and at least one second decoder having inputs smaller than (n-k).

In one embodiment, the number of inputs of the second decoder is equal to the maximum column weight.

An ECC module according to an embodiment of the present invention includes a check bit generator for generating a write check bit from received message data (k bits) and a read check bit (m bit) from received and stored message data, a read check bit, and A syndrome generator for calculating a syndrome from a write check bit, and a decoder unit for detecting an error by using an output of the syndrome generator as an input, the decoder unit including a plurality of decoders receiving different numbers of inputs; At least one of the decoders has an input equal to the column weight of the column with the maximum column weight of the H-matrix.

In one embodiment, it includes at least one first decoder having (n-k) inputs and at least one second decoder having inputs smaller than (n-k).

In one embodiment, the number of inputs of the second decoder is equal to the maximum column weight.

The decoder unit for the (n, k) error correction code according to an embodiment of the present invention includes n decoders corresponding to the number n of columns of the H-matrix, and includes a column having a maximum column weight of the H-matrix. The corresponding decoder has an input equal to the maximum column weight.

H-matrix generating method according to an embodiment of the present invention, the first condition that there is no column of all zeros; A second condition in which each column is distinct from all other columns; The third condition of maximizing the number of rows having the maximum column weight is satisfied.

In one embodiment, each row weight further satisfies a fourth condition where the total weight of the matrix is an integer close to the number divided by the number of rows.

In one embodiment, the heat is filled in the order of 2, 3, ..., MCW-2, MCW, MCW-1.

An embodiment of the present invention provides a computer-readable recording medium storing a program for performing the method of generating the H-matrix.

According to an embodiment of the present invention, the number of inputs constituting the maximum column weight preference decoder is reduced, so that the area of the maximum column weight preference decoder is also reduced compared to the existing decoder.

The area reduction effect of the maximum column weight preference decoder may be further maximized through the maximum column weight preference error correction code according to an embodiment of the present invention, which maximizes the number of columns having the maximum column weight of the H-matrix.

The maximum column weight preference error correcting code according to an embodiment of the present invention can reduce the operation time of the path having the longest operation time in the check bit generator in comparison with the hamming code by matching all the row weights similarly. Therefore, the operation time of the entire error correction code execution circuit can be reduced.

The maximum column weight preference decoder and the maximum column weight preference single error correction code according to an embodiment of the present invention have a small area burden and a small amount of memory in a memory having a small number of data bits that read / write at a time, such as DRAM or SRAM. Enable error correction code execution circuitry of operating time.

1 illustrates a memory device according to an embodiment of the present invention.
2 illustrates an ECC module according to an embodiment of the present invention.
3 shows an example decoder of an ECC module.
4 shows a decoder of an ECC module according to the prior art.
5 illustrates a decoder of an ECC module according to an embodiment of the present invention.
FIG. 6 illustrates a comparison of the number of transistors used in an error correction code performing circuit using a maximum column weight preferred single error correction code using a maximum column weight preferred decoder and a conventional hamming code according to an embodiment of the present invention.

Other advantages and features of the present invention and methods of achieving them will become apparent with reference to the embodiments described below in detail with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims.

Unless defined otherwise, all terms (including technical or scientific terms) used herein have the same meaning as commonly accepted by the generic art in the prior art to which this invention belongs. Terms defined by generic dictionaries may be interpreted to have the same meaning as in the related art and / or in the text of this application, and may be conceptualized or overly formalized, even if not expressly defined herein I will not.

The terminology used herein is for the purpose of illustrating embodiments and is not intended to be limiting of the present invention. In the present specification, the singular form includes plural forms unless otherwise specified in the specification. As used herein, the terms' comprise 'and / or various forms of use of the verb include, for example,' including, '' including, '' including, '' including, Steps, operations, and / or elements do not preclude the presence or addition of one or more other compositions, components, components, steps, operations, and / or components.

The term 'and / or' as used herein refers to each of the listed configurations or various combinations thereof.

On the other hand, the terms '~', '~', '~ block', '~ module', '~ unit' used throughout the present specification may mean a unit for processing at least one function or operation. have. For example, a hardware component, such as a software, FPGA, or ASIC. However, the terms '~', '~', '~ block', '~ module' and '~ unit' are not limited to software or hardware. '~', '~', '~ Block', '~ module', '~ unit' may be configured to be in an addressable storage medium or may be configured to play one or more processors. . Thus, as an example, '~', '~', '~ block', '~ module', '~ unit', etc. are software components, object-oriented software components, class components, and task configurations. Components such as elements, processes, functions, properties, procedures, subroutines, segments of program code, drivers, firmware, microcode, circuits, data, databases, data It includes structures, tables, arrays, and variables. The components and functions provided within '~', '~', '~ block', '~ module', '~ unit' can be divided into smaller components and '~', '~~' , Combined with '~ block', '~ module', '~ unit' or further separated into '~', '~ gi', '~ block', '~ module', '~ unit' Can be.

1 is a memory device according to an embodiment of the present invention. The memory device includes an error correction code (ECC) module 100 and a memory 200.

The ECC module 100 encodes user data provided from a host by an error correction code method according to an embodiment of the present invention. The ECC module 100 may convert user data including a message into a codeword vector using a parity check matrix. In general, data bits and check bits are mixed in a codeword, or are stored in the memory 200 in a sequentially connected state. In an embodiment of the present invention, the ECC module 100 separates the data bit and the check bit of the codeword and stores them in the memory 210 and 220 spaced apart from each other. The ECC module 100 may add parity bits for each of the data bits and the check bits of the codeword. Here, the parity scheme for each of the data bits and the check bits may apply odd parity or even parity.

The memory 200 may be, for example, a memory having few data bits read / written at one time, such as an SRAM or a DRAM. In addition, the memory 200 may be a next-generation memory such as MRAM, ReRAM, PRAM, or the like.

Referring to FIG. 2, the ECC module 100 will be described in detail. Referring to FIG. 2, the ECC module 100 includes a check bit generator 110, a syndrome generator 120, a decoder unit 130, and a modifier 140.

Data bits are stored in the data bit memory 210 during a write operation of the memory. Meanwhile, the check bit generator 110 generates a write check bit from the data bits and stores the write check bit in the check bit memory 220. The check bit generator 110 is designed by an H-matrix. The write check bit implies the characteristics of the input data bits.

During the read operation of the memory, the ECC module 100 receives the data bits and the write check bits stored in the memories 210 and 220. The check bit generator 110 reads data bits from the data bit memory 210 and generates read check bits therefrom. The syndrome generator 120 generates a syndrome using the read check bit thus generated and the write check bit generated during the write operation and stored in the check bit memory 220. If there are no errors in the stored data bits and the write check bits, the syndrome values are all "0". On the other hand, if there is an error in the stored data bit and the write check bit, the syndrome becomes the same value as the column value of the H-matrix at the corresponding bit position. Decoder unit 130 uses this syndrome to find the correct error bit position. The modifier 140 corrects the error by inverting the data in the write bit and the data bit at the position of the error bit found through the decoder unit 130.

The specific error correction method will be described through specific examples. Here, a description is given using (12, 8) codes as an example, and it is assumed that data bits are 0011 1001 8 bits and the generated codeword is composed of data bits and check bits in the following order.

For example, data bits and check bits are mixed together to form a codeword, but check bits may come first, followed by data bits, or vice versa, data bits may precede, check beak, or randomly Check bits may be mixed.

Meanwhile, the H-matrix for the (12, 8) code is as follows.

The check bit generator uses the data bits to form check bits, for example, generating four check bits C1, C2, C3 and C4 with the following operation.

Therefore, the write check bit generated by the check bit generator 110 of the ECC module 100 is

to be.

Accordingly, the generated codeword is 00 0 1 011 0 1001 (in bold, the check bit), and the data bit '0011 1001' and the write check bit '0010' are stored in the memories 210 and 2220, respectively.

Next, the error correction of the ECC module 100 will be described. The case where an error occurs in the fifth data bit '1' from data bit 0011 1001 is described. That is, the data bit read from the data bit memory 210 is '0011 0001' because an error occurs in the fifth bit.

The check bit generator 110 of the ECC module 100 generates the read check bits C1 ', C2', C3 ', and C4' as follows by using the above-described check bit generation operation from the read data bits '0011 0001'. do.

Here, the square box is the fifth data bit in which an error occurs.

An error occurs in the fifth data bit, so the write check bit '0010' and the read check bit '1011' are different from each other.

이다. 오류가 발생하지 않았다면 신드롬은 '0000'이 되지만, 5번째 데이터 비트에서 오류가 발생하여 신드롬이 '1001'이 되었다. The syndrome generator of the ECC module 100 generates a syndrome by calculating a write check bit and a read check bit into two modules. Syndrome is

to be. If no error occurred, the syndrome would be '0000', but an error occurred on the fifth data bit, resulting in a syndrome of '1001'.

Since the syndrome is '1001', it is the fifth column of the above-described column of the H-matrix. Therefore, it can be seen that an error has occurred in the fifth data bit.

The decoder unit 130 of the ECC module 100 uses a syndrome to find the error bit position and invert the bit at the position where the error occurred to correct the error. The decoder unit 130 includes as many decoders as the number of columns of the H-matrix, and each decoder may be a NAND gate that receives each element of the column of the corresponding H-matrix as an input.

Returning to the above example, since the H-matrix of the (12, 8) code is composed of four rows and twelve columns, the decoder unit is composed of twelve NAND gates having four inputs. 3 exemplarily shows a decoder corresponding to the fourth and fifth columns. The decoder receives an input of an element of a corresponding column of the H-matrix as an input, but inverted when it is '0'. If no error occurs, each decoder outputs '0' because the syndrome bits S01, S02, S03, and S04 are all '0'. However, in the above example, an error occurs in the fifth data bit, and the syndrome becomes '1001'. Therefore, only the decoder (the right decoder of FIG. 3) corresponding to the fifth column (the fifth data bit) outputs '0' and the remaining decoders output '1' (see the left decoder of FIG. 3). Thus, it is possible to detect that an error occurs in the fifth data bit.

Among the ECC modules, the portion of the ECC module that has the largest design and the most different design depending on the H-matrix is the check bit generator and decoder, whereas the syndrome generator and the modifier are designed identically regardless of the code.

Accordingly, an embodiment of the present invention provides an ECC module that can reduce an operation time of a check bit generator and can greatly reduce an area of a decoder unit.

Embodiments of the present invention relate to error correction of a memory. The (n, k) code is an error correcting code using code words consisting of n bits, and one code word is composed of k data bits and nk (= m) check bits. At this time, n becomes k + m. In a typical memory, the number k of data bits is 2 ^m-1 . The (n, k) single error correction code is represented by an (m × n) H-matrix, which is composed of m rows and n columns. In this case, n columns include k data bit strings and m check bit strings. On the other hand, a syndrome is composed of m bits, and a syndrome consisting of m bits can represent 2 ^m vectors.

However, the number of columns to be decoded in the H-matrix used in a general memory is n, that is, 2 ^m-1 + m. Thus, the decoder may have the number of inputs of the NAND gate decoding the column having the maximum column weight among the columns of the H-matrix to have a value less than m. This is possible because the number of columns the decoder has to decode is not 2 ^m , but less than 2 ^m-1 + m.

This is explained further.

Below is the H-matrix of exemplary (21, 16) code.

In this case, the decoder typically requires five inputs, the number of check bits (the number of syndrome bits), and 21 decoders, the number of columns, for single error correction. 4 shows decoders corresponding to the eighth and eleventh columns among them.

However, for single error correction, the number of decoders required is 21 rather than 2 ⁵ = 32. Thus, the number of inputs of a decoder for which every decoder decodes a column having the maximum column weight without having to have five inputs can be equal to the column weight of that column. FIG. 5 shows a new decoder of the present invention corresponding to the same decoder as the existing decoder corresponding to the eighth column having no maximum column weight and the eleventh column as the column having the maximum column weight.

Thus, while the decoding unit for the above (21, 16) code is conventionally composed of 21 five-input decoders, in the embodiment of the present invention, the maximum column weight preference decoder is used to decode 20 five to decode columns rather than the maximum column weight. It consists of an input decoder and one four input decoder to decode the column with the maximum column weight. On the other hand, in the case of the (12, 8) code described above, four columns and seven columns have a maximum column weight as a column weight of three, and the conventional decoder unit is composed of twelve four-input decoders, according to an embodiment of the present invention. It consists of ten four-input decoders and two three-input decoders.

The maximum column weight preference decoder may further reduce the area of the decoder as the number of columns having the maximum column weight in the H-matrix increases. Therefore, an embodiment of the present invention provides an H-matrix generation method that can maximize the reduction of the area of a decoder.

In creating an H-matrix, we maximize the number of columns with the maximum column weight possible, and make the number of inputs of the decoder for decoding the column with the maximum column weight equal to the column weight of the maximum column weight column. .

In this specification, an H-matrix having as many maximum column weights as possible according to the concept of the present invention as compared to a conventional H-matrix is referred to as a 'maximum-column-weight prioritizied H-matrix'. This can be mentioned. Similarly, a decoder operating on the basis of a maximum column weight preference H-matrix can be referred to as a 'maximum column weight preferred decoder'.

The maximum heat weight preference H-matrix satisfies the following conditions.

1) No column is a zero vector.

2) Each column has a different vector from the other columns.

3) Maximize the number of rows with the maximum column weight.

4) Each row weight is an integer close to the total weight of the matrix divided by the number of rows.

Constraints 1 and 2 are the same constraints as conventional Hamming code, and constraints 3 and 4 are the constraints first proposed by the inventors.

The maximum column weight preferred H-matrix generation condition 1 allows the syndrome to be a zero vector if no error exists.

The maximum column weight preference H-matrix generation condition 2 allows the column vector at the position of the bit where the error occurred to be equal to the vector value of the syndrome.

Maximum column weight preference H-matrix generation condition 3 can maximize the area reduction of the decoder when using the maximum column weight preference decoder.

Maximum Column Weight Preferred H-matrix generation condition 4 reduces the run time of the check bit generator by making the weights of all rows similar.

In an embodiment according to the inventive concept, condition 4 of the above conditions 1 to 4 for the maximum heat weight preferred H-matrix is optional.

Hereinafter, a method of generating a maximum column weight preference H-matrix according to an embodiment of the present invention will be described.

The above maximum column weight preferred H-matrix generation conditions 1 and 2 are well known to those skilled in the art and will not be described.

First, a method of obtaining the maximum heat weight according to the H-matrix generation condition 3 of the maximum heat weight preference will be described.

(2 ^m-1 + m, 2 ^m-1 ) Maximum heat weight To generate a single error correction code, the maximum heat weight must first be found. The maximum heat weight is given by Equation 1 below.

Where MCW is the maximum column weight and _m C _I is the number of columns that can have a column weight of I (I is 2, 3, ..., MCW) in the m H-matrix rows. Means.

Next, a method of maximizing the maximum number of column weights according to the maximum column weight preference H-matrix generation condition 3 will be described.

Once the maximum column weight of the H-matrix is determined, the maximum number of column weights in the H-matrix is maximized as permissible. To this end, in one embodiment according to the concept of the present invention, for example, the H-matrix is filled in the order of the heat weight of 2, 3, ..., MCW-2, MCW, MCW-1. That is, the column with the maximum column weight is not filled last in the H-matrix, but at least last second. After the column with the maximum column weight is filled, the remaining columns of the matrix (unfilled columns) are filled with columns smaller than the maximum column weight, for example MCW-1. At this time, the columns may be selected from the columns having the MCW-1 column weight so that the row weight of each row of the H-matrix is similar to satisfy the H-matrix generation condition 4.

More specifically, the generation of an H-matrix for the (71, 64) maximum column weight preference code of 71 codeword bits, 64 data bits, and 7 check bits will be described.

First, calculate the maximum heat weight according to <Equation 1> above, 2 ^7-1 (= 64) ≤ ₇ C ₂ + ₇ C _{3 + Since 7} C ₄ = 21 + 35 + 35, (71, 64) the maximum column weight is the maximum column weight of the H-matrix of the preferred single error correction code.

Thus, the H-matrix is first populated with rows of column weight 2 and columns of column weight 4 with MCW-2. Rows with a weight of 2 are 21 with ₇ C ₂ and rows with a weight of 4 are 35 with ₇ C ₄ . The remaining eight data bit columns of the H-matrix are filled with columns of column weight 3 with column weight MCE-1. Here, out of 35 columns with column weight 3, 8 columns satisfying the above constraint 4, i.e., each row weight becomes an integer 30 or 31 close to the total weight of the matrix divided by the number of rows. Can be selected.

One example of the H-matrix of the resulting (71, 64) maximum column weight preferred single error correction code is as follows.

The maximum heat weight preference H-matrix generation described above may be implemented as electronic hardware, computer software, or a combination of both. Whether such functionality is implemented as hardware or software depends on the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.

The software for generating maximum thermal weight preferred H-matrix is RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, register, hard disk, removable disk, CD-ROM, or any other form known in the art. May reside in a storage medium. One example storage medium may be coupled to the processor such that the processor may read information from and write information to the storage medium.

Hereinafter, the maximum column weight preferred single error correction code according to an embodiment of the present invention is compared with the existing hamming code. For comparison, we assume that the proposed single error junk code and Hamming code use 64, 128, and 256 data bits. For simplicity, the check bit generator, syndrome generator, and modifier are implemented using only two input exclusive-or (XOR2) gates, and the decoder is implemented with an inverter, two input or three input NAND gate, and a NOR gate. In order to reduce one stage of the XOR2 gate, the check bit generator and the syndrome gate are implemented as one XOR gate tree.

Table 1 below shows the number of columns with all the weights in the H-matrix, the maximum row weight, MRW (maximum row weight), and the maximum column weight (MCW) of the existing Hamming code and the proposed maximum column weight preferred single error correction code. .

Data bits Code types Total weight in H-matrix Max row weight Maximum number of heat weights 64 bit Existing Hamming Code 212 36 One Invention code 213 31 35 128 bit
Original Hamming Code 470 68 One Invention code 434 55 70 256 bit Original Hamming Code 1049 133 One Invention code 1003 112 126

Looking at Table 1 above, it can be seen that the code of the present invention has a relatively small total weight in the matrix compared to the existing Hamming code. Less weight in the H-matrix means that the area burden of the error correction code execution circuitry is reduced.

In addition, the code of the present invention has a much higher maximum number of heat weights than the conventional hamming code. By greatly increasing the number of columns having the maximum column weight, the area reduction effect of the maximum column weight preferred decoder can be maximized.

In addition, the stage L of the check bit generator and the XOR2 gate tree of the syndrome gate, which are implemented as one of the longest operating time of the error correction code execution circuit, may be obtained by Equation 2 below.

Where [X] is the smallest integer not less than X.

As a result, it was confirmed that the number of stages of the XOR2 gate tree of the proposed maximum column weight single error correction code can be reduced by one stage in all data bits compared to the Hamming code.

FIG. 6 illustrates a comparison of the number of transistors used in an error correction code performing circuit using a maximum column weight preferred single error correction code using a maximum column weight preferred decoder and a conventional hamming code according to an embodiment of the present invention.

In the check bit generator and the syndrome generator implemented as one, the maximum column weight preferred single error correction code according to an embodiment of the present invention is 64, 128, and 256 data bits when used in one codeword. The transistor count increased by 0.5%, and the transistor count decreased by 7.8% and 4.5%.

In addition, the maximum column weight preferred single error correction code in the decoder has reduced transistor counts by 28.3%, 32.7% and 26.7%, respectively, when 64, 128 and 256 data bits are used in one codeword.

Therefore, in the full error correction code execution circuit, the maximum column weight preferred single error correction code reduced transistor counts by 10.6%, 16.1%, and 11.8%, respectively, when 64, 128, and 256 data bits were used in one codeword. .

In the present invention as described above has been described by the specific embodiments, such as specific components and limited embodiments and drawings, but this is provided to help a more general understanding of the present invention, the present invention is not limited to the above embodiments. For those skilled in the art, various modifications and variations are possible from these descriptions.

Therefore, the spirit of the present invention should not be limited to the described embodiments, and all the things that are equivalent to or equivalent to the scope of the claims as well as the following claims will belong to the scope of the present invention.

100: ECC module
200: memory
110: check bit generator
120: syndrome generator
130: decoding unit
140: modifier
210: data bit memory
220: check bit memory

Claims (12)

A decoder unit for a (n, k) error correction code,
The decoder unit comprises a plurality of decoders receiving different numbers of inputs, wherein at least one of the plurality of decoders has an input equal to the column weight of the column having the maximum column weight of the H-matrix. The method according to claim 1,
The decoder unit comprises at least one first decoder having (nk) inputs and at least one second decoder having inputs smaller than (nk). The method of claim 2,
And a number of inputs of the second decoder is equal to the maximum column weight. A check bit generator for generating a write check bit from the received message data (k bits) and a read check bit (m bits) from the received and stored message data;
A syndrome generator for calculating a syndrome from the read check bit and the write check bit; And,
A decoder unit for detecting an error as an input of an output of the syndrome generator,
And the decoder unit comprises a plurality of decoders receiving different numbers of inputs, wherein at least one of the plurality of decoders has an input equal to a column weight of a column having a maximum column weight of an H-matrix. 5. The method of claim 4,
at least one first decoder having (m) inputs and at least one second decoder having inputs smaller than (m). 6. The method of claim 5,
And an input number of the second decoder is equal to the maximum column weight. A decoder unit for a (n, k) error correction code,
The decoder unit includes n decoders corresponding to the number n of columns of the H-matrix, and the decoder corresponding to the column having the maximum column weight of the H-matrix has an input equal to the maximum column weight. Decoder unit. H-matrix generation method for error correction code,
Generating an H-matrix that satisfies a first condition without all zero columns, a second condition in which each column is distinguished from all other columns, and a third condition maximizing the number of columns having a maximum column weight;
H-matrix generation method comprising a. The method of claim 8, wherein generating the H-matrix
And generating a H-matrix so as to further satisfy a fourth condition in which each row weight of the generated H-matrix is an integer close to the total weight of the matrix divided by the number of rows. The method of claim 8,
H-matrix generation method of filling columns in the order of 2, 3, MCW-2, MCW, MCW-1. A computer-readable recording medium storing a program for performing the method of any one of claims 8 to 10. An error correction code module for detecting and correcting an error of a received codeword by using the H-matrix generated by the H-matrix generation method of any one of the methods of claims 8 to 10 as a parity check matrix.

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