JPS5851354A - Program control circuit - Google Patents

Abstract

PURPOSE:To eliminate a waste of instruction execution and to realize high-speed control by adding a rereading circuit which operates on the basis of jump addresses in addition to a integrated logical circuit. CONSTITUTION:By an instruction, a specific bit in a holding circuit 4 is selected by a selector 5, whose selection result is regarded as a test result to obtain a control signal to an address switching indication terminal P3 and a selector 3. When the output of the terminal P3 arrives, a selector 10 switches the output of a holding circuit 11 and the output of a program memory II to send it from an instruction input terminal P2 to an instruction register 6. The value of a jump address field of the output of the selector is written in a holding circuit 12. A selector 3 selects a jump address and the result of addition by a +1 adding circuit 2 is stored in an address register 1, thereby sending an instruction address P1 out of the integrated logical circuit

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a program control circuit that is capable of increasing the speed of an integrated logic circuit that operates under program control and in which instructions are supplied externally.

Conventionally, in this type of device, a logic operation is performed inside an integrated logic circuit as shown in FIG. The instruction was read by determining whether to add 1 to the previous instruction address or to make it a negative address, and sending the address to an externally attached program memory. In general, the internal logic operations of integrated logic circuits are extremely fast, but when a signal is sent out of the integrated logic circuit, a large amount of energy must be extracted, resulting in a large delay in signal propagation. Therefore, if the instruction is read after determining whether it is the +1 address or the jump destination address at timing Ta in Figure 2 (A), the instruction will be read out at T1 in Figure 2 (A), and the next cannot meet the instruction execution time of
Generally, as shown in Figure 2 (b), before determining whether it is address K, +1, or the jump destination address, address +1 is presumed to be the next instruction and read out (during period Ca). If is the jump destination address, read the jump destination instruction (in the period of C84), make the next instruction ineffective, pause the execution time of one instruction in Mb cycle, and then stop the execution of the instruction at the jump address. It takes the form of a cycle of In this case, when controlling an external device that runs on its own using an autonomous clock, such as a communication control device or a file storage device, there is a problem that the probability of abnormalities such as overruns increases.

In order to eliminate this drawback, the present invention provides a circuit that reads and stores an instruction at an incremented address outside the integrated logic circuit, and a circuit that reads an instruction at an address specified in the jump address field of the instruction. The present invention is characterized in that two instructions are read out within the integrated logic circuit, and the instructions are sent to the integrated logic circuit in accordance with a signal indicating the test result from the integrated logic circuit.

FIG. 3 shows an embodiment of the present invention, and FIG. 4 is an operation time chart in the embodiment of the present invention. It is now assumed that the controlled circuit 7 is controlled by the command read into the instruction register 6, and the state of the controlled circuit 7 is stored in the holding circuit 4. Furthermore, this instruction selects a specific bit in the holding circuit 4 with the selector 5, and uses the selection result as a test result and as an address switching instruction terminal P3 and a selector 30 control signal.

In FIG. 4, the instructions are executed sequentially as Ma+Mbm Me, but in the instruction execution cycle Ma, M
From the first time of a, the instruction is stored in the holding circuit 1 from the program memo 'Jl' via the selector 8 according to the contents of the external holding circuit 12 (corresponding to the address field of the microinstruction being executed) by the time of Tl. Read out. Thereafter, the address next to the currently executed instruction is sent from the holding circuit 1 to the program memory 1 via the program address output terminal P. To switch between the two, selector 8
done by. It is assumed that the selector 8 switches the address input according to the timing, as shown in t1 and t2 in FIG. 4, by the timing generation circuit 9. Further, when the output of the address switching instruction terminal P3 arrives, the selector 10 switches between the output of the holding circuit 11 and the output of the program memory 2 and sends it to the instruction register 6° via the instruction input terminal P2. At the same time, the value of the jump address field among the outputs of the selector is written into the holding circuit 12. On the other hand, when the jump is established, the selector 3 selects the jump address, performs +1 addition by the +1 addition circuit 2, stores the result in the address register 1, and sends the instruction address P1 to the outside of the integrated logic circuit. The above operations are repeated as Ma, Ml) and Me.

In addition, if the circuit of the voice A is placed outside the integrated logic circuit, the output of the address register 1 becomes the address output terminal P1.
This eliminates the time it takes for the data to reach the outside via t, which can shorten the time, and this margin time t- can be utilized to use a memory element whose access time is slower than t. In this case, the jump address input to the selector 3 uses the output of the holding circuit 12, but the operation is the same as described above. In this case, it is not necessary to send the signal corresponding to the jump address field into the integrated logic circuit, so that the terminals of the integrated logic circuit can be saved.

As explained above, the present invention adds a rereading circuit based on the N/P address outside the integrated logic circuit, so that the present invention is different from the conventional method in which an instruction is read into the integrated logic circuit and the address is output again. This has the advantage of eliminating wasteful execution and increasing speed.

[Brief explanation of drawings]

FIG. 1 shows a circuit according to the prior art, FIG. 2 shows an instruction execution time chart for explaining its operation, FIG. 3 shows an embodiment of the present invention, and FIG. 4 shows its time chart. ■・・・・・・Integrated logic circuit, ■・・・・・・
・・・・・・Program memory, l ・・・・・・・・・Address register, 2・・・・・・・・・+1 addition circuit, 3・・・・・・・Selector, 4・・・・・・Pa internal state holding circuit, 5...Selector, 6
・・・・・・・・・Instruction register, 7・・・・・・・・・
・Controlled circuit, 8...Selector, 9
......timing generation circuit, 10...
...Selector, 11...Instruction holding circuit, Ma+ Ml), Mg, -, ,,,
,,,Instruction execution cycle, Can ca'... Song instruction read cycle, 'ra......Test result judgment timing during instruction execution cycle, P
1. P2+P3...Signal terminal. Figure 1 Figure 2 Figure 4

Claims (2)

[Claims] (1) In a program-controlled integrated logic circuit that inputs an instruction from a terminal and executes the instruction, the integrated logic circuit determines whether the next instruction to be executed is the instruction at the next address of the instruction currently being executed, or whether the instruction is currently being executed. Equipped with an address switching instruction terminal that sends a signal specifying whether the instruction is at the address specified in the jump address field of the instruction, a program address output terminal that outputs an address that is +1 to the address of the currently executing instruction, and an instruction input terminal. and a jump address holding circuit that holds a jump address field of an instruction input to the integrated logic circuit independently of the integrated logic circuit; One of the addresses from the address output terminal is selected and the first instruction is read using the selected address, and during the second period, the other address is selected and the second instruction is read using the selected address. an instruction holding circuit that holds the read instruction; and an instruction holding circuit that selects one of the first and second instructions according to a signal from the address switching instruction terminal, and A program control circuit characterized by comprising two means for sending data to an input terminal. (2) In a program-controlled integrated logic circuit that inputs an instruction from a terminal and executes the instruction, the integrated logic circuit determines whether the next instruction to be executed is the one at the next address of the instruction currently being executed, or whether the instruction is currently being executed. It is equipped with an address switching instruction terminal that sends a signal specifying whether the instruction is at the address specified in the jump address field of the instruction, and independently of the integrated logic circuit, When specifying the instruction at the next address, the next address of the currently executing instruction is held, and if the instruction signal specifies the instruction at the address specified in the jump address field of the currently executing instruction, the currently executing instruction is a next address holding circuit that holds an address next to the address specified in the jump address field of the instruction in the integrated logic circuit; a jump address holding circuit that holds the jump address field of the instruction input to the integrated logic circuit; selecting either the address held in the jump address holding circuit or the address from the next address holding circuit during the period;
means for reading the second instruction according to the selected address, selecting the other address in a second period, and reading the second instruction according to the selected address; an instruction holding circuit that holds a first instruction; and a command holding circuit that holds a first instruction;
and means for selecting one of the second instructions and sending it to the instruction hexagonal child.