JP2001319477A - Semiconductor memory and memory control method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable a samiconductor memory simultaneous to designate write-in to and read-out from the same address, in a semiconductor memory having addresses and data terminals for write-in and read-out respectively. SOLUTION: This device has registers 102-105 connected in series for addresses and data on the write-in side of a memory circuit 101 and registers 109, 114 for addresses and data of a read-out side, write-in data is written in the memory circuit 101 after 2 clock cycles, read-out data is read out from the memory circuit 101 after 1 clock cycle, access for the same address for the memory circuit 101 is detected by a coincidence detecting circuit 110, data of the second register 105 for write-in data is made read-out data instead of read-out data from the memory circuit 101.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device having address and data signal lines for writing and reading, respectively, and a memory control method.

[0002]

2. Description of the Related Art A semiconductor memory device having an input / output port on each of a write side and a read side and writing and reading data in synchronization with a clock is known in the structure shown in FIG.

In FIG. 6, reference numeral 601 denotes a memory circuit;
2 is a write address register, 603 is a write data register, 604 is a write enable register that specifies memory writing, 605 is a chip select register, 606 is a read address register, 6
07 is a read enable register for designating memory read, and 608 is a read data register.

Hereinafter, the operation of the semiconductor memory device having the above configuration will be described. On the memory write side, the write address and the write data are latched by the write address register 602 and the write data register 603 at the rising edge of the clock, respectively, and are written into the memory cells of the memory circuit addressed by the write address register 602. Write data register 6
03 is written. On the memory read side, the read address is latched by the read address register 606 at the rising edge of the clock, the contents of the memory cell of the memory circuit 601 specified by the read address register are read, and the read data register 608 is read. And output to the outside.

[0005]

However, in the above conventional configuration, when writing and reading to the same address are specified at the same time, data is written during reading, and the contents of the read data are not guaranteed. Therefore, it has been prohibited to simultaneously designate writing and reading for the same address.

An object of the present invention is to provide a semiconductor memory device and a memory control method which enable simultaneous designation of writing and reading to the same address and which are not restricted by use. With the goal.

[0007]

A semiconductor memory device according to the present invention has a write address signal line, a write data signal line and a write control signal line on a write side, and a read address signal line and a read data signal line on a read side. And a memory circuit having a read control signal line, a write address register connected to the write address signal line and holding an externally supplied write address for two clock cycles, and an externally connected write data signal line. The supplied write data is
A write data register that holds only the clock cycle time, a write control register that is connected to the write control signal line and holds an externally supplied write control signal for the two clock cycle time, and a read address signal line A read address register for holding a read address supplied from outside for only one clock cycle time, a read data register connected to the read data signal line and holding read data from a memory circuit, and a read control signal line And a read control register for holding a read control signal supplied from the outside for the one clock cycle time.

A semiconductor memory device according to claim 2, wherein a match detection circuit for detecting a match between the output of the write address register and the output of the read address register, and the memory based on an output of the match detection circuit. A selection circuit for selecting read data from the circuit and an output of the write data register and inputting the input to the read data register, wherein when the match detection circuit detects a match, the write data When the match is not detected by the match detection circuit, the data read from the memory circuit is selected.

According to the memory control method of the present invention, externally supplied write data is written to a cell in a memory circuit specified by a write address, and read data written to a cell in the memory circuit is specified by a read address. Latching the write address and the write data for a plurality of clock cycles, latching the read address and the read data for a clock cycle shorter than the plurality of clock cycles, and latching the write address. Detecting a match between the output that has been latched and the output that has latched the read address; and outputting the write data when the match is detected, and outputting the write data when the match is not detected. And a step of outputting the read data from.

According to the semiconductor memory device of the present invention, the time latched in the register (write address register, write data register, write control register) related to the write operation corresponds to the register related to the read operation (read address register). (Register, read data register, read control register) is longer by one clock, so that writing of data to the memory circuit is delayed by one clock cycle from reading of data. Therefore, even when writing and reading for the same address are specified at the same time, simultaneous access to the specified memory cell is avoided, and the contents of the read data are guaranteed.

According to the semiconductor memory device of the present invention, the output of the write address register and the output of the read address register are compared by the coincidence detecting circuit. The output of the register is selected. Therefore, the contents of the read data are guaranteed even during writing to the cell in the designated memory circuit.

[0012]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a configuration of a semiconductor memory device according to an embodiment of the present invention. In FIG. 1, 101 is a memory circuit, 102 is a first write address register connected to a write address signal line and latching write address data for one clock cycle, and 103 is further latching write address data for one clock cycle. A second write address register 104 is a first write data register that latches write data for one clock cycle.
Reference numeral 5 denotes a second write data register for latching write data for another clock cycle, reference numeral 106 denotes a write control AND circuit, reference numeral 107 denotes a first write control register for latching write control data for one clock cycle, reference numeral 108 Is a second write control register for latching write control data for one clock cycle, 109 is a read address register for latching read address data for one clock cycle, 110
Is a match detection circuit for detecting a match between the output of the second write address register 103 and the output of the read address register 109; 111 is a read control AND circuit; 112 is the output of the read control AND circuit 111 ( A read control register for latching read control data) for one clock cycle;
A selection circuit that selects the read data from the memory circuit 101 and the output of the second write data register 105 based on the output of the selector 10, and a read data register 114 that latches the output of the selection circuit 113 for one clock cycle. is there. The memory circuit 110 writes the write data input to the write data input unit to the cell specified by the write address input to the write address decoder based on the write instruction from the write control circuit, and reads the read instruction from the read control circuit. On the basis of the,
The read data is output from the cell specified by the read address input to the read address decoder via the read data output unit.

The operation of the semiconductor memory device according to the embodiment will be described below. (Operation 1 of Embodiment) The operation of the semiconductor memory device shown in FIG. 1 will be described with reference to a time chart shown in FIG. 2 and a flowchart shown in FIG.

When the write enable and the write chip select (write control signal) are “H” and the read enable and the read chip select (read control signal) are “H”, on the write side, at the rising edge of the clock in cycle 1, , The write address “A1” is latched in the first write address register 102, and the first write data register 1
At 04, the write data “D [A1]” is latched.
On the read side, the address “A1” is latched in the read address register 109 at the rising edge of the clock in cycle 1. Further, the output “A1” of the read address register 109 is output to the memory circuit 10
1 and the memory circuit 101 reads out the read data “D
[A1-1] ”is output.

Next, at the rising edge of the clock in cycle 2, on the write side, the address "A1" is latched in the second write address register 103,
The data “D” is stored in the second write data register 105.
[A1] ”is latched. At the rising edge of the clock in cycle 2, on the read side, the read data register 114 latches the read data“ D [A1-1] ”of the memory circuit 101 and externally. Then, the second write address register 103 is output.
Is output to the write address of the memory circuit 101 and the second write data register 105
Is output to the write data of the memory circuit 101, and the memory write is performed.

As a result, writing of the data "D [A1]" to the address "A1" is performed by the same address "A1".
Despite being specified at the same time as reading data, writing data to the memory circuit is one
The read data “D [A1
-1] "is correctly read.

(Operation 2 of Embodiment) The operation of the semiconductor memory device shown in FIG. 1 will be described with reference to a time chart shown in FIG. 3 and a flowchart shown in FIG.

When the write enable is “H” and the write chip select is “H”, the write address “A” is written into the first write address register 102 at the rising edge of the clock in cycle 1 on the write side.
1 "is latched, and the write data" D [A1] "is similarly latched in the first write data register 104.

Next, at the rising edge of the clock in cycle 2, the address "A1" is latched in the second write address register 103, and the data "D [A1]" is latched in the second write data register 105. Is done. On the read side, in cycle 1, the address “A
When a read for "1" is instructed and the read enable becomes "H" and the read chip select becomes "H",
At the rising edge of the clock in cycle 2, the address “A1” is latched in the read address register 109.

At this time, since the output of the second write address register 103 matches the output of the read address register 109, the match detection circuit 110 outputs "H", and the selection circuit 113 outputs the second write data. The output of the register 105 is selected. At the rising edge of the clock in cycle 3, the read data register 114 stores the data “D” output from the selection circuit 113 in cycle 2
[A1] ”is latched and output to the outside. Further, write data“ D [A1] ”is written to the write address“ A1 ”of the memory circuit 101.

As a result, writing of the data "D [A1]" to the address "A1" is performed by the same address "A1".
The data held in the write data register is directly converted into the read data without passing through the memory circuit, even though the data is executed in the memory circuit at the same time as the read operation for the read data “D [A1]”. Is read correctly.

[0022]

As described above, by making the time latched by the register relating to the write operation longer by one clock than the time latched by the register relating to the read operation, data writing to the memory circuit can be performed. One clock cycle can be delayed from data reading. Therefore, even when writing and reading to the same address are specified at the same time, simultaneous access to the specified memory cell is avoided and data contents are guaranteed, so that writing and reading to the same address are specified at the same time. It becomes possible.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is a timing chart illustrating an operation of the semiconductor memory device according to the embodiment of the present invention.

FIG. 3 is a timing chart illustrating an operation of the semiconductor memory device according to the embodiment of the present invention.

FIG. 4 is a flowchart illustrating an operation of the semiconductor memory device according to the embodiment of the present invention.

FIG. 5 is a flowchart illustrating an operation of the semiconductor memory device according to the embodiment of the present invention.

FIG. 6 is a configuration diagram of a conventional semiconductor memory device.

[Explanation of symbols]

Reference Signs List 101 memory circuit 102 first write address register (write address register) 103 second write address register (write address register) 104 first write data register (write data register) 105 second write Data register (write data register) 106 Write control AND circuit 107 First write control register (write control register) 108 Second write control register (write control register) 109 Read address register 110 Match detection circuit 111 Read control AND circuit 112 Read control register 113 Selection circuit 114 Read data register

Claims (3)

[Claims] A write address signal line on a write side;
Having a write data signal line and a write control signal line,
A memory circuit having a read address signal line, a read data signal line, and a read control signal line on the read side; and a write address register connected to the write address signal line and holding an externally supplied write address for two clock cycle times A write data register connected to the write data signal line and holding externally supplied write data for the two clock cycle time; and a write control signal connected to the write control signal line and supplied from the outside. A write control register for holding for two clock cycle times, a read address register connected to the read address signal line for holding an externally supplied read address for one clock cycle time, and a read data signal line A read data register that is connected to hold read data from the memory circuit; and a read control register that is connected to the read control signal line and holds an externally supplied read control signal for the one clock cycle time. Semiconductor storage device. 2. A match detection circuit for detecting a match between an output of the write address register and an output of the read address register; and read data from the memory circuit and the write based on an output of the match detection circuit. A selection circuit for selecting an output of the data register and an input of the read data register, and when a match is detected by the match detection circuit, selecting the output of the write data register. 2. The semiconductor memory device according to claim 1, wherein when a match is not detected by the match detection circuit, data read from the memory circuit is selected. 3. A memory control method for writing externally supplied write data to a cell in a memory circuit specified by a write address and reading read data written in a cell in the memory circuit by specifying a read address. A step of latching the write address and the write data for a plurality of clock cycles; a step of latching the read address and the read data for a clock cycle shorter than the plurality of clock cycles; an output latching the write address and the read address; Detecting the coincidence with the output latched, outputting the write data when the coincidence is detected, and reading the data from the memory circuit corresponding to the read address when the coincidence is not detected. Memory control method and a step of outputting.