JPS5846175B2 - programmable circuit - Google Patents

Abstract

PURPOSE:To improve the yield rate of C-MOS super LSIs by a method wherein a pulse driven MOS switching element maintains the level of voltages in response to fuse element conditions as to whether it is open or closed for the reduction of current to be consumed in detecting such fuse element conditions. CONSTITUTION:One end of a fuse element F is connected to a first power source VSS, and an MOS switching element T1 is connected between the other end of the fuse F and a second power source VCC. A pulse signal applying circuit 11 outputs pulse signals to energize and drive the switching element T1 to determine potentials at the junction point Q according to the condition of the fuse element F that is either an open state or a closed state. A potential maintaining circuit 12 maintains the potential set at the junction point Q and supplies to an address buffer circuit 20 an output dependent on the fuse element F condition. This construction provides a battery backup for a faulty C-MOS redressing means, which improves the yield rate of C-MOS super LSIs provided with a faulty product redressing circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a programmable circuit for repairing defects in MOS-LSIs such as CMOS memories.

As the integration density of MOS-LSI increases and the chip size increases, it has become difficult for all the elements integrated on one chip to operate without defects.

For example, in the Memo IJ LSI, as the density increases from 64 bits to 256 bits to 1M bits, the yield of chips that operate on all bits is expected to continue to decline, and this is a problem that hinders the increase in capacity. This is a close-up.

What appeared as a means to solve this problem was a defect relief means equipped with a defective address storage circuit.
It has already begun to be put into practical use with OS memory and JLSI.

This defect relief means provides spare memory rows and row decoders or memory columns and column decoders in the matrix memory array of the MOS memory IJ LSI, and if there is a defective bit in the matrix memory array, the defective bit is removed. The row or column containing the memory is replaced with the spare memory row, row decoder, memory column, or column decoder for relief.

In this case, a fuse element is used in the defective address storage circuit, and the address of the defective bit is stored depending on the greasing state (two states, connected state and disconnected state) of this fuse element, and the address of the defective bit is selected. At this time, the spare row decoder or column decoder is selected to use the spare row or column, and the selection of the row or column containing the defective bit is prohibited.

FIG. 1 shows this type of conventional defective address storage circuit, where Xi and Xi are address signal inputs, P is a program (write) input, and Xpt is an address signal selection output.

When the fuse element F is not disconnected, the node Q is at the power supply Vcc potential (for example, 5V), the output of the transistor T1 is O, the output of the on-chip inverter is O, the transistor T2 is off, and the address signal input Xi is at the address It is derived as a signal selection output Xpi.

On the other hand, when the programming power P is set to O■ during programming, the transistor T3 is turned off, the transistor T4 is turned off if the address signal Xi is Ov, and turned on if Xi is at the Vcc potential.

When this transistor T4 is off, the potential of the program power supply vpp (for example, +
10V) is applied, the transistor T6 is turned on,
A fusing current flows through the fuse element F, and the fuse element F is cut off.

Therefore, when the fuse element F is in the disconnected state, the node Q becomes Ov, the transistor T1 is turned off, and the transistor T2 is turned on, so that the address signal input signal Xi is derived as the address signal selection output Xpi.

That is, the defective address storage circuit stores the address signal input Xi or Xi as an address depending on whether a defective address is written in the fuse element F, that is, whether the fuse element F is disconnected or connected. It is derived as the signal output Xpi.

However, in the above-described defective address storage circuit of FIG. A depletion type transistor T7 is connected as an element, and therefore, when the fuse element F is in a connected state, a direct current consumption occurs through the series circuit of the fuse element F and the transistor T7.

This current consumption is not a problem in the case of N-channel MOS memory, which has a finite standby current, but in the case of N-channel MOS memory, which has a finite standby current,
In the case of MOS memory, this cannot be ignored.

In particular, in a battery-backed CMOS memory, it is necessary to suppress standby current consumption to about 1 μA to several tens of μA, and in this respect, it has been difficult to provide a defect relief means.

The present invention was made in view of the above circumstances, and
A circuit in which a MOS switch element is connected in series with a fuse element to repair a defective circuit part in a MOS-LSI circuit such as, and this switch element is pulse-driven to obtain and hold a voltage according to the greasing state of the fuse element. By adopting this configuration, it is possible to reduce the current consumption for detecting the greasy state of the fuse element, and it is possible to use battery backup as a means of remediating CMOS memory defects, and it is programmable, which makes it possible to realize CMOS VLSI with high yield. It provides a circuit.

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings, taking a CMOS memory as an example.

FIG. 2 shows a defective address storage circuit 10, an address buffer circuit 20, and a program circuit 30, which are part of the peripheral circuits of a CMOS memory.

In the defective address storage circuit 10, one end of the fuse element F is connected to a first power supply Vss (in this example, the ground terminal as a reference potential), and the other end (node Q in the figure) is connected to a second power supply (in this example, a 5V voltage). Vcc), a P-channel transistor T1 is connected as a MOS switch element.

Reference numeral 11 applies, for example, a pulse signal synchronized with a change in the address signal input to the gate of the transistor T1 to drive it into conduction, and changes the potential of the connection node Q between the transistor T1 and the fuse element F to the greasy state of the fuse element F. This is a pulse signal application circuit that is set according to the

The node Q is connected to the input terminal of the inverter 1 and the source of the P-channel transistor T2, the drain of which is connected to the power supply Vcc, and the gate connected to the output terminal of the inverter 1.

That is, the above inverter (1) and transistor T2
constitutes a potential holding circuit 12 that holds the potential set at the node Q, generates an output according to the greasing state of the fuse element F, and supplies it to the address buffer circuit 20.

On the other hand, in the address buffer circuit 20, the potential holding output supplied from the defective address storage circuit 10 is connected to the inverter 2 and the P channel transistor T3. It is led to each gate of N-channel transistor T4.

An N-channel transistor T5 is connected in parallel to the P-channel transistor T3, and a P-channel transistor T is connected in parallel to the N-channel transistor T4.
6 is connected.

The transistor T5. The output of the inverter (2) is supplied to each gate of T6, and the parallel transistors T3. Transistor T4. in parallel with T5. T6 is connected in series, and the address signal Ai is input to one end of this series circuit, and the address signal Ai is input to the other end.

That is, the inverter (2) and the four transistors T3, T4, T5, To receive the address signal A by the output potential of the defective address storage circuit 10.
i, Ai, and connect the parallel transistors T3. A switch circuit 21 is configured to output a defect relief address signal selection output Xi from a connection node between T5 and the parallel transistors T, , T6.

Note that the inverters ■3 + I4 t I5 and I6 are connected in cascade, and the address input signal PAi (i20 = n
) constitutes an address drive circuit 22 which receives the address signals Ai and outputs the address signals Ai and Ai.

On the other hand, in the program circuit 30, the P-channel transistor T7 for program control and the P-channel transistor T8 for defective address designation are connected in parallel, their sources are connected to the power supply Vcc, and their drains are connected via the load element 31 for programming. Connected to power supply vpp.

The program control input signal PR is applied to the gate of the transistor T7, and the inverter 1 of the address buffer circuit 20 is applied to the gate of the transistor T8.
4 output is applied.

And these transistors T7. The gate of a P-channel transistor T9 for programming is connected to the connection node P between the drain of T8 and the load element 31, the source of this transistor T is connected to the power supply Vcc, and the drain is connected to the connection node P of the defective address storage circuit 10. Connected to node Q.

Next, the operation of FIG. 2 in the above configuration will be explained with reference to the timing diagram of FIG. 3.

First, in the program mode, the address input signal P
As Ai, set the address containing the defective pit to high 0 level (e.g. +5V) or low (L) level (e.g. O■)
Specified by.

In this state, at time t1 the program power supply VpT)
is set from a high level to a negative voltage program level Vp (for example, -10V).

Next, at time t2, the program control input signal PR
is changed from a low level to a high level to turn off the program control transistor T7.

At this time, since a signal of the same logic level as the address input signal PAi is applied to the gate of the defective addressing transistor T8 from the inverter 4, the
If Ai is at a high level, it is off, and if it is at a low level, it is on.

Therefore, the potential at the node P becomes the negative voltage program level Vp when the transistor T8 is off (PAi is at a high level), and remains at a high level (power supply Vcc level) when the transistor T8 is on (PAi is at a low level). will be done.

When the potential of this node P is at the negative voltage program level Vp, the programming transistor T is driven to a large current of about 10 mA, and the fuse element F is blown out to perform program writing.

Conversely, when the potential at the node P is at a high level, the programming transistor T.

is off, fuse element F is not turned on, and no program writing is performed.

Next, at time t3, the program control input signal PR
By returning the program control transistor T7 from a high level to a low level, the program control transistor T7 is turned back on.) The potential at the node P is forced to a high level via the transistor T7.

Therefore, the programming transistor T, returns to the off state, and then the programming mode is terminated by returning the programming power supply Vl)I) to the Vcc level (high level).

Next, the operation of generating the defect relief address signal selection output Xi will be explained.

After the program mode described above, the circuit of FIG.
Generally, cc is temporarily cut off.

This is because programming for defect relief is generally performed when chips are sorted on a wafer, and then the chips are cut out from the wafer and mounted in a package.

Of course, in rare cases, it is possible to write a program after mounting to repair defective bits, but even in this case, the power supply Vcc may be cut off.

Assume that the power supply Vcc is cut off at time t5, and then turned on again at time t6.

Further, it is assumed that the pulse signal application circuit 11 of FIG. 2 generates a pulse signal R synchronized with changes in the address signal using an address displacement detector 41 and an inverter 42, as shown in FIG. 4a, for example.

Note that this pulse signal R is an address input signal A as shown in FIG.

It becomes low level for a certain period τ in synchronization with a change in any signal Ai in -An.

When the power supply Vcc is turned on at time t6, the potential at the node Q of the defective address storage circuit 10 immediately becomes a low level if the fuse element F is in a connected state, but becomes a high level or a low level if the fuse element F is in a disconnected state after blowing out. level, the potential remains indeterminate.

Next, at time t7, address input signal A is input.

When any signal Ai among ~An changes, Fig. 4a
The address transition detector operates to cause the pulse signal application circuit 10 to generate a synchronization pulse R that is at a low level between times t7 and t8.

This synchronizing pulse R is the memory read transistor T1.
conducts, thereby changing the potential at node Q to fuse element F
It is set to a low level if it is in a connected state, and to a high level if it is in a disconnected state after blowing out, that is, it is uniquely set according to the greasing state of the fuse element F.

Once the potential of the node Q is set to a high level, the output of the inverter 1 of the memory holding circuit 12 becomes a low level and the transistor T2 is turned on, so that the high level state of the node Q is maintained. It becomes like this.

In this way, the address input signal A is generated in the same manner from now on.

-An at time t in synchronization with any change in An. ~tlO, the synchronizing pulse R becomes low level between times 111 and t12, temporarily making the memory read transistor T1 conductive, and the node Q is always set at a potential according to the greasing state of the fuse element F. Therefore, the information stored in the fuse element F can be read out correctly.

As a result of the reading described above, when the node Q is at a high level, the output of the inverter 11 becomes a low level, and in the switch circuit 21, the output of the transistor T3. T.

conducts, transistor T4. Since T6 becomes non-conductive, address signal Ai is derived as defective relief address signal selection output Xi.

On the other hand, when the node Q is at a low level, the output of the inverter (1) becomes a high level, transistors T, , T6 in the switch circuit 21 become conductive, and transistors T3, .
Since T5 becomes non-conductive, address signal Ai is derived as the output Xi.

As mentioned above, the defective address storage circuit 10 of FIG.
A memory/read transistor T1 is connected in series to the fuse element F, and this transistor T1 is connected to the address input signal A.
.

−The fuse element F is driven in pulses in synchronization with the changes in An.
The voltage is obtained according to the greasing condition of the

Therefore, the address input signal A.

Although there is a possibility that a current flows through the transistor T1 when -An changes, the address input signal A.

When -An remains unchanged, that is, in a standby state, no current flows through the transistor T1, and the characteristics of the CMO8 circuit are not lost.

In addition, the inverter ■3 + of the address buffer circuit 20
I4゜I3. Similarly to the above, no current flows in I6 in the standby state.

Therefore, if the circuit shown in FIG. 2 is adopted, it becomes possible to provide battery backup for the CMO8 defect relief means, and it becomes possible to realize a CMO8 super LSI with a defect relief circuit at a high yield.

In addition, in the above embodiment, since the stored information of the fuse element is always read out to the node Q in synchronization with changes in the address input signal, there is little risk that this readout output will be lost due to power supply noise. strong against

Furthermore, even if the blown fuse element F is accompanied by leakage current, the potential of the node Q can be uniquely set and maintained by the magnitude of the current flowing through the fuse element F due to the function of the memory read transistor T1. Since this can be held by the function of the transistor T2, it is possible to realize a defective address storage circuit with extremely high reliability.

Note that the pulse signal application circuit 11 in FIG. 2 is not limited to the circuit shown in FIG. 4 described above; for example, as shown in FIG. A detection circuit may be used or a fourth
The output of the circuit shown in the figure and the output of the circuit shown in FIG. 5 may be AND-processed, and a pulse signal synchronized with the chip selection signal of the CMOS memory may be generated.

The power-on detection circuit shown in FIG. 5 is well known, and detailed description thereof will be omitted, but Pl and P2 are P-channel transistors, N1 to N2 are N-channel transistors, and ■1□ to
114 is an inverter, and C1 and C2 are capacitors.

Further, the program writing to the fuse element is not limited to the current blowing of the above embodiments, but may also utilize laser beam cutting.

Furthermore, the present invention is not limited to the above embodiments, and the present invention is not limited to the above embodiments.
When a fuse element is used to repair a defective circuit part in an O8 circuit (this also includes cases such as logic conversion).

) is generally applicable. As described above, according to the present invention, a MOS switch element is connected in series with a fuse element for repairing a defective circuit in a CMO8 circuit, and this switch element is driven in pulses to obtain a voltage according to the greasing state of the fuse element. Since the circuit configuration is designed to hold the fuse element, the current consumption for detecting the greasy state of the fuse element can be reduced, making it possible to use battery backup as a means of remediating CMO8 failures, and making it possible to realize CMO8 ultra-LSIs with high yields. Can provide programmable circuits.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram showing a conventional CMO8 defect relief circuit, Fig. 2 is a circuit diagram showing an embodiment of the programmable circuit of the present invention, and Fig. 3 is a timing diagram shown to explain the operation of Fig. 2. , FIG. 4a is a circuit diagram showing an example of the pulse signal application circuit of FIG. 2, FIG. 4 is a timing diagram shown to explain the operation of FIG. FIG. 5 is a circuit diagram showing another example, and FIG. 5 is a timing diagram shown for explaining the operation of FIG. 10... Defective address storage circuit, 11...
...Pulse signal application circuit, 12...Potential holding circuit, F...Fuse element, T1...Transistor.

Claims (1)

[Claims] 1. A MOS switch element electrically connected between the other end of a fuse element whose one end is electrically connected to a first power supply and a second power supply; pulse signal applying means for driving conduction to set a potential at a connection point between the switch element and the fuse element according to a greasing state of the fuse element; and holding information on the potential at the connection point set by this means. A programmable circuit comprising potential holding means for generating an output depending on the greasing state of the fuse element. 2. The programmable circuit according to claim 1, wherein the pulse signal applying means outputs a pulse signal synchronized with a change in address signal input of a MOS-LSI. 3. The programmable circuit according to claim 1, wherein the pulse signal applying means outputs a pulse signal synchronized when power is turned on. 4. The programmable circuit according to claim 1, wherein the pulse signal applying means outputs a pulse signal synchronized with a chip selection signal of a MOS-LSI.