JPS5834622A - Signal analogizing circuit for sample hold output signal - Google Patents

Abstract

PURPOSE:To make analog signal without using a low-pass filter by taking difference between a staircase wave signal and a staircase wave signal made by delaying the staircase wave signal and adding a signal obtained by integrating the differential signal for every period to the delayed staircase wave signal. CONSTITUTION:An FM composite signal 1 is converted to staircase wave through a buffer 2 and a staircase wave generating circuit U. This signal passes through the first sample hold circuit V, a buffer 8 and the second sample hold circuit V and delayed by phase difference of two-phase pulse of a pulse generating circuit 3. The sum of output of the circuit U and output of the circuit W inverted in an inversion circuit 14 is obtained by an adder 15 and applied to an integrator 16. Sampling pulse of the circuit 3 is added to the integrator 16 and reset by this pulse. Output of the integrator 16 is added to staircase wave output of the circuit W, and smooth waveform is obtained from the adder 18.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a sample-and-hold output signal analog signal converting circuit that converts a staircase wave signal obtained by a sample-and-hold circuit into an analog signal. The present invention relates to a circuit for converting a hold output signal into an analog signal.

For example, in an FM stereo demodulation circuit, especially a sampler hold type stereo demodulation circuit, the sampled and held left and right channel signals have a staircase waveform, and the nano ring pulse included in the staircase waveform. In view of the above, there is a problem in that a filter is required in order to remove side I4 nodal components resulting from the multiplication of the input signal and the sun cylinder/arm pulse. , for example, FM
It is an object of the present invention to provide a circuit for converting a Sansol-hold output signal into an analog signal, which can be used in a stereo demodulation circuit for the first and second systems, and can omit the above-mentioned filter.

The present invention will be explained below using examples.

FIG. 1 is a block diagram of one embodiment of the present invention.

In FIG. 1, 1 is a signal source, and 2 s S e 8
=11 and 13 have a high slew rate, high input impedance, and low output impedance.

7A amplifier. Reference numeral 3 denotes a two-phase Norse oscillator that generates two sampling/norse trains having a phase difference.

4, 6.9 and 17 are switch circuits consisting of electronic switches such as CMOB analog switches, 1 or field effect transistors, and switch circuits 4.9 and 17 are output from the two-phase 4-phase oscillator 3. First Sun! The switching circuit 6 is turned on and off by the sampling pulse of the second Sunsolings arm output from the two-phase Noculus oscillator 3. The user switch circuit 4 constitutes a staircase wave generation circuit Ut consisting of a Sansol hold circuit that performs cobble hold and converts the signal into a staircase wave signal whose amplitude changes at regular time intervals. The switch circuit 6, together with a capacitor 7, constitutes a first delay circuit V consisting of a Sansol hold circuit that samples and holds the staircase wave signal inputted through the buffer amplifier 5 to the staircase wave generation circuit U and then delays it. There is. Switch circuit 9 is capacitor 1o
and a second delay circuit Wt consisting of a sample and hold circuit that samples and delays the staircase wave signal inputted through the 1/4 Zuffer amplifier 8t. The delay circuit delays the amplitude change of the staircase wave signal and upper limb staircase wave signal from the multi-staircase wave generating circuit U by one cycle, that is, one cycle of the sampler pulse of the first sanclinda notarus train.

14 is an inverting circuit, 15 is a quantity, and an amplifier 13t.
- the staircase wave signal output from the staircase wave generating circuit U input through the staircase wave signal tΔ output from the second delay circuit W, and the signal inverted by the inverting circuit 14 through the amplifier 11. This is the first adder that performs addition. 16 is an integrating circuit], and the integrating circuit 16 is connected to a switch circuit 17 and 4.
The integral output of hK and the switch circuit 17 is reset every number/4 pulses of the first Sandelian falsification sequence.

18 is a second addition circuit;
The output signal of the second one-delay circuit W and the output signal of the integrating circuit 16 inputted through the output terminal OUT K are added together and output to the output terminal OUT K.
Output The operation of the present embodiment configured as described above will be explained in sequence for the case where the present embodiment is applied to a sampling-and-hold type stereo demodulation circuit.

In this case, the signal source 1 is converted into a low output impedance signal source by the I47A amplifier 2, and the 1M conduit shown in FIG. The digital signal is input to the staircase wave generation circuit UK. Also, in Figure 2 (in Xun, the solid line indicates the waveform of the 38KH1 subcarrier, the broken line indicates one channel component of the stereo audio component, and the dashed line indicates the other channel component. 2-phase) The f pulse oscillator 3 is also output from the FM composite signal from the signal source 1. It is phase-synchronized to the FM composite signal, which is included in the t signal, and the t signal. Figure 2(b) for
The first sun shown in! A pair of sampling pulse trains of 38 KHz with a mutual phase difference of 180 degrees between the IJ 7 da pulse train and the second Sandelinda nodal pulse train shown in Figure 2(e) K for separating the right channel signal. Output.

It is assumed that the switch circuits 4, 6, 9, and 17 are turned on when the applied sampling pulse is at a high potential, and are turned off when the applied sampling pulse is at a low potential.

Therefore, the sampling pulse shown in FIG. The switch circuit 4 is charged to the level of the current 1M current signal applied to the sampling/reflection signal. When the sampling pulse becomes a low potential, the switch circuit 4 is turned off. However, since the buffer amplifiers 5 and 13 connected to the output terminal of the staircase wave generation circuit U have high input impedance and are isolated from the capacitor 12 and the amplifier 2, the capacitor g'' The electric charge stored in the capacitor 12 is held until the next time the voltage becomes high, and the potential of the capacitor 2 is transmitted to the subsequent stage via the amplifier 5.13'J-. In this case, since the purpose is to demodulate only the envelope of the FM con/dc signal, the width of the sampling/1 pulse that turns on the switch circuit 4t is narrow and the off period is long, but as described above (the capacitor 12 The potential of is held during the off period, and the output of the staircase wave generation circuit U becomes the staircase wave signal shown in FIG. Same as waveform.

The output of the nine-step wave generation circuit U shown in FIG. 2(d) is applied to the first delay circuit V through the buffer amplifier 5.

The amplifier 5 converts the potential of the capacitor 12 into a low output impedance signal source as an input signal. On the other hand, the switch circuit 6 is turned on and off by the second sampling/sampling of the 9th pulse train/9th pulse, that is, the sampler pulse shown in FIG. ) is charged to the potential K of the staircase wave signal shown in FIG. 2(d) when the sampling pulse occurs, and is held until the occurrence of the next sampling pulse. The potential of 7 is the second g.
The potential becomes stepwise at each period of the sampler pulse shown in (a).

However, since the Sansoling wave in Figure 2(c) has a phase difference of 180 degrees with respect to the sampling/9 wave in Figure 2(c), the output signal of the first delay circuit V is As shown in Fig. 2(・)K, the same shape as in Fig. 2(d) is obtained by delaying the period of the amplitude change of the staircase wave signal outputted from the staircase wave generating circuit U shown in Fig. 2(d) by i period. becomes a staircase wave signal.

In addition, during the delay, when the switch circuit is off and the capacitor 7 holds charge, the charge on the capacitor 7 is not reduced because the amplifier 8 has a high input impedance. Furthermore, when the subsequently applied sampler pulse is generated, if the staircase wave signal applied as the input signal is lower than the potential that was off when the sampler pulse was generated immediately before, the charge on the capacitor 7 is When it is sucked into the switch circuit 6t-5, it becomes . Therefore, even if the sampling/4 pulse width is narrow, if the on-resistance of the switch circuit 6 is small, the input impedance of the amplifiers 5 and 8 is high, and the output impedance is low, so the capacitor 7
can be completely charged to the potential K of the λ power staircase wave signal, and the electric charge of the capacitor 7 can be discharged, so that the staircase wave signal waveform applied to the first delay circuit V can be changed to the rising and falling phases. Even if the waveform of the delayed staircase wave signal is sharp, the waveform of the delayed staircase wave signal is delayed without being distorted.

In addition, the second delay circuit W also operates in the same manner as the first delay circuit V detailed above, so that the waveform is not destroyed.
The staircase wave signal output from the first delay circuit V, whose waveform is shown in FIG. 2 (@), is delayed.

In this case, the switch circuit 9 of the second delay circuit W
t-On/off sampling/1 pulse is shown in Figure 2 (b
) The sampling pulse 9 as shown in FIG.
Since the angle is 0 degrees, the second delay circuit W is
) Figure 2 (f) shows the staircase wave signal shown by K delayed by 180 degrees.
The staircase wave signal shown in is output.

Therefore, the staircase wave signal output from the second delay circuit W is the first sampler pulse shown in FIG. It becomes a staircase waveform that is delayed by one period of the Sansolingturus of the sequence.

Next, the output of the second delay circuit W is inverted by the inversion circuit 14 and added to the output of the staircase wave generation circuit U outputted via the Av amplifier 13 in the first adder 15. In other words, it is equivalent to being subtracted because it is inverted and added, and from the first adder 15, the
) is subtracted from the staircase wave signal of FIG. 2(f), and the staircase wave signal shown in FIG. 2 ω is output.

What is the relationship between the output signal of the sixteenth adder 15 on the output signal waveform of the second delay circuit W shown in FIG. This shows whether a potential difference occurs in the staircase wave signal. That is, the potential of (shown in Figure 2 ω) is (7) in Figure 2 (f), (-00 potential difference [(a) - (
b)], and the potential of (6) becomes the potential of ((m − H) ).

The output signal of the first adder 15 is integrated by the integrator 16, and the switch circuit 17 is turned on every period of the sampling noculus shown in Fig. 2, and the integrator 16 is reset. , the output of the integrator 16 has a sawtooth waveform as shown in FIG. 2(h).

The output of the integrator 16 is added to the output of the second delay circuit W in a second adder 18. That is, Fig. 2(f)
and the staircase wave signal of the second delay circuit W shown by K.

The output of the integrator 16 shown in FIG. 2(h)K is added by the second adder 18. Therefore, the output of the second adder 18 is as shown in FIG. 2(1)K. Figure 2(d) The output staircase wave signal of the staircase wave generation circuit U up to K, that is, li' in the sampling-and-hold stereo demodulation circuit.
One channel signal obtained by sampling and holding the M, I, and G signals is passed through a low-pass filter and becomes similar to the output signal.

Therefore, according to this embodiment, the low-pass filter in the sampling-and-hold type stereo demodulation circuit can be omitted.

Stereo demodulation circuit using master sampling and hold method. Take a break! According to this embodiment, the amplifier provided between the ring-hold signal and the low-pass filter has a slew rate that is required to amplify the staircase wave signal that was conventionally required because the output signal is output as an analog signal. It is possible to amplify the signal without distortion and transmit it to the subsequent stage using a simple amplifier without requiring a high-performance amplifier.

In addition, although the stereo demodulation circuit was explained above as an example,
Without losing generality, according to this embodiment, it is possible to convert a sampled and held output signal into an analog signal.As explained above, according to the present invention, it is possible to convert a staircase wave signal into an analog signal. I can do it.

Therefore, by applying the present invention to a stereo demodulation circuit, the amount of the sun cylinder/f pulse component remaining on the output waveform is reduced, and at the same time, the side indium component of the sampling frequency υ is also reduced. Therefore, there is no need to add a low-pass filter.

Further, there is an advantage that the amplifier in the post-rounding stage, where the output waveform is an analog signal, can be a simple amplifier.

[Brief explanation of the drawing]

FIG. 1 shows an embodiment of the present invention! Rock diagram. FIG. 2 is a waveform diagram for explaining the operation of one embodiment of the present invention. 2.5, 8.11 and 13.../42. amplifier, 3...2-phase falsification oscillator, 4, 6.9 and 17
... switch circuit, 14 ... inversion circuit, 15 and 18 ... first and second adders, 16 ... integrator, U, ... staircase wave generation circuit consisting of sample hold circuit, ■ and W...first and second delay circuits consisting of sample and hold circuits Patent applicant: Trio Co., Ltd.

Claims (1)

[Claims] A staircase wave generation circuit that outputs a staircase wave signal whose amplitude changes at regular time intervals through a sample hole of an input signal, and a Young Ring tool for sample-holding the output staircase wave signal of the staircase wave generation circuit. a delay circuit for delaying by one cycle; a subtraction means for subtracting the output staircase wave signal of the delay circuit from the output staircase wave signal of the staircase wave generation circuit; A circuit for converting a Sanzor-hold output signal into an analog signal, comprising: an integrating means for integrating each time, and an adding means for adding the output signal of the integrating means and the output staircase wave signal of the delay circuit. .