JPS5822907B2 - Color Burst Warmer Warmer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a circuit for extracting a specific wave from a color burst signal in a color television signal.

To explain in more detail, the control voltage of the VCO is controlled according to the phase difference between the oscillation output of the VCO (voltage controlled oscillator) and the color burst signal of the input video signal.
A phase-locked loop (LL) is constructed, from which a sampling clock pulse is obtained, and only one cycle of the color burst signal of the input video signal always at a fixed position is detected, and the PLL is The present invention relates to a circuit for extracting a specific wave of the color burst signal.

When digitally encoding a video signal, especially an NTSC signal that has time axis fluctuations such as VTR output, it is necessary to match the phase of the sampling clock pulse to the phase of the video signal that includes the time axis fluctuations. There is.

When obtaining such a sampling pulse, the phase of the oscillation output of the VCO (voltage controlled oscillator) and the horizontal synchronization signal or color burst signal of the input video signal is compared, and the above-mentioned PLL is used to control the control voltage of the CO. (phase locked loop) can be used.

In this case, if you try to detect the phase difference only from the horizontal synchronization signal in the VTR output signal, if the S/N ratio of the output signal is poor, for example, the waveform of the horizontal synchronization signal may become dull, and accurate detection may not be possible. .

Therefore, when handling an NTSC signal, a color burst signal included in the backhaul of the horizontal synchronization signal is used instead of the horizontal synchronization signal.

The signal-to-noise ratio of the color burst signal can be improved by passing it through a narrow band-pass filter, so it is possible to obtain a sampling clock pulse that accurately follows the time-axis fluctuations of the input NTSC color signal. .

In other words, in a black and white video signal, from the horizontal synchronization signal, the NT
For the SC signal, it is sufficient to detect the phase difference from the color burst signal.

However, in a PLL using a color burst signal, the oscillation frequency of vCO is phase-locked at multiple points due to the characteristics of a phase comparison circuit that directly uses a burst signal having waves of 8 to 12 cycles. There is a possibility that this may occur, leading to a risk of malfunction.

Therefore, in order to focus on only one wave in the burst signal and perform phase comparison, we extracted one cycle in the center from the color burst signal using the window pulse created by the horizontal synchronization signal. You should do it.

However, since the relative positions of the horizontal synchronizing signal and the burst signal are not strictly determined, it is a hassle to adjust the position of the window pulse each time the relative position changes depending on the video signal.

In order to solve this problem, the present invention uses a window pulse whose position is automatically controlled to detect one cycle always at a fixed position of a color burst signal in a video signal, thereby controlling the above-mentioned PLL. We propose a burst signal extraction circuit constructed as follows.

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to the drawings showing one embodiment.

That is, Fig. 1 is a block diagram showing the basic configuration of a phase-locked loop (PLL) that generates a color burst signal and a sampling clock pulse. A color burst with a time-varying axis.

A signal is provided.

And, the PLL with has a phase comparator circuit 2, a compensation circuit 3,
Consists of vCO4 and pulse forming circuit 5,
The comparison pulse forming circuit 5 generates a pulsed signal having a predetermined phase relationship with the color burst signal from the oscillation output of the vCO4, and the phase comparison circuit 2 compares the phase of this pulsed signal and the color burst signal. Let's do it.

This comparison output is applied to vCO4 via the compensation circuit 3, and this vCO4 produces a sampled pulse of a predetermined frequency corresponding to the color burst signal.

FIG. 2 shows a basic block diagram of a sampling clock pulse generation circuit in which a color burst signal extraction circuit according to the present invention is added to the basic configuration of FIG. 1.

That is, in FIG. 2, the human video signal is first divided into a horizontal synchronizing signal and a color burst signal by each signal separation circuit 1.
It is separated by 1 and 12.

The horizontal synchronizing signal is supplied as a window pulse to a sampling hold circuit 15 via a voltage controlled phase shift circuit 13 and a window pulse forming circuit 14.

Further, the color burst signal is supplied from the pulse shaping circuit 16 to the sampling and holding circuit 15 via the gate circuit 21.

This sampling and holding circuit 15 detects the phase difference between the window pulse and a specific wave in the color burst signal, and holds error information until the next phase comparison is performed.

The information thus detected is supplied to the voltage controlled phase shift circuit 13 via the compensation circuit 17.

In this way, the position of the window pulse is always controlled, and the window pulse can always pick out one cycle at a fixed location in the color burst signal.

Further, 18 is a selection circuit that supplies either one cycle of the horizontal synchronizing signal or the color burst signal to the sampling pulse forming circuit 19.

This selection circuit 18 is the output of a detection circuit 20 that detects whether the video signal is black and white (monochrome) or color, and is extracted by a gate circuit 21 using the sampling pulse of the wind pulse and color burst signal whose phases are compared. The one-cycle wave of the color burst signal and the horizontal synchronization signal from the separation circuit 11 are switched.

Further, the output of the sampling pulse forming circuit 19 is output from a comparison pulse forming circuit 25 which counts down the outputs of the phase comparison circuit 22, the compensation circuit 23, vCO24 and vCO24 so that the phases can be compared using a horizontal synchronization signal or a color burst signal. is supplied to the PLL.

In this way, the aforementioned sampling clock pulse can be obtained as the oscillation output of the VCO 24.

In this way, in the embodiment with the configuration shown in FIG. 2, even if there is no color burst signal, such as a vertical synchronization period, or there is a large step-like time axis fluctuation such as a skew, the burst signal is always generated. Since one cycle at a fixed location in the signal can be extracted, and this signal indicates a fixed location in the video signal, the v
By resetting the oscillation phase of the CO, a sampling clock having a constant phase can be obtained with high precision for the video signal.

Next, a circuit diagram and a waveform diagram specifically showing the portion surrounded by dotted lines in the above circuit will be explained with reference to FIGS. 3 and 4.

In FIG. 3, numeral 31 is an input terminal for a horizontal synchronizing signal obtained from a video signal, and the horizontal synchronizing signal as shown in FIG.
/2 frequency divider circuit 32 and a monostable multi-by-break (hereinafter referred to as mono-multi) for time-delaying a window pulse, which will be described later, to bring it to the center of the burst signal group.

) 33 respectively. The above 1/2 frequency divider circuit 32
outputs a signal with a waveform as shown in FIG. 4E.

The mono/multi 33 is triggered at the falling edge of the horizontal synchronizing signal, outputs a signal as shown in FIG. 4B, and triggers the mono/multi 34 at the falling edge of this signal.

The mono-multi 34 is configured so that its time constant can be electrically controlled, and outputs a mono-multi signal as shown in FIG. The signal is supplied to the mono multi 35 to control the position of the window pulse output from the mono multi 35.

The mono-multi 35 constitutes a window pulse forming circuit which is triggered by the falling portion of the output pulse from the mono-multi 34 and forms a window pulse as shown in the fourth figure.

The window pulse formed by this monomulti 35 is supplied to an AND gate circuit 36, an AND gate 38, and a NAND circuit 39.

Here, the AND gate circuit 36 and the AND gate circuit 38 alternately gate the window pulse according to the frequency divided output of the 1/2 frequency divider circuit 32 described above.

That is, the AND gate circuit 36 operates as shown in FIG. The output is supplied to an AND gate circuit 40.

At this time, the output of the AND gate circuit 38 is logic 0, and the mono/multi 41 following it does not operate.

Conversely, when the output of the 1/2 frequency divider circuit 32 is logic XXO" (for example, this occurs every even number), the output of the AND gate circuit 36 is logic 10", and the AND gate The output of the circuit 38 becomes logic 11'', and the output of the mono/multi 35 is supplied to the mono/multi 41.

Therefore, this mono/multi 41 is triggered by the falling part of the above signal and outputs a pulse as shown in FIG. ” to form.

The output pulse from this mono/multi 42 is supplied to an AND gate circuit 43.

The output pulse from the mono/multi 42 is the mono/multi 42.
1 4 Q n5e corresponding to the period of the color burst signal for the window pulse created by Multi 35
This becomes a window pulse given a time delay of c.

The reason why two types of window pulses are used in this way is that N
The phase of the subcarrier of the TSC color signal is 1 per horizontal period.
This is because the difference is 80.

On the other hand, the output of the 1/2 frequency divider circuit 32 and the mono/multi 3
The output of No. 3 is supplied to an AND gate circuit 44.

Here, as described above, the 1/2 frequency divider circuit 32 outputs a logic "1" to the odd numbered output signal, and outputs a logic "0" to the even numbered output signal to the AND gate circuit 44. Therefore, when the output of logic "1" is received (that is, every odd number), due to the fall of the output of the AND gate circuit 44 (this is the same pulse as in FIG. 4B), The mono-multi 45 operates to obtain a pulse as shown in FIG. 4H.

This pulse is further converted into a mono-pulse for overflow pulse formation.
The monomulti 46 outputs an overflow pulse as shown in FIG.

This overflow pulse is input to the NAND gate circuit 39 via the inverter 47.

This NAND gate circuit 39 detects whether or not the window pulse from the mono/multi 35 is within the overflow pulse. When the window pulse is outside the overflow pulse, the output becomes logic 10"; output becomes logic ``1'' [When the inverted signal overlaps the above window pulse (both have logic ``X 1''), a logic ``1'' signal is generated, but since NOT is applied, this Then the logic becomes 10"].

In other words, based on this signal information, mono/multi 4
An overflow is detected at 8 (this D mono multi 48 operates when the logic ``XO'' changes to the logic ``1'').

The mono-multi 48 has a time constant equal to, for example, 10 horizontal sections H, and the NAND gate circuit 39
Triggered at the rising edge of the window pulse supplied via

That is, the NAND gate circuit 39 is gate-controlled by the overflow pulse, and is closed during the overflow pulse and opened outside the overflow pulse.

Therefore, when the window pulse enters during the overflow pulse, the mono multi 48 is not triggered and maintains the logic 10" output state, and when the window pulse is removed from the overflow pulse, the window pulse remains at logic 10". It is triggered at the falling edge of the dope pulse and generates a pulse that maintains the logic "X1" output state for a period of 10H as shown in FIG. 4J.

The output of the mono/multi 48 is an AND gate.
is supplied to the AND gate circuits 6 and 1, and is also supplied to the AND gate circuits 40 and 43 via the impark 49,
Controls opening and closing of each gate.

Therefore, when the window pulse is within the overflow pulse, the AND gate circuit 61 is closed and each AN
The D gate circuits 40 and 43 are in an open state, and the above A
A window pulse as shown in FIG. Output.

The window pulse (4th pulse) extracted in this way
M) is supplied to the AND gate circuit 52 and the sawtooth waveforming circuit 55.

In this AND gate circuit 52, one specific burst signal among the burst signals (N in FIG. 4) supplied to the input terminal 53 and shaped by the waveform shaping circuit 54 is extracted by the window pulse. By outputting the signal, a jealous pulse shown in FIG. 4 O is obtained at the output terminal 62.

Furthermore, the sampling pulse, which is one burst signal extracted in this way, and the OR gate circuit 51
The sawtooth wave signal formed by the sawtooth wave forming circuit 55 based on the window pulse obtained from the above is supplied to a phase comparator 56 constituted by a sample and hold circuit. The phase difference is detected by

The phase detection output from this phase comparator 56 is supplied to the above-mentioned mono/multi 34 via a low-pass filter 57 and an amplifier 58.

The position of the window pulse is controlled by the phase detection output so as to extract a specific wave in the center of the burst signal as described above.

Furthermore, when the window pulse is outside the overflow pulse, the AND gate circuit 61 is opened and each A
The ND gate circuits 40 and 43 are closed, and operate so as to use the pseudo signal output from the AND gate circuit 61 via the OR gate circuit 51 as a window pulse.

That is, the mono-multi 59 is triggered by the falling part of the output pulse from the mono-multi 45, and the trigger is triggered by the falling part of the output pulse from the mono-multi 59.
The triggered mono/multi 60 constitutes a pseudo signal forming circuit that forms a pseudo signal.

The mono multi 60 is triggered by the rising edge of the output pulse from the mono multi 59 and generates a pseudo signal as shown in FIG. 4K located on the leading edge side of the overflow pulse.

This pseudo signal is supplied to the AND gate circuit 61, and when the window pulse deviates from the overflow pulse, the output signal is output from the AND gate circuit 61.
It is output via the R gate circuit 51.

That is, in this embodiment, it is detected whether or not the window pulse enters the overflow pulse.
When it comes to extracting burst signals with large transmission distortion,
Over the IOH period given by the time constant of the mono/multi 48, the pulse shown in Figure 4 0 (dotted line) is extracted by using the pseudo signal C (M dotted line in Figure 4) instead of the window pulse. By using this, it is possible to prevent the window pulse phase control loop based on the phase detection output from the phase detector 56 from being locked to the phase of one wave of the burst signal outside the overflow pulse.

As is clear from the description of the embodiments described above, according to the present invention, a specific wave in a color burst signal is transferred to a phase-locked loop by a color burst extraction signal formed at a predetermined position from a horizontal synchronizing signal. The color burst signal to be extracted is extracted as a signal that locks the oscillation phase of the voltage oscillator, and the phase of a specific wave in the extracted color burst signal is compared with the phase of the extracted pulse. In the color burst signal extraction circuit that controls the phase of the sampling pulse with respect to the phase of the color burst sampling pulse, when the color burst sampling pulse deviates from a predetermined interval determined based on the horizontal synchronization signal, the color burst sampling pulse In other words, by controlling the phase of the color burst extraction pulse using a pseudo pulse having a fixed phase relationship with the horizontal synchronization signal, the window pulse can be adjusted according to the horizontal synchronization signal of the input video signal. The position of the window pulse can be automatically controlled to reliably extract a specific wave of the color burst signal, and the control loop for controlling the position of the window pulse can extract one wave of the burst signal with large transmission distortion. It also prevents the device from being locked.

Therefore, with the color burst signal extraction circuit according to the present invention, it is possible to perform accurate time axis correction, etc. even for NTSC video signals with poor S/N ratios, and the desired purpose can be satisfactorily achieved. It can be achieved.

[Brief explanation of the drawing]

The figures are a circuit diagram showing an embodiment of the present invention and a waveform diagram explaining the circuit diagram, and Fig. 1 is a block circuit diagram of a PLL configured by a color burst signal extracted by a color burst signal extraction circuit according to the present invention. , FIG. 2 is a block circuit diagram having a color burst signal extraction circuit, FIG. 3 is a circuit diagram showing the circuit block of FIG. 2 in more detail, and FIG. It is a time chart figure of a signal waveform. 11...Horizontal synchronization signal separation circuit, 12...
... Color burst signal separation circuit, 13 ... Voltage control phase shift circuit, 14 ... Window pulse forming circuit, 15 ... Sampling hold circuit,
16...Sampling pulse forming circuit, 18.
....Selecting circuit for one cycle of horizontal synchronization signal or color burst signal.

Claims (1)

[Claims] 1. A signal that locks the oscillation phase of a voltage-controlled oscillator in a phase-locked luneve of a specific wave in a color burst signal by a color burst extraction pulse formed at a predetermined position from a horizontal synchronization signal. The phase of a specific wave in the extracted color burst signal is compared with the phase of the extracted pulse, and the phase of the old extracted J pulse is controlled with respect to the phase of the color burst signal to be extracted. In the color burst signal extraction circuit, when the color burst extraction pulse deviates from a predetermined interval determined based on the horizontal synchronization signal, the color burst extraction pulse is replaced with the horizontal synchronization signal. A color burst signal extraction circuit extracts a specific wave from the color burst signal using a pseudo pulse having a fixed phase relationship with the color burst signal.