JPS58225469A - Multi-processor controlling system - Google Patents

Abstract

PURPOSE:To minimize the change of a monitor program, by selecting one of idle processor units and indicating the execution of an instruction following a program state word loading instruction. CONSTITUTION:A multi-processor controlling system comprises a memory unit 10, plural processor units 20-23, a memory bus 40 and a control bus 50. The memory unit 10 stores plural programs. The processors 20-23 share the unit 10 and execute simultaneously at least one of plural programs. When one of processors 20-23 starts execution of a new program by a program state word loading instruction, one of other idle processor units is selected. Then the execution is indicated to this selected processor unit for an instruction following the program state word loading instruction.

Description

Detailed Description of the Invention (Description of the Technical Field to Which the Invention Pertains) The present invention relates to a multiprocessor control system in an electronic computer system, and particularly to a multiprocessor system including a memory unit shared by a plurality of processor units. 1. Multiprocessor control method for executing the program (Description of prior art) Conventionally, in a multiprocessor system, it has been necessary to allocate a job program to be executed to each of multiple processor units. It is well known that this is performed by a special control program called a monitor program. The monitor program has the function of selecting an executable job program and assigning it to a processor unit.The monitor program of a multiprocessor system manages the number of processor units existing in the system and the status of each processor unit. There is a need to. However, when executing a monitor program in a single processor system that has only a single processor unit, there is no need to be aware of multiple processor units, so if you try to apply this to a multiprocessor system, the monitor program Significant changes to the program itself will be required. However, the transition from a single processor system to a multiprocessor system is often necessary as part of the growth of electronic computer systems. In such cases, changes to the monitor program generally involve changes to the job programs that operate under its control, and a major challenge for those skilled in the art is how to minimize the amount of change. ing.

(Detailed Description of the Invention) For the purpose of the present invention, a multiprocessor control system configured so that it can be applied as a monitor program for a multiprocessor system with minimal changes to the monitor program used in a single processor system. The goal is to provide a method.

(Detailed Description of the Invention) A multiprocessor control system according to the present invention includes a memory unit, a plurality of processor units, a memory bus,
This was realized by including a control bus. Memory unit fl is for storing a plurality of programs. A memory unit lf is shared by a plurality of processor units, and is used to simultaneously execute at least one program among a plurality of programs.

Each processor unit is equipped with a buffer count register and an interprocessor communication control section. A memory bus connects the memory unit and the plurality of processor units, and information is transferred through the memory bus. The control bus connects a plurality of processor units to each other, and is connected to an inter-processor communication control unit inside each processor unit.

When one of the multiple processor units starts executing a new program by a program state word load instruction, if any of the other processor units is in the idle state, it is in the idle state. One of the processor units is selected and the selected processor unit is instructed to execute the instruction following the program state word load instruction.

(Explanation of the principle and operation of the invention) Before explaining one embodiment of the present invention, it is important to understand that in a single processor system consisting of only a single processor unit as shown in FIG. ) Explain how to allocate K job programs.

Referring to FIG. 1, the single processor system includes a processor unit 2 having a memory unit 1 and an instruction count register 3, and a signal line 4 for connecting the memory unit 1 and the processor unit 2. has been done. The processor unit 2 is a unit that executes a program, and sequentially retrieves each instruction constituting the program from the memory unit 1 according to the contents of the instruction count register 3 and executes it.

Referring to FIG. 2, the program state word (P8
W) It is divided into field 1, field 2 and field 3.

This program status word has information necessary to execute the program, and this information is unique for each program.

The contents of field 1 above determine the execution mode of the program belonging to the corresponding program status word,
Field 2 indicates the location within memory unit 1 of the first instruction of the corresponding program, that is, address information. This is specifically called an instruction counter. Field 3 contains mask information regarding input/output interrupts during program execution. As already explained, program status words are defined for each program, so there are as many program status words as there are programs.
It is stored inside the memory unit 1 together with the program. FIG. 3 conceptually shows a state in which each program and a program status word are stored in association within the memory unit 1. Referring to FIG. 3, the monitor program and job program a
1 The program status words unique to job program b and job program C are P8WO1P SW
a, PSWb, and P8Wc. 1, program state word p swo, P 8W
The storage addresses in the memory of a, PSWb, and P8Wc are 100016.20001, respectively.
6.2010ts, and 20201+1. Here, the 16F hexadecimal representation of the subscript is shown.

Furthermore, the start addresses of the monitor program, job program a, job program b, and job program C within the memory unit 1, that is, the address of the first instruction to be executed in each program, are each 500.
016.6000sa, 700016, and 8000
Suppose that it is 16. Therefore, the contents of field 2, the instruction count portion, of each program state word shown are 50001. ．． 600016
．． 700016, and 5ooo 16.

As explained above, when executing a program KTh,
By reading the program status word, the operating mode of the corresponding program and the storage address of the program within the memory unit 1 can be recognized. Therefore, in order for these programs to be executed by the processor unit 2, the program status word corresponding to the program to be started is taken into the processor unit 2 and given to the program execution controller inside the processor unit 2. good. For this purpose, a program state word load instruction (LOAD PSW instruction) is especially provided.

FIG. 4 illustrates the structure of the program state word load instruction. 98 in the HOP code field of this instruction.
316, and the address field contains the memory address where the program state is stored.

The program state word load instruction has the function of "taking out the program state word from the memory address indicated by the address field and loading it into a predetermined register inside the processor unit 2." This predetermined register is for holding the contents of each field of the program state word, and in particular, the contents of field 2 shown in FIG. 2, that is, the contents of the instruction count section, are stored in the instruction count register 3 shown in FIG. is stored in

That is, in response to the program state word load instruction, the instruction count register 3 inside the reprocessor unit 2 includes an instruction count field that is new information different from the previous information. Program operation modes other than those set in the instruction count register 3 are executed in the same manner. The processor unit 2 executes the program by extracting and executing instructions from the memory unit 1 according to the contents of the instruction count register 3.

This point has already been explained, and after executing this program state word load instruction, the processor unit 2 will continue to execute a different program. In other words, the program executed inside the processor unit 2 has been switched. Using the above functions, the monitor program allocates the job program to the processor unit 2. That is, for example, the third
As shown in the figure, job program a is waiting to start execution.
If b, c exist, the monitor program selects one of them, for example job program af, according to predetermined selection criteria and provides the corresponding program status word to the processor unit 2. however,
Since the monitor program itself is one program, the program currently being executed inside the processor unit 2 is the monitor program. That is, the program state word held by the processor unit 2 is the program state P8WO for the monitor program. Therefore, it is necessary to switch the execution program of the processor unit 2, or in other words, the program status word (PSW) from the monitor program to the job program a. For this reason,
The program status word P s wa corresponding to job program a is loaded into the processor unit 2 by the program status word load command.

FIG. 5 is a flow chart showing the case where the monitor program allocates a job program to the processor unit 2. As shown in FIG. 5, first, one program is selectively determined from among the executable job programs, and after distinguishing the current program as being in the running state, the corresponding program state word is sent to the program state word load command. is loaded into the processor unit 2 by. In the flowchart shown in FIG. 5, a particularly important point is that no processing is performed after the program state word load instruction is executed. This is because this monitor program is for a single processor system,
This is because there is only one processor unit 2 that executes the program. Therefore, after the job program is assigned to the processor unit 2, there are no other processor units that can execute the program.

Therefore, after the monitor program allocates the job program to processor units (K), it becomes meaningless for subsequent processing since there is no processor unit to operate on. From the above explanation, it is clear that in the case of a single processor system, the monitor program assigns job programs to the processor units 2.

(Description of an Embodiment) Next, an embodiment of a multiprocessor control system according to the present invention constructed by applying this principle will be described with reference to the drawings.

FIG. 6 shows an embodiment of the multiprocessor control scheme according to the present invention. In FIG. 6, the multiprocessor control system is composed of a memory unit 10 and first to fourth processor units 20 to 23. The first to fourth processor units 20 to 23r/i are connected by a common memory bus 40. Further, the first to fourth processor units 20 to 23 are each provided with first to fourth inter-processor communication control units 60 to 63 for mutually exchanging information with other processor units. ing.

The first processor unit 20 includes a first inter-processor communication control section 60 and a second processor unit).
21Kij A second inter-processor communication control section 61, a third inter-processor communication control section 62 corresponds to the third processor unit 22, and a fourth inter-processor communication control section 63 corresponds to the fourth processor unit 23. A common control bus 50 for the first to fourth inter-buseser communication control units 60 to 63
are connected by. The first to fourth processor units 20 to 23 are program execution units similar to the single processor system shown in FIG.
33.

Next, the operation of a monitor program according to an embodiment of the multiprocessor control system shown in FIG. 6 will be described with reference to the flowchart shown in FIG.

Referring to FIG. 7, steps A, B, and CVi operate in the same way as in the case of the CVi single processor system, except that after execution of the branch instruction in step D, the system returns to step AtC. This is different for single-processor systems. That is, after one job program is assigned to one of the first to fourth processor units (20 to 23) by the transition from step A to step B to step C, the program is further assigned to one of the first to fourth processor units (20 to 23), and then transferred to one of the step D by the branch instruction. Return to A.

Thereafter, similar processing is repeated. Referring again to FIG. 6, in the first to fourth processor units 20 to 23,
Each program state word load instruction switches from its own program state word to the program state word specified by the corresponding instruction, but this operation is the same as in the case of a single processor. However, when performing this switching operation in the above embodiment according to the present invention, the first to fourth inter-processor communication control units that are present in the first to fourth processor units 20 to 23 respectively correspond to the switching operation. 60 to 63 and the common control bus 50,
Select one of the other idle processor units. Therefore, the program state word held until then is transferred to the selected processor unit. In other words, after the processor unit that was executing the monitor program gives the program status word of the monitor program that was being executed to one of the other processor units that is in the idle state, it is specified with a program status word load instruction. It also loads the program status word of the new job program into itself and starts executing this job program. Here, the processor unit that executes the monitor program is called the first processor unit).
20, and the processor unit selected by the first processor unit 20 in the idle state is assigned to the second processor unit 20.
Assuming that the processor unit 21 is the first processor unit 20, after giving the program state word of the Fi monitor program to the second processor unit 21, the program state word of the new job program specified by the program state word load instruction is given to the second processor unit 21. 1 processor unit 20
Load into.

As a result, the first processor unit 20 starts executing the job program. In response to instructions from the first processor unit 20, the second processor unit 21 communicates with the first and second inter-processor communication controller 6.
0, 61 and the control bus 50, when receiving an instruction to load the program status word of the monitor program, it starts executing the program according to the program status word of the given monitor program. At this time, since the program state word is the state after the first processor unit 20 executes the program state word load instruction, the instruction count part of the program state word is located immediately after the program state word load instruction in FIG. The branch instruction of step D is specified. Therefore, the second processor unit 21 executes the branch instruction in step D in FIG. 7, so it returns to step A and executes step A→
The processing from step B to step C is continued in sequence. Therefore, when the monitor program is executed in the second processor unit 21 in the same manner as previously executed in the first processor unit 20, and the program state word load instruction shown in step C in FIG. The second processor unit 21 selects another processor unit that is in an idle state, gives the program status word of the monitor program to this processor unit, and then starts executing the job program. Processor units whose monitor programs are in an idle state one after another in this way)
The job program is started by the processor unit K.

FIG. 8 is a diagram chronologically showing how a job program is started starting from the first processor unit 2o and ending at the third processor unit 22. In FIG. 8, job programs a, b, and c are waiting to start execution, and each job program is selected in this order. When the first processor unit 20 switches from the monitor program to job program a, the second processor unit starts executing the monitor program.

When the second processor unit 21 switches from the monitor program to the job program b, the third processor unit 22 starts executing the monitor program. Third
When the processor unit 22 shown in the figure switches from the monitor program to the job program C, the fourth processor unit 23 starts executing the monitor program. In this embodiment, the fourth processor unit 23 is in the idle state, but since there is no job program to start, the monitor program keeps the fourth processor unit 23 in the idle state again.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an actual example of a single processor system, FIG. 2 is a diagram showing the structure of a program state word defined by the multiprocessor control method according to the present invention, and FIG. FIG. 4 is a diagram illustrating the structure of a program state word load instruction, and FIG. FIG. 6 is a block diagram showing an embodiment of the multiprocessor control method according to the present invention, and FIG. 7 is a block diagram showing an example of the multiprocessor control method of FIG. FIG. 8 is a flowchart illustrating how a job program is started from the processor unit in FIG. 1 to a third processor unit in chronological order. 1.10...Memory unit 2.20-23...Processor unit 3.30-3
3... Instruction count registers 60 to 63... Inter-processor communication control unit 4°-) -
E-IJ bus 50° 1 bus
(5 Patent Applicant NEC Co., Ltd. Agent Patent Attorney Hisashi Inoro Hisashi Izuen) ``A-3 Figure PSW. Copy Figure 4 Figure 5

Claims (1)

[Claims] a memory unit for storing a plurality of programs; a multi-tube processor unit for sharing the memory unit and simultaneously executing at least one program among the plurality of programs; a memory bus for connecting the plurality of processor units; and a control bus for connecting the plurality of processor units; and each of the plurality of processor units has an instruction count. a register and an inter-processor communication control unit connected to the control bus, and when one of the plurality of processor units starts execution of a new program in response to a program state word load instruction, the other processor unit If there is one in the idle state, select one of the processor units in the idle state i,
A multiprocessor control system characterized by instructing the selected processor unit to execute an instruction following the program state word load instruction.