JP2506591B2 - Auxiliary processor - Google Patents

Description

Detailed Description of the Invention

[0001]

The present invention relates to a host processor (hereinafter abbreviated as CPU) in a computer system.
The auxiliary processing device.

[0002]

2. Description of the Related Art In recent years, an auxiliary processing device for a computer has been improved in speed and function. By combining a CPU and an auxiliary processing device, the load on the CPU can be reduced.

There are two types of execution states of the auxiliary processing device. First, the CPU sequentially issues commands from the auxiliary processing device,
The command sequence that is transferred to the auxiliary processing device or prepared in advance is referred to as a DMA controller (hereinafter, DMAC).
Abbreviated. ) Continuously transfers to the auxiliary processing device, that is, the CPU or the DMAC becomes the bus master, and the auxiliary processing device becomes the slave to perform command transfer.
This is an execution state in which the auxiliary processing device interprets and executes the command (hereinafter, referred to as slave mode execution state).
Secondly, the auxiliary processing device itself sequentially fetches and executes its own command prepared in the memory similarly to the CPU (hereinafter, referred to as a master mode execution state). In this master mode execution state, the CPU only has to prepare the command sequence of the auxiliary processing device in the memory and then activate the auxiliary processing device.

On the other hand, as an auxiliary processing device, there is an auxiliary processing device that has both slave mode and master mode execution states. In this case, there is a case where the execution state can be changed directly at the time of execution, and the changing method will be described below with reference to FIG.

FIG. 4 shows a time chart for changing the execution state at the time of execution. In FIG. 4, 41, 4
The parts indicated by 3, 47, and 49 indicate that the auxiliary processing device is in the slave mode execution state.
5, 46 and 48 indicate that the auxiliary processing device is in the master mode execution state. Also, 41, 43, 47, 49
Is the execution of the main routine of the program,
Reference numerals 44, 46, and 48 are subroutines called from the main routine, and 45 is a subroutine called from the subroutine. The command branching to the subroutine is represented by JSR, and the command returning from the subroutine is represented by RET. Further, the character string following JSR represents the name of the subroutine. That is, 43 J
In SR, the subroutine Pb (44) is called, and in 44, the subroutine Pc (45) is called. In this way, by calling a subroutine from the slave mode execution state at the time of execution, the execution state shifts.

Next, the configuration of the auxiliary processing device for performing such execution control will be described with reference to FIG. In FIG. 5, reference numeral 51 is a counter that holds the storage address of the word next to the command currently being executed when in the master mode execution state, and is automatically updated in the master mode execution state. Reference numeral 52 is a command register in which the command stored in the memory designated by the counter 51 is read and stored. Reference numeral 53 is a command register that stores a command to be processed in the slave mode execution state, and is written from the outside. Reference numeral 54 is a selector that selects and outputs the contents of the command register 52 or 53 according to the value of a flag (FLAG) 55 indicating the current execution state. That is, the selector 54, when the value of FLAG 55 is 0, indicates the slave mode execution state, outputs the contents of the command register 53, and when the value is 1, indicates the master mode execution state, and outputs the contents of the command register 52. To do. An execution control unit 56 interprets and executes the command supplied from the selector 54.

The inside of the execution control unit 56 is composed of three blocks. Reference numeral 56a is an operation execution unit that interprets commands and at the same time performs numerical operations by the ALU and updates of various registers.
A stack control unit that controls writing to and reading from the stack when executing the return from the subroutine, 56c is F
This is a flag inspection unit that inspects the value of LAG 55 and notifies the execution unit. Reference numeral 57 denotes a stack, which is composed of an address stack 57a and a flag stack 57b.

The change processing of the execution state in the auxiliary processing apparatus having the above configuration will be described with reference to the flowcharts of FIGS. 6 and 7. 6 and 7 are flowcharts for explaining the processing of the JSR and RET commands described in FIG. 4, respectively.

First, the processing of the JSR command will be described with reference to FIG. In step 61, the value of FLAG 55 is stored in the flag stack 57b by the stack control unit 56b. In step 62, the contents of the counter 51, which is the return address, that is, the start address of the command to be executed next to the currently executed JSR is the address stack 57.
It is stored in a. In step 63, the value of FLAG is inspected by the flag inspection unit 56c, and if FLAG = 1, it means that the master mode is being executed, and the routine proceeds to step 65. If FLAG = 0 in the inspection of step 63, it means that the slave mode is in the active state, and therefore the process goes to step 64, FLAG is updated to 1 and the process goes to step 65. In step 65, the branch destination address is stored in the counter 51. The JSR command is processed as described above, and the execution state after execution of the JSR command is always the master mode execution state.

Next, the processing of the RET command will be described with reference to FIG. In step 71, the return address is read from the address stack 57a. At step 72, the value of FLAG is read from the flag stack 57b.
In step 73, the FLAG read in step 72
Is checked by the flag checking unit 56c, and if it is 1, the procedure goes to step 74, and the return address read in step 71 is stored in the counter 51. If the value is 0 in step 73, the flow proceeds to step 75, and FLAG 55 is updated to 0. That is, the execution state after the processing of step 75 is the slave mode execution state. After the processing of step 74, the execution state remains the master mode execution state.

As described above, the execution mode can be changed at the time of execution by executing the JSR command and the RET command. This provides flexibility in the system configuration of the computer system. That is, by operating the auxiliary processing device in the master mode execution state, the host processor does not need to send a command to the auxiliary processing device thereafter, and the load on the host processor can be reduced.

[0012]

However, in the above-described conventional configuration, since two types of information, FLAG and return address, are stored in the stack, a large stack capacity is required and the number of memory accesses increases. Therefore, there is a problem that high-speed processing cannot be performed.

An object of the present invention is to solve the above-mentioned problems of the prior art, and an object thereof is to provide an auxiliary processing device capable of high-speed processing with a small stack capacity.

[0014]

In order to achieve the above object, the present invention provides a first storage means for holding a command written from the outside and an address in the memory for reading the memory. A counting unit whose return address is automatically updated so as to indicate a start address of a command arranged next to the read command; and a command which is read by the counting unit and is stored in the memory. The second storage means, the third storage means for holding selection information for deciding which command of the first storage means and the second storage means to be selected, and the third storage means. Corresponding to the value, the first storage means and the second storage means
Selecting means for selecting and outputting any one of the storing means, a stack for storing the return address designated by the counting means or a predetermined specific value, and the information supplied from the selecting means for interpreting and returning. When the mode in which the address is unnecessary, the specific value is stored in the stack, and in the mode in which the return address is required, the return address is stored in the stack, and it is determined whether or not the specific value is stored. By doing so, execution control means for executing processing corresponding to each mode is provided.

[0015]

According to the present invention, when the execution control means interprets the information supplied from the selection means and the information is a command for branching to the subroutine, the contents of the third storage means is the first one. If it is a value, the return address of the counting means is stored in the stack, and if the content of the third storage means is a second value, a predetermined specific value is stored in the stack and the third storage means is stored. Is updated to the first value, and after any of these processes, an address is generated from the command supplied from the selecting means, the value is stored in the counting means, and the information supplied from the selecting means is stored. When the command returns from the subroutine, the information is taken out from the stack, and if the information is a predetermined specific value, the contents of the third storage means are updated to the second value, and the information taken out from the stack is Predetermined If the specific value, by storing the address information in the counting means, it is possible to switch the execution state of the third storage means the contents is not necessary to be stored in the stack, and at run faster.

[0016]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of an auxiliary processing device according to an embodiment of the present invention. In FIG. 1, reference numeral 11 is a counter (counting means) for holding the storage address of the word next to the command currently being executed when in the master mode execution state, and is automatically updated in the master mode execution state. To go. Reference numeral 12 is a command register (first storage means) in which the command stored in the memory designated by the counter 11 is read and stored. Reference numeral 13 is a command register (second storage means) in which a command to be processed is stored in the slave mode execution state.
And is written from the outside. A selector (selection means) 14 selects and outputs the contents of the command register 12 or 13 according to the value of a flag (third storage means, FLAG) 15 indicating the current execution state. That is, when the value of FLAG 15 is 0, the selector 14 indicates the slave mode execution state, and outputs the contents of the command register 13, and when the value is 1, it indicates the master mode execution state, and the contents of the command register 12 is output. To do. Reference numeral 16 denotes an execution control unit (execution control means) which interprets and executes the command supplied from the selector 14.

The inside of the execution control unit 16 is composed of three blocks. Reference numeral 16a is an operation execution unit for interpreting commands and at the same time performing numerical operation by the ALU, updating various registers, etc., 16b is a subroutine call,
A stack control unit that controls writing to and reading from the stack when executing a return from a subroutine, 16c is F
A flag inspection unit that inspects the value of the LAG 15 and notifies the operation execution unit 16a , and a return address inspection unit 16d that inspects the return address read from the stack 17. 1
7 is the return address , or the return address is unnecessary
A stack for storing a specific value in the case of FIG.
There is no area for storing FLAG as shown in FIG.

The process of changing the execution state at the time of execution in the auxiliary processing device configured as described above will be described with reference to the flowcharts shown in FIGS. First, the processing of the JSR command will be described with reference to FIG. JSR
The mand process is compared with the process shown in FIG.
Then, the routine 41 receives the JSR command JSR Pa.
When taken, the routine 43 calls the JSR command JSR P
When receiving b, the routine 44 calls the JSR command J
Upon receipt of SR Pc and in routine 47 JS
Start when R command JSR Pd is received
Processing. This JSR command processing starts
Then, in step 21, the value of FLAG15 is flagged.
Inspected by the inspection unit 16c, and if FLAG = 1, master
This is called the mode execution state, and this mode returns
It is a mode that requires a dress. This is in the processing of Figure 4
Routine 44 receives the JSR command JSR Pc
It is equivalent to when In this case, go to step 22.
Ku. In step 22, the contents of the counter 11, that is, the present
The command placed next to the JSR command JSR Pc being executed.
Mand start address (this is the "return address")
Is written to the stack 17. In addition, the flag 15
FLAG = 1 remains. After this procedure,
After moving to step 25, the branch destination address Pc
Stored in the computer 11 and branches to the subroutine. to this
More processing is routine 44 to routine 45
Jump to processing FLAG = in step 21
If it is 0, it means the slave mode execution state.
This mode does not require a return address.
It This is performed by the routine 41 in the process of FIG.
When receiving Mand JSR Pa, in routine 43
When a JSR command JSR Pb is received and
Received the JSR command JSR Pd on the command line 47.
Sometimes equivalent. In this case, go to step 23. Su
In step 23, the return address is unnecessary, so
The specified value 0, which is a predetermined value, is stored in the stack 17.
Then, in step 24, FLAG15 is updated to 1. So
Then, the process proceeds to step 25, and the branch destination address is
Stored in the computer 11 and branches to the subroutine. Coun
The branch destination address stored in data 11 depends on each routine.
Is Pa, Pb, Pd, and a branched subroutine process
Are routine 42, routine 44 and routine , respectively.
48.

Next, the processing of the RET command will be described with reference to FIG. At step 31, the return address is fetched from the stack 17. In step 32, the value of the return address extracted in step 31 is inspected by the return address inspecting unit 16d, and if the value is other than 0 which is a specific value, the process proceeds to step 33 and the return address (the above-mentioned
In the case, it is placed after the JRS command JSR Pc.
The start address of the written command is stored in the counter 11.
To be done. As a result, in the process of FIG.
The routine 46 and the processing that has been returned from 5 are started.
It This is a subroutine in the same master mode.
This is the process of returning from Chin. On the other hand, inspection in step 32
If the value is 0, go to step 34 and set FLAG1
5 is updated to 0. This allows the process to be in master mode
Is switched to the slave mode from routine 42
To routine 43, routine 46 to routine 4
Return to 7 and return from routine 48 to routine 49
Homecoming is done.

As described above, according to the above-described embodiment, the execution state can be changed at high speed at the time of execution by executing the JSR command and the RET command with simple control.

In the above embodiment, the check value of the return address is set to 0 as a specific value, but it goes without saying that this value may be any value as long as it is a specific value.

[0022]

As described above, according to the present invention, the execution control means interprets the information supplied from the selection means, and when the return address is in a mode where the return address is unnecessary, a predetermined specific value is stored in the stack. If a mode that requires storing a return address is stored, the return address is stored in the stack, and the process corresponding to each mode is executed by determining whether or not the above specific value is stored. It is not necessary to store the flag indicating the conventional mode in the stack, the stack capacity can be reduced, and the execution state can be switched at high speed during execution.

[Brief description of drawings]

FIG. 1 is a block diagram of an auxiliary processing device according to an embodiment of the present invention.

FIG. 2 is a flowchart showing a JSR command processing operation in the embodiment.

FIG. 3 is a flowchart showing a RET command processing operation in the embodiment.

FIG. 4 is a time chart for explaining an execution state in a conventional auxiliary processing device.

FIG. 5 is a block diagram of an auxiliary processing device in a conventional example.

FIG. 6 is a flowchart showing JSR command processing operation in a conventional example.

FIG. 7 is a flowchart showing a RET command processing operation in a conventional example.

[Explanation of symbols]

 11 counter (counting means) 12 command register (first storage means) 13 command register (second storage means) 14 selector (selection means) 15 flag (third storage means) 16 execution control unit (execution control means) 16a Operation execution unit 16b Stack control unit 16c Flag inspection unit 16d Return address inspection unit 17 Stack

 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor Chika Onodera 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (72) Hiroshi Uranaka, 1006 Kadoma, Kadoma City, Osaka Matsushita Electric (72) Inventor Katsura Kawakami 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd.

Claims (2)

(57) [Claims] [Claim 1] holds the address in memory, counting the memory is read out, the return address so as to instruct the start address of the disposed next read command command is automatically updated Means, first storage means for reading the command instructed by the counting means from the memory and storing it, and a command written from the outside.
A second storage means to be held , and a second storage means to be held in the first storage means.
Command processing that requires a return address and the second
Stored in the storage means of the
And a third storage means for holding selection information for deciding which of the command processing and the command processing should be selected;
In response to the value stored in the storage means, and selecting means for selecting and outputting one of said first memory means and said second storage means, has been instructed by said counting means
Command placed next to the currently executing command
Start address is a return address, and a stack for storing a specific value determined in advance was or interprets the information supplied from the selecting means, the return address is the specific value when the unnecessary mode Is stored in the stack, the return address is stored in the stack when the mode requires a return address, and the processing corresponding to each mode is performed by determining whether or not the specific value is stored. An auxiliary processing device having an execution control means for executing the execution. 2. The execution control means interprets the information supplied from the selection means, and when the information is a command for branching to a subroutine, counting is performed if the content of the third storage means is the first value. The return address of the means is stored in the stack, and if the content of the third storage means is the second value, a predetermined specific value is stored in the stack and the third value is stored in the stack.
Updating the contents of the storage means to a first value, generating an address from the command supplied from the selecting means after any one of the processing, and storing the value in the counting means; When the information supplied from the means is a command for returning from the subroutine, the information is taken out from the stack, and if the information is the predetermined specific value, the content of the third storage means is changed to the second value. 2. The auxiliary processing device according to claim 1, further comprising a function of storing the address information in the counting means if the information updated from the stack is not the specific value.