JPS58213321A - Transferring method of data - Google Patents

Abstract

PURPOSE:To attain data transfer to all modules with only one transfer operation, by switching a confirmation response line when a common address is designated, in a data transferring method between plural modules. CONSTITUTION:An address discriminating modules A-N or address data to all the modules A-N is added as the address data. The logic of the confirmation response signal is converted from the negative to the positive logic based on the address to the transfer to all the modules A-N at the modules A-N so as to produce the confirmation response signal on a line 3 when the confirmation response confirming signal is transmitted from all the modules A-N, allowing to confirm the completion of data transfer to all the modules A-N.

Description

[Detailed Description of the Invention] The present invention provides a plurality of central processing units (hereinafter referred to as CPUs).
The present invention relates to a data transfer method between modules in a multiprocessor system in which existing modules are connected via a common bus.

When data is transferred from one module to another using an asynchronous common bus, the transfer destination module and its address are placed on the address bus, and data is placed on the data bus for transfer. By the way, in the conventional data transfer, data is transferred between a pair of modules in all the modules. Therefore, even when the same data is to be transferred from one module to all other modules, the conventional data transfer method has the drawback that it is necessary to transfer the data to each module in sequence, which takes time.

The present invention was made in view of the problems of the conventional data transfer method, and even when the same data is transferred to all modules, just one transfer masterpiece is required, as in the case of data transfer to one module. This provides a data transfer method that can be transferred using .

The basic H& of the present invention is to add an address for each module as address data or a separate address when transferring data to all modules, and on the module side, add an address for transferring data to all modules. Based on this, the logic of the acknowledgment signal is converted from negative logic to positive logic, and when the acknowledgment signal is sent from all modules, an acknowledgment signal is generated on the line, and data transfer to all modules is completed. The reason is that I tried to confirm this.

The data transfer method of the present invention will be explained below by way of example with reference to the drawings. Figure 1 shows the overall configuration of a multiprocessor system, in which modules A, B, C...
- N is commonly connected to the common address bus 1, data bus 2 and other control lines 3. Each module A, B,
C...N are interfaces 4A and 4B each having the same =a inside.

4C-...4N and CPU 5A, 5B, 5C...5N
and internal memory 6A.

It has 6B, 6C...6N. The other control lines 8 are an address strobe signal indicating that the address on the address bus 1 is valid, and a cheater strobe signal DS indicating that the data on the bus 2 is valid.
,! These are the signal lines for the J-dry drive signal q R7ζ and the acknowledgment signal ACK for notifying completion of data reception.

Next, FIG. 2 is a block diagram showing the circuit configuration of the interface 4B of module B. Although FIG. 2 shows the interface 4B, the same applies to the interfaces of other modules. In this figure, the address bus 1 has two types of address decoders 10 and 11.
is connected. Address decoders 10.11 decode the upper bits of the address bus. In the present invention, the address data carried on the address bus consists of an upper bit part Y indicating the transfer destination module and a lower bit part X indicating the address of the internal memory 6 in each module, as shown in FIG. 3(a). I will always have it. The upper bit part X also contains predetermined data α when data is to be transferred to all □ modules, and data of an address indicating that module when data is to be transferred to an individual module. Therefore, address decoders 10 and 11 of interface 4B of module B decode this all-module transfer data α and module B transfer data b, respectively.
The outputs are applied to AND circuits 12 and 18, respectively. Address strobe signal AS is applied to each address decoder 10.11 to provide timing for decoding.

The output of the address decoder 10 is also applied to an AND circuit 18 via an inverter 14.

On the other hand, theta strobe signal DS is applied to an AND circuit 12 and a delay circuit 16 via an inverter 15. The Tilley circuit 16 is the internal memory 6B of module B.
This is a circuit for securing time for reading data into the 2nd circuit, and provides an output to the AND circuit 12 via the AND circuit 13 and the inverter 17 after the reading is completed. The outputs of the AND circuits 12 and 18 are applied to the OR circuit 18, and the logical OR output thereof is applied to the control line 3 via the NAND circuit 19 as an acknowledgment signal ACK.

Next, this data transfer method will be explained while referring to the time chart of Figure 4 as ib=. Now, if you want to transfer data from module A to module B, module A
places the address ``'b'' indicating the transfer destination module and its internal address x1 on the address bus 1.!8
1N (b) indicates this address data.

Assuming that this point is time tl, module A further transmits the cheetah strobe signal AS to +l as shown in FIG. 4(a).
It indicates that the address data has been established as L" level. Then, each module B.

The address decoders of the interfaces 4B, 4C, . . . , 4N of the interfaces 4B, 4C, . In this case, the address decoder 11 of the interface 4B outputs an "H" output and transmits the "H" output to the AND circuit 13.

Next, as shown in FIG. 4(C), module A sets the read/write signal l to "L" level and requests data writing. Module A then sends the data to be transferred onto data bus 2, and also sends the data strobe DS.
This indicates that the data has been established as L++ level. In module B, a predetermined address x of the internal memory 6B is decoded based on the cheetah strobe signal DS.
The data on the data bus 2 is written, and at the same time, the tiller circuit 16 starts operating via the inverter 15 in the interface 4B. After a sufficient time has elapsed to complete the data writing, the delay circuit 16 outputs an 'H' output at time t2 and supplies it to the AND circuit 13.

As mentioned above, the 6-AND circuit 13 is connected to the address decoder 11.
If t< HI+ ratio output given address decoder 10
An "H" output is also provided from the inverter 14.

Therefore, the AND output is the OR circuit 18 and the NAND circuit 19.
is applied to the control line as an acknowledgment signal ACK. In this case, since it is via the NAND circuit 19, σ
), the signal is at L" level. In this way, the W1 magazine response signal ACK is a common signal and is set to negative logic because a wired-OR connection is made. On the other hand, module A receives this acknowledgment signal ACKfe. The data transfer operation is completed by making the address strobe signal AS, data strobe signal plane, address, and data driver outputs high impedance at time t3.Module B also completes the data transfer operation. When it is detected that the strobe signal DS has gone to the "H" level, the AND circuit F@181E is inverted, so that the acknowledgment signal ACK is set to the "H" level and the data reception operation is completed.

- One module A and all other modules B.

When transferring data to C...N, as shown in FIG. 3(c), the upper bit part Y of the address is set to α, and the lower bit part X is set to an address X2 common to each internal memory. Then, at time t4, this address data is sent to the address bus 1, and the address strobe signal AS is set to +1L" level to indicate that the address has been established. Furthermore, as shown in FIG. is set to "L+" to request data writing, and the data is applied to the data bus 2, and the data strobe signal DS is set to "L" level to indicate that the data has been established.

On the other hand, each module's interface 4B, 4C,...
- At 4N, start tecoding address data. Here, the operation of the interface 4B will be explained below based on FIG. 3, but the same operation is performed for the other interfaces. Now, the top hit part of the address Y
Since the data of is α, address decoder 1 (b),
The It H11 output is given to the AND circuit 12.

Further, the data strobe signal plane is inverted by an inverter 154 and applied to the AND converter 12 as an "H" output. At time t4, the Tilley circuit 15 (1"L 1
Since it is a double level, it is inverted by the inverter 17
+H" output is added to the AND circuit 12. Therefore, the AND circuit 12 outputs an AND output of the +HI" level, and this signal is sent to the NAND circuit 19 via the OR circuit 18 as υ+1.
L Converted to H level signal. The address decoder on one side of each interface outputs an output when the upper bit portion Y is α, so similar operations are performed. Then, at time t5 when the NAND circuit 19 (and the corresponding NAND circuit) of all the modules starts to output "L" level signals, the acknowledgment signal line is connected as shown in FIG. It drops to the "L" level. At this point, the acknowledgment signal line has been switched to positive logic. Next, within each module, the data carried on the data bus is written to the address X2 of the internal memory 6B, 6C, . . . indicated by the lower hit part X of the address data. This data storage progresses simultaneously in all modules except the module that sends the data.
After a period of time sufficient for data writing has elapsed, the delay circuit 16 attains the ``H'' level and transmits the ``L'' level signal to the output circuit fitiN12 via the inverter 17.

Therefore, the AND circuit 12 is inverted to the 1L'' level, and the output of the NAND circuit 19 is also inverted to the H'' level. However, since the mm response signal line is commonly connected to each module, the NAND circuit of all modules is l? When the module reaches the H++ level, the acknowledgment signal ACK goes to the "H" level as shown in FIG. , the acknowledgment signal becomes "H" level due to the signal from the module that completed the writing at the latest.

Module A receives this acknowledgment signal ACK as lH+F.
It is judged that the data has been transferred to all the monitors by reaching the level, and at time t7, the address strobe signal AS, data strobe signal ball, address, and data driver outputs are set to /'% impedance and data transfer operation is started. finish.

Through this procedure, the same data is transferred to each module almost simultaneously.

As described in detail above, according to the present invention, data can be transferred to each module and to all modules by operating the same line by simply reversing the logic of the acknowledgment signal. Therefore, when transferring data to all modules, the transfer time can be significantly reduced compared to conventional methods. Further, since only a small amount of circuit configuration is required for this purpose, the data transfer method according to the present invention can be applied to a conventional multiprocessor system with great ease.

[Brief explanation of drawings]

Figure 1 is a block diagram of a multiprocessor system using the data transfer method according to the present invention, Figure 2 is a blog diagram showing the circuit configuration of the interface, and Figures 3 (a) and (b).
), (c) indicates the structure of the address to be sent,
FIGS. 4(a) to 4(f) are time charts of the common bus and control lines during data transfer. 1... Address bus, 2... Data bus, 4A, 4
]3~4N...Interface, 5A*5to5N-
CPU, 6A. 6Pr-6N...Internal memory, A to N...Module, 1o. 11... Address coater, 12.18... AND circuit, 14°15.17... Inverter, 16...
・Delay circuit, 19... NAND circuit patent applicant Tateishi Electric Co., Ltd.

Claims (1)

[Claims] (1) A data transfer method between a plurality of modules connected via a common address bus and a data bus, each having a central processing unit, in which the address data is an address identifying each module to which the data is transferred or all It contains an address indicating the module, and each module receives data from the data bus when the address of the module is specified, and outputs an acknowledgment signal by the load when the transfer is completed. A data transfer method characterized by switching an acknowledgment signal line to positive logic when a common address is specified on a data bus, and transmitting an acknowledgment signal when data transfer over a data bus is completed.